PCM1730E/2KG4

 SLES021 − NOVEMBER 2001      
             FEATURES D 24-Bit Resolution D Analog Performance (VCC = 5 V): D D D D D D D D D D D D − Dynamic Range: 117 dB (Typically) − SNR: 117 dB (Typically) − THD+N: 0.0004% (Typically) − Full-Scale Output (At Post Amp): 2.2-Vrms Differential Current Output: ±2.48 mA 8× Oversampling Digital Filter: − Stop-Band Attenuation: −82 dB − Pass-Band Ripple: ±0.002 dB Sampling Frequency of 10 kHz to 200 kHz System Clock: 128, 192, 256, 384, 512, or 768 fS With Auto Detect Accepts 16-, 20-, and 24-Bit Audio Data Data Formats: Standard, I2S, and Left-Justified Digital De-Emphasis Soft Mute Zero Flags for Each Output Dual Supply Operation: − 5 V for Analog − 3.3 V for Digital 5-V Tolerant Digital Inputs Small 28-Lead SSOP Package APPLICATIONS D A/V Receivers D DVD Movie Players D SACD Player D HDTV Receivers D Car Audio Systems D Digital Multi-Track Recorders D Other Applications Requiring 24-Bit Audio DESCRIPTION The PCM1730 is a CMOS, monolithic integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters utilize Texas Instruments’ advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1730 provides balanced current outputs, allowing the user to optimize analog performance externally. Sampling rates up to 200 kHz are supported. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPERATING TEMPERATURE RANGE PACKAGE MARKING PCM1730E 28-Lead SSOP 28DB –25°C to 85°C PCM1730E ORDERING NUMBER† PCM1730E PCM1730E/2K † Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of PCM1730E/2K will get a single 2000-piece tape and reel. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
    !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/
#".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ Copyright  2001, Texas Instruments Incorporated www.ti.com 1 
 SLES021 − NOVEMBER 2001 pin assignments SSOP PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RST ZEROL ZEROR LRCK DATA BCK SCKI DGND VDD DEMP0 DEMP1 FMT0 FMT1 FMT2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC3 AGND2 IOUTL− IOUTL+ VCC2 VCC1 VCOM3 IREF VCOM2 VCOM1 AGND1 IOUTR+ IOUTR− MUTE functional block diagram IOUTL+ LRCK DATA BCK Current Segment DAC Serial Input I/F IOUTL− VCOM2 RST Advanced Segment DAC Modulator Digital Filter MUTE FMT0 FMT1 FMT2 IREF Bias and Vref I/V and Filter VCOM1 VCOM3 Function Control I/F IOUTR− DEMP0 DEMP1 Current Segment DAC IOUTR+ System Clock I/V and Filter 2 www.ti.com AGND2 VCC3 AGND1 VCC2 VCC1 Power Supply DGND ZEROL Manager Zero Detect VDD System Clock ZEROR SCKI 
 SLES021 − NOVEMBER 2001 Terminal Functions TERMINAL NAME PIN I/O DESCRIPTION AGND1 18 − Analog ground AGND2 27 − BCK 6 I Analog ground Bit clock input† DATA 5 I DEMP0 10 I Serial audio data input† De-emphasis control‡ DEMP1 11 I De-emphasis control‡ DGND 8 − Digital ground FMT0 12 I FMT1 13 I Audio data format select† Audio data format select† FMT2 14 I Audio data format select† IOUTL– IOUTL+ 26 O L-channel analog current output – 25 O L-channel analog current output + IOUTR– IOUTR+ 16 O R-channel analog current output – 17 O R-channel analog current output + IREF LRCK 21 − 4 I Output current reference bias pin. Connect a 16-kΩ resistor to GND. Left and right clock (fS)† MUTE 15 I RST 1 I Analog output mute control† Reset† SCKI 7 I System clock input† VCC1 VCC2 23 − Analog supply, 5 V 24 − Analog supply, 5 V VCC3 VCOM1 28 − Analog power supply, 5 V 19 − Internal bias decoupling pin VCOM2 VCOM3 20 − Common voltage for I/V 22 − Internal bias decoupling pin VDD ZEROL 9 − Digital supply, 3.3 V 2 O Zero flag for L-channel ZEROR 3 O Zero flag for R-channel † Schmitt-trigger input, 5-V tolerant ‡ Schmitt-trigger input with internal pulldown, 5-V tolerant www.ti.com 3 
 SLES021 − NOVEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: VCC1, VCC2, VCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Supply voltage: VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Supply voltage differences: VCC1, VCC2, and VCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Ground voltage differences: AGND1, AGND2, and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Digital input voltage: LRCK, DATA, BCK, SCKI, DEMP0, DEMP1, FMT0, FMT1, FMT2, RST, and MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V Digital input voltage: ZEROL, ZEROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V) Analog input voltage: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V) Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 s Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 s † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data (unless otherwise noted) PCM1730E PARAMETER TEST CONDITIONS MIN TYP RESOLUTION MAX 24 UNIT Bits DATA FORMAT Standard, I2S, left justified Audio data interface format fS Audio data bit length 16, 20, 24-bits selectable Audio data format MSB first, 2’s complement Sampling frequency 10 System clock frequency 200 kHz 128, 192, 256, 384, 512, 768 fS DIGITAL INPUT/OUTPUT Logic family VIH VIL TTL compatible High-level input logic level 2 Low-level input logic level 0.8 IIH IIL Input logic current (see Note 1) VIN = VDD VIN = 0 V IIH IIL Input logic current (see Note 2) VIN = VDD VIN = 0 V VOH VOL High-level output logic level Low-level output logic level 10 −10 65 100 −10 IOH = −2 mA IOL = 2 mA 2.4 www.ti.com VDC µA A µA A VDC 1 NOTES: 1. Pins 1, 4, 5, 6, 7, 12, 13, 14, and 15: RST, LRCK, DATA, BCK, SCKI, FMT0, FMT1, FMT2, and MUTE 2. Pins 10 and 11: DEMP0, DEMP1 4 VDC VDC 
 SLES021 − NOVEMBER 2001 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data (unless otherwise noted) (continued) PCM1730E PARAMETER TEST CONDITIONS MIN TYP MAX 0.0004% 0.008% UNIT DYNAMIC PERFORMANCE (see Note 3) THD+N Total harmonic distortion plus noise fS = 44.1 kHz fS = 96 kHz VOUT = 0 dB 0.0006% fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range 0.0012% 114 EIAJ, A-weighted, fS = 96 kHz Signal-to-noise ratio 114 EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 192 kHz Channel separation fS = 44.1 kHz fS = 96 kHz Level linearity error fS = 192 kHz VOUT = –110 dB dB 117 EIAJ, A-weighted, fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz 117 117 dB 117 110 115 113 dB 111 ±1 dB 2.45 V DC ACCURACY VCOM2 voltage VCOM2 output current Delta VCOM2 < 5% Gain error Gain mismatch, channel-tochannel Bipolar zero error At BPZ 100 µA ±2 %/FSR ±0.5 %/FSR ±0.5 %/FSR ±2.48 mAp-p mAp-p ANALOG OUTPUT Output current Full scale (−0 dB) Center current BPZ input 0 DIGITAL FILTER PERFORMANCE—FILTER CHARACTERISTICS Pass band ±0.002 dB 0.454 fS −3 dB 0.49 fS Stop band 0.546 fS Pass-band ripple Stop-band attenuation ±0.002 −75 Stop band = 0.546 fS Stop band = 0.567 fS Delay time dB −82 dB 29/fS s ±0.1 De-emphasis error dB dB NOTE 3: Analog performance specifications are measured by audio precision II under averaging mode. At 44.1-kHz operation, measurement bandwidth is limited to 20 kHz. At 96-kHz and 192-kHz operation, measurement bandwidth is limited to 40 kHz. www.ti.com 5 
 SLES021 − NOVEMBER 2001 electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data (unless otherwise noted)(continued) PCM1730E PARAMETER TEST CONDITIONS MIN TYP MAX 3 3.3 3.6 4.75 5 5.25 7 9.8 UNIT POWER SUPPLY REQUIREMENTS VDD VCC Voltage range fS = 44.1 kHz fS = 96 kHz IDD Supply current ICC PD Power dissipation VDC 15 fS = 192 kHz fS = 44.1 kHz 30 fS = 96 kHz fS = 192 kHz 34.5 fS = 44.1 kHz fS = 96 kHz 188 fS = 192 kHz 282 33 46.2 mA 36.5 263 222 mW TEMPERATURE RANGE Operation temperature θJA Thermal resistance −25 28-pin SSOP 85 °C °C/W 100 functional description system clock and reset functions The PCM1730 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCKI input (pin 7). The PCM1730 has a system clock detection circuit, which automatically senses if the system clock is operating at 128 fS to 768 fS. Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multi-clock generator is an excellent choice for providing the PCM1730 system clock. tw(SCKH) 2V System Clock 0.8 V tw(SCKL) System Clock Pulse Cycle Time PARAMETER MIN UNIT System clock pulse width high, tw(SCKH) 5 ns System clock pulse width high, tw(SCKL) 5 ns Figure 1. System Clock Input Timing 6 www.ti.com 
 SLES021 − NOVEMBER 2001 system clock and reset functions (continued) Table 1. System Clock Rates for Common Audio Sampling Frequencies SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1 kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688 36.864 48 kHz 6.144 9.216 12.288 18.432 24.576 96 kHz 12.288 18.432 24.576 36.864 49.152 73.728 192 kHz 24.576 36.864 49.152 73.728 See Note 4 See Note 4 NOTE 4: This system clock rate is not supported for the given sampling frequency. power-on and external reset functions The PCM1730 includes a power-on reset function. Figure 2 shows the operation of this function. The system clock input at SCKI should be active for at least one clock period prior to VDD = 2 V. With the system clock active and VDD > 2 V, the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. The PCM1730 also includes an external reset capability using the RST input (pin 1). This allows an external controller or master reset circuit to force the PCM1730 to initialize to its reset state. Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, which starts the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between PCM1730 power up and system clock activation. In this case, the RST pin should be held at a logic 0 level until the system clock has been activated. The RST pin may then be set to logic 1 state to start the initialization sequence. www.ti.com 7 
 SLES021 − NOVEMBER 2001 functional description (continued) VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Reset Removal Internal Reset 1024 System Clocks System Clock Figure 2. Power-On Reset Timing RST (Pin 36) 50% of VDD t(RST) Reset Reset Removal Internal Reset 1024 System Clocks System Clock PARAMETER Reset pulse width low, t(RST) MIN 20 UNIT ns Figure 3. External Reset Timing audio data interface audio serial interface The audio serial interface for the PCM1730 is comprised of a 3-wire synchronous serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the audio interface’s serial shift register. Serial data is clocked into the PCM1730 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface’s internal registers. LRCK should be synchronous with the system clock. In the event these clocks are not synchronized, the PCM1730 can compensate for the phase difference internally. If the phase difference between LRCK and SCKI is greater than 6-bit clocks (BCK), the synchronization is performed internally. While the synchronization is processing, the analog output is forced to bipolar zero level. The synchronization typically occurs in less than one cycle of LRCK. Ideally, it is recommended that LRCK and BCK be derived from the system clock input or output, SCKI or SCKO. The left/right clock, LRCK, is operated at the sampling frequency, fS. 8 www.ti.com 
 SLES021 − NOVEMBER 2001 audio data formats and timing The PCM1730 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 4. Data formats are selected by using the FMT2 (pin 14), FMT1 (pin 13) and FMT0 (pin 12) as shown in Table 2. All formats require binary 2’s complement, MSB-first audio data. Figure 5 shows a detailed timing diagram for the serial audio interface. Table 2. Audio Data Format Select FMT2 (PIN 14) FMT1 (PIN 13) FMT0 (PIN 12) Low Low Low 16-bit standard format, right-justified Low Low High 20-bit standard format, right-justified Low High Low 24-bit standard format, right-justified FORMAT Low High High High Low Low 24-bit MSB-first, left-justified format 16-bit I2S format High Low High 24-bit I2S format High High Low Reserved High High High Reserved zero detect When the PCM1730 detects that the audio input data in L-channel or R-channel is continuously zero for 1024 fS, the PCM1730 sets ZEROL (pin 2) or ZEROR (pin 3) to high. soft mute The PCM1730 supports mute operation. When MUTE (pin 15) is set to HIGH, both analog outputs are turned to bipolar zero levels by −0.5-dB steps with transition speed of 1/fS per step. This system provides pop-free muting of DAC output. de-emphasis The PCM1730 supports de-emphasis filter performance for sampling frequency 32 kHz, 44.1 kHz, 48 kHz. Sampling frequency is selectable by using DEMP1 (pin 11) DEMP0 (pin 10) as shown in Table 3. Table 3. De-Emphasis Control DEMP1 (PIN 11) DEMP0(PIN 10) DE-EMPHASIS FUNCTION Low Low Disabled Low High 48 kHz High Low 44.1 kHz High High 32 kHz www.ti.com 9 
 SLES021 − NOVEMBER 2001 functional description (continued) (1) Standard Data Format (Right Justified); L-channel = High, R-channel = Low 1/fS LRCK R-Channel L-Channel BCK Audio Data Word = 16 Bit DATA 14 15 16 1 2 MSB 15 16 1 2 15 16 LSB Audio Data Word = 20 Bit DATA 18 19 20 1 2 19 20 1 2 19 20 LSB MSB Audio Data Word = 24 Bit DATA 22 23 24 1 2 23 24 1 2 23 24 LSB MSB (2) Left Justified Data Format: L-channel = High, R-channel = Low 1/fS LRCK R-Channel L-Channel BCK Audio Data Word = 24 Bit DATA 1 2 23 24 MSB 1 2 23 24 1 2 LSB (3) I2S Data Format: L-channel = Low, R-channel = High 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 16 Bit DATA 1 2 MSB 15 16 1 2 1 2 15 16 1 2 1 2 LSB Audio Data Word = 24 Bit DATA 1 2 MSB 23 24 LSB Figure 4. Audio Data Input Formats 10 www.ti.com 23 24 
 SLES021 − NOVEMBER 2001 functional description (continued) 50% of VDD LRCK t(BCH) t(BCL) t(LB) 50% of VDD BCK t(BL) t(BCY) 50% of VDD DATA tsu th PARAMETER MIN UNIT BCK pulse cycle time, t(BCY) 70 ns BCK pulse width low, tw(BCL) 30 ns BCK pulse width high, tw(BCH) 30 ns BCK rising edge to LRCK edge, t(BL) 10 ns LRCK edge to BCK rising edge, t(LB) 10 ns DATA set up time, tsu 10 ns DATA hold time, th 10 ns 50% ±2 bit clock LRCK clock duty Figure 5. Audio Interface Timing www.ti.com 11 
 SLES021 − NOVEMBER 2001 typical connection diagram 5V 15 V −15 V Controller 1 RST 2 VCC3 28 ZEROL AGND2 27 3 ZEROR IOUTL− 26 − L/R Clock (fS) 4 LRCK IOUTL+ 25 + Audio DATA 5 DATA VCC2 24 + Bit Clock 6 BCK VCC1 23 System Clock 7 SCKI VCOM3 22 IREF 21 VCOM2 20 10 DEMP0 VCOM1 19 11 DEMP1 AGND1 18 12 FMT0 IOUTR+ 17 13 FMT1 IOUTR− 16 − 14 FMT2 MUTE 15 + 3.3 V + 8 DGND 9 VDD PCM1730E + − + + − + − + + − Analog Output Stage NOTE: Regarding R/C values for analog output stage, see Figure 9. Figure 6. Typical Application Circuit for Standard PCM Audio Operation 12 VOUT L-Channel www.ti.com VOUT R-Channel 
 SLES021 − NOVEMBER 2001 analog outputs 5V VCC3 PCM1730E 28 AGND2 27 IOUTL− 26 IOUTL+ 25 VCC2 24 VCC1 23 VCOM3 22 IREF 21 VCOM2 20 VCOM1 19 AGND1 18 IOUTR+ 17 IOUTR− 16 MUTE C13 0.1 µF R15 + R11 10 µF − C11 R13 + + R16 C15 R14 − + VOUT L-Channel R17 − + 10 µF R1 16 kΩ C17 10 µF + C12 R18 C16 R12 C14 10 µF + C23 R25 R21 − C21 15 C27 R23 + + R26 C25 R24 − + VOUT R-Channel R27 − C22 R28 C26 R22 C24 NOTE: Example R/C values for fC 45 kHz R11–R18, R21–R28: 620 Ω, C11, C12, C21, C22: not populated, C13, C14, C23, C24: 5600 pF, C15, C25: 8200 pF, C16, C17, C26, C27: 1800 pF Figure 7. Typical Application for Analog Output Stage analog output level and I/V converter The signal level of DAC current output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is ±2.48 mAp-p at 0 dB (full scale). The voltage output of the I/V converter is given by following equation: VOUT = ±2.48 mAp−p × Rf Here, Rf is the feedback resistor in the I/V conversion circuit, R11, R12, R21, R22 on typical application circuit. The common level of the I/V conversion circuit must be same as common level of DAC IOUT which is given by VCOM2 reference voltage, which is 2.48 V dc typically. The noninverting inputs of the op amps shown in the I/V circuits are connected to VCOM2 to provide the common bias voltage. www.ti.com 13 
 SLES021 − NOVEMBER 2001 op amp for I/V converter circuit OPA627BP/BM or NE5534 type op amp is recommended for I/V conversion circuit to obtain specified audio performance. Dynamic performance such as gain bandwidth, settling time and slew rate of op amp gives audio dynamic performance at I/V section. Input noise specification of op amp should be considered to obtain 120 dB S/N ratio. analog gain by balanced amp The I/V converters are followed by balanced amplifier stages, which sum the differential signals for each channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a second-order low pass filter function, which band limits the audio output signal. The cutoff frequency and gain are given by the external R and C component values. In this case, the cutoff frequency is 45 kHz with a gain of 1. The output voltage for each channel is 6.2 Vp-p, or 2.2 Vrms. reference current resistor As shown in the analog output application circuit, there is a resistor connected from IREF (pin 21) to analog ground, designated as R1. This resistor sets the current for the internal reference circuit. The value of R1 must be 16 kΩ ±1% in order to match the specified gain error shown in the specifications table. theory of operation Upper 6 Bit ICOB Decoder 0−62 Level 0−66 Advanced DWA Digital Input 24 Bit 8 fS MSB and Lower 18 Bit 3rd-Order 5-Level Sigma-Delta Current Segment DAC Analog Output 0−4 Level Figure 8. Advanced Segments DAC The PCM1730 utilizes Texas Instruments’ newly developed advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1730 provides balanced current outputs, allowing the user to optimize analog performance externally. Digital input data via digital filter separates into the upper 6 bits and lower the 18 bits. The upper 6 bits are converted to ICOB (inverted complementary offset binary) code. The lower 18 bits associated with the MSB are processed by five level third order delta-sigma modulator operated at 64 fS. The one level of the modulator is equivalent to the 1 LSB of the above code converter. The data groups processed in the ICOB converter and third order delta-sigma modulator are summed together to be created over the 64 level digital code, and then processed in DWA (data weighted averaging) to reduce noise produced by element mismatch. The data of over 64 level via DWA is converted to analog output in the differential current segment portion. This architecture has overcome the various drawbacks of conventional multi-bit and also achieves excellent dynamic performance. considerations for application circuit PCB layout guidelines A typical PCB floor plan for the PCM1730 is shown in Figure 9. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1730 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board. 14 www.ti.com 
 SLES021 − NOVEMBER 2001 PCB layout guidelines (continued) Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the D/A converters. In cases where a common 5-V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 10 shows the recommended approach for single-supply applications. bypass and decoupling capacitor requirements Various-sized decoupling capacitors can be used, with no special tolerances being required. All capacitors should be located as close to the appropriate pins of the PCM1730 as possible to reduce noise pickup from surrounding circuitry. Aluminum electrolytic capacitors that are designed for hi-fi audio applications are recommended for larger values, while metal-film or monolithic ceramic capacitors are used for smaller values. I/V section I/V conversion circuit by op amp IC and feedback resistor should achieve excellent performance of the PCM1730. To obtain 0.0004% THD+N, 117-dB signal-to-noise ratio audio performance, THD+N and input noise performance by the op amp IC should be considered, especially if the input noise of the op amp directly gives output noise level of the application. The IOUT– pin on the PCM1730 and the inverted input on the I/V amp should be connected as short distance. post LPF design Out-band noise level and attenuated sampling spectrum level are much lower than typical delta-sigma type DAC due to the combination of a high-performance digital filter and advanced segment DAC architecture. Secondorder or third-order post LPF is recommended as post LPF of the PCM1730. Cutoff frequency of post LPF is depends on applications to that there are many sampling rate operation such as fS = 44.1 kHz on CDDA, fS = 96 kHz on DVD−M, fS = 192 kHz on DVD−A. Digital Power +VD DGND Analog Power AGND +5VA +VS −VS REG VCC Digital Logic and Audio Processor VDD DGND Output Circuits PCM1730 Digital Ground AGND Digital Section Analog Section Analog Ground Return Path for Digital Signals Figure 9. Recommended PCB Layout www.ti.com 15 
 SLES021 − NOVEMBER 2001 Power Supplies RF Choke or Ferrite Bead 5V AGND +VS −VS REG VCC VDD VDD DGND PCM1730 Output Circuits Digital Ground AGND Digital Section Analog Section Figure 10. Single-Supply PCB Layout 16 www.ti.com Common Ground 
 SLES021 − NOVEMBER 2001 TYPICAL CHARACTERISTICS digital filter de-emphasis off AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 3 0.003 VCC = 5 V VDD = 3.3 V TA = 25°C −20 2 0.002 VCC = 5 V VDD = 3.3 V TA = 25°C −60 Amplitude − dB Amplitude − dB −40 −80 −100 1 0.001 0 −1 −0.001 −120 −2 −0.002 −140 −160 0 1 2 3 4 −3 −0.003 0.0 Frequency [x fs] 0.1 0.2 0.3 0.4 0.5 Frequency [x fs] Figure 12 Figure 11 † All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) www.ti.com 17 
 SLES021 − NOVEMBER 2001 TYPICAL CHARACTERISTICS de-emphasis error DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 VCC = 5 V VDD = 3.3 V fS = 32 kHz TA = 25°C −1 0.3 De-emphasis Error − dB De-emphasis Level − dB −2 VCC = 5 V VDD = 3.3 V fS = 32 kHz TA = 25°C 0.4 −3 −4 −5 −6 −7 0.2 0.1 −0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 0 2 4 f − Frequency − kHz 6 10 12 DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 VCC = 5 V VDD = 3.3 V fS = 44.1 kHz TA = 25°C −1 VCC = 5 V VDD = 3.3 V fS = 44.1 kHz TA = 25°C 0.4 0.3 De-emphasis Error − dB −2 −3 −4 −5 −6 −7 0.2 0.1 −0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 16 18 20 f − Frequency − kHz 0 2 4 6 8 10 12 14 16 18 f − Frequency − kHz Figure 15 Figure 16 † All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) 18 14 Figure 14 Figure 13 De-emphasis Level − dB 8 f − Frequency − kHz www.ti.com 20 
 SLES021 − NOVEMBER 2001 TYPICAL CHARACTERISTICS de-emphasis error (continued) DE-EMPHASIS ERROR vs FREQUENCY DE-EMPHASIS LEVEL vs FREQUENCY 0.5 0 VCC = 5 V VDD = 3.3 V fs = 48 kHz TA = 25°C De-emphasis Level − dB −2 VCC = 5 V VDD = 3.3 V fS = 48 kHz TA = 25°C 0.4 0.3 De-emphasis Error − dB −1 −3 −4 −5 −6 −7 0.2 0.1 −0.0 −0.1 −0.2 −0.3 −8 −0.4 −9 −0.5 −10 0 2 4 6 8 10 12 14 16 18 20 0 22 2 4 6 8 10 12 14 16 18 20 22 f − Frequency − kHz f − Frequency − kHz Figure 17 Figure 18 analog dynamic performance TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE 0.20 0.0020 THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE VDD = 3.3 V TA = 25°C 0.15 0.0015 0.10 0.0010 fS = 96 kHz 0.05 0.0005 fS = 44.1 kHz 0.00 0.0000 4.50 4.75 5.00 5.25 5.50 0.20 0.0020 VCC = 5 V VDD = 3.3 V 0.15 0.0015 0.10 0.0010 fS = 96 kHz 0.05 0.0005 fS = 44.1 kHz 0.00 0.0000 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VCC − Supply Voltage − V Figure 20 Figure 19 † All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) www.ti.com 19 
 SLES021 − NOVEMBER 2001 TYPICAL CHARACTERISTICS analog dynamic performance (continued) DYNAMIC RANGE vs SUPPLY VOLTAGE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 120 120 VDD = 3.3 V TA = 25°C VCC = 5 V VDD = 3.3 V 119 Dynamic Range − dB Dynamic Range − dB 119 fS = 96 kHz 118 fS = 44.1 kHz 117 116 4.50 fS = 44.1 kHz 118 fS = 96 kHz 117 4.75 5.00 5.25 116 −50 5.50 VCC − Supply Voltage − V −25 Figure 21 50 75 100 SNR vs FREE-AIR TEMPERATURE 120 120 VCC = 5 V VDD = 3.3 V TA = 25°C VCC = 5 V VDD = 3.3 V 119 119 118 SNR − dB SNR − dB 25 Figure 22 SNR vs SUPPLY VOLTAGE fS = 44.1 kHz fS = 96 kHz 117 116 4.50 0 TA − Free-Air Temperature − °C 4.75 5.00 118 fS = 44.1 kHz fS = 96 kHz 117 5.25 5.50 116 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C VCC − Supply Voltage − V Figure 23 Figure 24 † All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) 20 www.ti.com 
 SLES021 − NOVEMBER 2001 TYPICAL CHARACTERISTICS analog dynamic performance (continued) CHANNEL SEPARATION vs SUPPLY VOLTAGE CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 118 117 116 Channel Separation − dB Channel Separation − dB 117 118 VDD = 3.3 V TA = 25°C fS = 44.1 kHz 115 114 113 fS = 96 kHz 112 111 110 4.50 VCC = 5 V VDD = 3.3 V 116 fS = 44.1 kHz 115 114 fS = 96 kHz 113 112 111 4.75 5.00 5.25 5.50 VCC − Supply Voltage − V 110 −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C Figure 25 Figure 26 † All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) www.ti.com 21 
 SLES021 − NOVEMBER 2001 TYPICAL CHARACTERISTICS −60-dB OUTPUT SPECTRUM −60-dB OUTPUT SPECTRUM 0 0 VCC = 5 V VDD = 3.3 V fS = 44.1 kHz TA = 25°C BW = 20 kHz −20 −40 −60 Amplitude − dB Amplitude − dB −40 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 0 5 VCC = 5 V VDD = 3.3 V fS = 44.1 kHz TA = 25°C BW = 100 kHz −20 10 15 −160 20 0 20 f − Frequency − kHz 40 60 80 100 f − Frequency − kHz Figure 27 Figure 28 THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs INPUT LEVEL 100 VCC = 5 V VDD = 3.3 V TA = 25°C 10 1 fS = 96 kHz 0.1 fS = 44.1 kHz 0.010 0.001 0.0001 −100 −80 −60 −40 −20 0 Input Level − dBFS Figure 29 † All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) 22 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PCM1730E ACTIVE SSOP DB 28 47 RoHS & Green NIPDAU Level-1-260C-UNLIM PCM1730E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of