PCM3001E/2KG4

          PCM3000 PCM3001 SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT FEATURES • • • • • • • • Monolithic 18-Bit ∆Σ ADC and DAC 16- or 18-Bit Input/Output Data Accepts Seven Alternate Formats Stereo ADC: – Single-Ended Voltage Input – 64× Oversampling Digital Filter • Pass-Band Ripple: ±0.05 dB • Stop-Band Attenuation: –65 dB – High Performance: • THD+N: –88 dB • SNR: 94 dB • Dynamic Range: 94 dB – Digital High-Pass Filter Stereo DAC – Single-Ended Voltage Outut – Analog Low-Pass Filter – 8× Oversampling Digital Filter • Pass-Band Ripple: ±0.17 dB • Stop-Band Attenuation: 35 dB – High Performance: • THD+N: –90 dB • SNR: 98 dB • Dynamic Range: 97 dB Special Features (PCM3000) – Digital De-Emphasis – Digital Attenuation (256 Steps) – Soft Mute – Digital Loopback Sample Rate: 4 kHz to 48 kHz System Clock: 256 fs, 384 fs, 512 fs Lch In Analog Front-End Rch In Lch Out Rch Out Low-Pass Filter and Output Buffer Delta-Sigma Modulator Multilevel Delta-Sigma Modulator • • Single 5-V Power Supply Small Package: SSOP-28 APPLICATIONS • • • • • • • • Sampling Keyboards Digital Mixers Mini-Disk Recorders Hard-Disk Recorders Karaoke Systems DSP-Based Car Stereo DAT Recorders Video Conferencing DESCRIPTION The PCM3000/3001 is a low-cost, single-chip stereo audio codec (analog-to-digital and digital-to-analog converter) with single-ended analog voltage input and output. Both ADCs and DACs employ delta-sigma modulation with 64-times oversampling. The ADCs include a digital decimation filter and the DACs include an 8-times oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. The PCM3000/3001 operates with left-justified, right-justified, I2S or DSP data formats. The PCM3000 can be programmed with a three-wire serial interface for special features and data formats. The PCM3001 can be pin-programmed for data formats. The PCM3000 and PCM3001 are fabricated using a highly advanced CMOS process and are available in a small 28-pin SSOP package. The PCM3000/3001 are suitable for a wide variety of cost-sensitive consumer applications where good performance is required. Digital Decimation Filter Digital Interpolation Filter Digital Out Serial Interface and Mode Control Digital In Mode Control System Clock B0006-03 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2004, Texas Instruments Incorporated PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Input Logic VIH (1) VIL (1) IIN (2) IIN (3) VIH (4) VIL (4) IIN (4) 2 Input logic level 0.8 ±1 Input logic current –120 0.64 VDD Input logic level VDC µA VDC 0.28 VDD ±40 Input logic current µA Output Logic VOH (5) VOL (5) VOH (6) VOL (6) Output logic level Output logic level IOUT = –1.6 mA 4.5 IOUT = 3.2 mA 0.5 IOUT = –3.2 mA 4.5 IOUT = 3.2 mA VDC 0.5 Clock Frequency fS 4 (7) 44.1 48 256 fS 1.024 11.2896 12.288 384 fS 1.536 16.9344 18.432 512 fS 2.048 22.5792 24.576 Sampling frequency System clock frequency kHz MHz ADC CHARACTERISTICS Resolution 18 Bits DC Accuracy Gain mismatch, channel-to-channel ±1 ±5 Gain error ±2 ±5 ±20 Gain drift (1) (2) (3) (4) (5) (6) (7) (8) 2 % of FSR ppm of FSR/°C Bipolar zero error High-pass filter off (8) ±1.7 % of FSR Bipolar zero drift High-pass filter off (8) ±20 ppm of FSR/°C Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt-trigger input) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt-trigger input, 70-kΩ internal pullup resistor) Pin 20: XTI Pins 19, 22: DOUT, CLKIO Pin 21: XTO Refer to Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies. High-pass filter disabled (PCM3000 only) to measure dc offset PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX f = 1 kHz, VIN = –0.5 dB –88 –80 f = 1 kHz, VIN = –60 dB –31 UNIT Dynamic Performance (9) THD+N dB Dynamic range f = 1 kHz, A-weighted 90 94 dB Signal-to-noise ratio f = 1 kHz, A-weighted 90 94 dB 88 92 dB Channel separation Digital Filter Performance Pass band 0.454 fS Stop band 0.583 fS Hz ±0.05 Pass-band ripple Stop-band attenuation –65 Delay time (latency) Hz dB dB 17.4/fS s 0.019 fS mHz Digital High-Pass Filter Response Cutoff frequency –3 dB ANALOG INPUT Voltage range 2.9 Vp-p Center voltage 0 dB (full scale) 2.1 VDC Input impedance 15 kΩ 170 kHz 18 Bits Antialiasing Filter Cutoff frequency –3 dB, CEXT = 470 pF DAC CHARACTERISTICS Resolution DC Accuracy Gain mismatch, channel-to-channel ±1 ±5 % of FSR Gain error ±1 ±5 % of FSR Gain drift ±20 ppm of FSR/°C Bipolar zero error ±1 % of FSR Bipolar zero drift ±20 ppm of FSR/°C Dynamic Performance(9) THD+N VOUT = 0 dB (full scale) –90 VOUT = –60 dB –34 –80 dB Dynamic range EIAJ A-weighted 90 97 dB Signal-to-noise ratio (idle channel) EIAJ A-weighted 92 98 dB 90 95 dB Channel separation Digital Filter Performance Pass band Stop band 0.445 fS 0.555 fS Hz ±0.17 Pass-band ripple Stop-band attenuation Delay time (9) Hz –35 dB dB 11.1/fS s fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation or measurement. 3 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Voltage range Center voltage Load impedance AC load 0.62 VCC Vp-p 0.5 VCC VDC 5 kΩ Analog Low-Pass Filter Frequency response f = 20 kHz –0.16 dB POWER SUPPLY REQUIREMENTS VCC 4.5 Voltage range VDD ICC, IDD (10) 4.5 5 5.5 VDC VDC 5 5.5 Supply current VCC = VDD = 5 V 32 50 mA Power dissipation VCC = VDD = 5 V 160 250 mW °C TEMPERATURE RANGE TA Operation –25 85 Tstg Storage –55 125 θJA Thermal resistance °C °C/W 100 (10) With no load on XTO and CLKIO PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE PCM3000E PACKAGE MARKING PCM3000E 28-pin SSOP DB PCM3001E PCM3001E ORDERING NUMBER TRANSPORT MEDIA QUANTITY PCM3000E Rails 47 PCM3000E/2K Tape and reel 2000 PCM3001E Rails 47 PCM3001E/2K Tape and reel 2000 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage: VDD, VCC1, VCC2 –0.3 V to 6.5 V Supply voltage differences ±0.1 V GND voltage differences ±0.1 V Digital input voltage Analog input voltage Power dissipation Input current (any pins except supplies) Operating temperature Storage temperature Lead temperature, soldering Package temperature (IR reflow, peak) 4 –0.3 to VDD + 0.3 V, < 6.5 V –0.3 to VCC1, VCC2 + 0.3 V, < 6.5 V 300 mW ±10 mA –25°C to 85°C –55°C to 125°C 260°C, 5 s 235°C PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Analog supply voltage, VCC1, VCC2 4.5 5 5.5 VDC Digital supply voltage, VDD 4.5 5 5.5 VDC Analog input voltage, full scale (–0 dB) 2.9 Digital input logic family Digital input clock frequency Analog output load resistance System clock Sampling clock 8.192 24.576 MHz 32 48 kHz 5 kΩ Analog output load capacitance 50 Digital output load capacitance 10 Operating free-air temperature, TA Vp-p TTL –25 pF pF 85 °C 5 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 PIN CONFIGURATION—PCM3000/3001 PCM3000 (TOP VIEW) VINL VCC1 AGND1 VREFL VREFR VINR CINPR CINNR CINNL CINPL VCOM VOUTR AGND2 VCC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PCM3001 (TOP VIEW) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSTB ML MD MC DGND VDD CLKIO XTO XTI DOUT DIN BCKIN LRCIN VOUTL VINL VCC1 AGND1 VREFL VREFR VINR CINPR CINNR CINNL CINPL VCOM VOUTR AGND2 VCC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSTB FMT0 FMT1 FMT2 DGND VDD CLKIO XTO XTI DOUT DIN BCKIN LRCIN VOUTL P0007-01 PIN ASSIGNMENTS—PCM3000 (1) (2) 6 NAME PIN I/O AGND1 3 – ADC analog ground DESCRIPTION AGND2 13 – DAC analog ground BCKIN 17 I Bit clock input (1) CINNL 9 – ADC antialias filter capacitor (–), Lch CINNR 8 – ADC antialias filter capacitor (–), Rch CINPL 10 – ADC antialias filter capacitor (+), Lch CINPR 7 – ADC antialias filter capacitor (+), Rch CLKIO 22 I/O DGND 24 – Digital ground DIN 18 I Data input (1) DOUT 19 O Data output LRCIN 16 I Sample rate clock input (fS) (1) MC 25 I Serial mode control, bit clock MD 26 I Serial mode control, data ML 27 I Serial mode control, strobe pulse RSTB 28 I Reset, active-low (1) (2) VCC1 2 – ADC analog power supply VCC2 14 – DAC analog power supply Buffered oscillator output or external clock input (1) VDD 23 – Digital power supply VCOM 11 – DAC output common VINL 1 I ADC analog input, Lch VINR 6 I ADC analog input, Rch VOUTL 15 O DAC analog output, Lch VOUTR 12 O DAC analog output, Rch VREFL 4 – ADC input reference, Lch VREFR 5 – ADC input reference, Rch Schmitt-trigger input With 70-kΩ typical internal pullup resistor PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 PIN ASSIGNMENTS—PCM3000 (continued) NAME PIN I/O XTI 20 I Oscillator input DESCRIPTION XTO 21 O Oscillator output PIN ASSIGNMENTS—PCM3001 (1) (2) NAME PIN I/O AGND1 3 – ADC analog ground DESCRIPTION AGND2 13 – DAC analog ground BCKIN 17 I Bit clock input (1) CINNL 9 – ADC antialias filter capacitor (–), Lch CINNR 8 – ADC antialias filter capacitor (–), Rch CINPL 10 – ADC antialias filter capacitor (+), Lch CINPR 7 – ADC antialias filter capacitor (+), Rch CLKIO 22 I/O DGND 24 – Digital ground DIN 18 I Data input (1) DOUT 19 O Data output FMT0 27 I Audio data format control 0 (1) (2) FMT1 26 I Audio data format control 1 (1) (2) FMT2 25 I Audio data format control 2 (1) (2) LRCIN 16 I Sample rate clock input (fS) (1) RSTB 28 I Reset, active-low (1) (2) VCC1 2 – ADC analog power supply VCC2 14 – DAC analog power supply VDD 23 – Digital power supply VCOM 11 – DAC output common VINL 1 I ADC analog input, Lch VINR 6 I ADC analog input, Rch Buffered oscillator output or external clock input (1) VOUTL 15 O DAC analog output, Lch VOUTR 12 O DAC analog output, Rch VREFL 4 – ADC input reference, Lch VREFR 5 – ADC input reference, Rch XTI 20 I Oscillator input XTO 21 O Oscillator output Schmitt-trigger input With 70-kΩ typical internal pullup resistor 7 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF ADC SECTION All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, VIN = 2.9 Vp-p, and SYSCLK = 384 fS, unless otherwise noted 3 0.006 2 FS 0.004 1 0.002 −25 0 25 50 75 0 100 TA − Free-Air Temperature − °C −60 dB 0.008 3 0.006 2 0.004 1 FS 0.002 4.25 4.50 4.75 5.00 5.25 G002 SNR AND DYNAMIC RANGE vs POWER SUPPLY 44.1 kHz 3 0.008 −60 dB 0.006 2 48 kHz 48 kHz 0.004 1 FS 44.1 kHz 0 256 fS 384 fS 512 fS Dynamic Range − dB THD+N vs SYSTEM CLOCK AND SAMPLING FREQUENCY 4 98 98 96 96 Dynamic Range 94 94 SNR 92 90 4.25 92 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V System Clock G003 Figure 3. 0 5.75 VCC − Supply Voltage − V G001 Figure 2. 0.002 8 5.50 Figure 1. 0.010 THD+N − Total Harm. Dist. + Noise at FS − % 4 Figure 4. 5.50 SNR − Signal-to-Noise Ratio − dB −60 dB 0.008 0.010 THD+N − Total Harm. Dist. + Noise at FS − % 4 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at FS − % 0.010 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N vs POWER SUPPLY THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N vs TEMPERATURE 90 5.75 G004 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF ADC SECTION (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, VIN = 2.9 Vp-p, and SYSCLK = 384 fS, unless otherwise noted THD+N vs OUTPUT DATA RESOLUTION 4 0.008 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at FS − % 0.010 3 −60 dB 0.006 2 FS 0.004 1 0.002 0 16-Bit 18-Bit Resolution G005 Figure 5. TYPICAL PERFORMANCE CURVES OF DAC SECTION All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, and SYSCLK = 384 fS, unless otherwise noted 4 0.008 3 −60 dB 0.006 2 FS 0.004 0.002 −25 1 0 25 50 75 TA − Free-Air Temperature − °C Figure 6. 0 100 0.010 4 0.008 3 −60 dB 0.006 2 0.004 1 FS 0.002 4.25 G006 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V 5.50 THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 THD+N − Total Harm. Dist. + Noise at FS − % THD+N vs POWER SUPPLY THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at FS − % THD+N vs TEMPERATURE 0 5.75 G007 Figure 7. 9 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF DAC SECTION (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, and SYSCLK = 384 fS, unless otherwise noted 3 0.008 48 kHz 0.006 2 −60 dB 48 kHz 44.1 kHz 0.004 1 FS 44.1 kHz 0.002 100 Dynamic Range 384 fS 98 98 SNR 96 96 94 94 92 4.25 0 256 fS 100 512 fS 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V System Clock G008 Figure 8. Figure 9. 0.010 4 0.008 3 −60 dB 0.006 2 FS 0.004 1 0.002 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at FS − % THD+N vs INPUT DATA RESOLUTION 0 16-Bit 18-Bit Resolution G010 Figure 10. 10 5.50 SNR − Signal-to-Noise Ratio − dB 4 Dynamic Range − dB THD+N − Total Harm. Dist. + Noise at FS − % 0.010 SNR AND DYNAMIC RANGE vs POWER SUPPLY THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N vs SYSTEM CLOCK AND SAMPLING FREQUENCY 92 5.75 G009 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted DECIMATION FILTER OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 0 0 −20 Amplitude − dB −100 −40 −60 −150 −80 −200 0 8 16 24 −100 0.0 32 Normalized Frequency [× fS Hz] 0.2 0.4 0.6 0.8 Normalized Frequency [× fS Hz] G011 Figure 11. 1.0 G012 Figure 12. PASS-BAND RIPPLE CHARACTERISTICS 0.2 0.0 Amplitude − dB Amplitude − dB −50 −0.2 −0.4 −0.6 −0.8 −1.0 0.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS Hz] 0.5 G013 Figure 13. 11 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted HIGH-PASS FILTER HIGH-PASS FILTER RESPONSE 0.2 Amplitude − dB 0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 1 2 3 4 Normalized Frequency [× fS/1000 Hz] G014 Figure 14. ANTIALIASING FILTER ANTIALIASING FILTER PASS-BAND FREQUENCY RESPONSE (CEXT = 470 pF, 1000 pF) ANTIALIASING FILTER OVERALL FREQUENCY RESPONSE (CEXT = 470 pF, 1000 pF) 0.2 0 470 pF 470 pF −10 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 1000 pF −0.6 −20 1000 pF −30 −40 −0.8 −1.0 −50 1 10 100 1k 10k 100k f − Frequency − Hz 1 10 100 1k 10k G015 Figure 15. 12 100k 1M 10M f − Frequency − Hz G016 Figure 16. PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted DIGITAL FILTER PASS-BAND RIPPLE CHARACTERISTIC 0.0 −20 −0.2 −40 −0.4 Level − dB Level − dB OVERALL FREQUENCY CHARACTERISTIC 0 −60 −80 −0.6 −0.8 −100 −1.0 0 0.4536 fS 1.3605 fS 2.2675 fS 3.1745 fS 4.0815 fS 0 0.1134 fS f − Frequency − Hz 0.2268 fS 0.3402 fS 0.4535 fS f − Frequency − Hz G017 G018 DE-EMPHASIS FILTER DE-EMPHASIS ERROR (32 kHz) 0 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k f − Frequency − Hz 0 3628 7256 10884 14512 f − Frequency − Hz G019 G020 13 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted DE-EMPHASIS ERROR (44.1 kHz) 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) 0 −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k 0 4999.8375 f − Frequency − Hz 9999.675 14999.5125 G021 G022 DE-EMPHASIS ERROR (48 kHz) 0 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k f − Frequency − Hz 0 5442 10884 16326 21768 f − Frequency − Hz G023 14 19999.35 f − Frequency − Hz G024 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted ANALOG LOW-PASS FILTER INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20 Hz–24 kHz, EXPANDED SCALE) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10 Hz–10 MHz) 10 1.0 5 0 −5 0.5 −10 Level − dB Level − dB −15 0.0 −20 −25 −30 −35 −40 −0.5 −45 −50 −55 −1.0 20 100 1k 10k 24k −60 10 100 1k 10k 100k 1M 10M f − Frequency − Hz f − Frequency − Hz G025 G026 15 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Block Diagram CINPL CINNL (+) VINL Analog Front-End Circuit (−) Decimation and High-Pass Filter Delta-Sigma Modulator LRCIN BCKIN VREFL Serial Data Interface ADC Reference VREFR DIN (−) VINR Analog Front-End Circuit (+) Decimation and High-Pass Filter Delta-Sigma Modulator DOUT CINNR Loop Control CINPR ML(FMT0)(1) VOUTL Analog Low-Pass Filter Multilevel Delta-Sigma Modulator Mode Control Interface DAC VCOM VOUTR Interpolation Filter 8× Oversampling Analog Low-Pass Filter Multilevel Delta-Sigma Modulator MD(FMT1)(1) Interpolation Filter 8× Oversampling Reset Power Supply AGND2 VCC2 AGND1 VCC1 MC(FMT2)(1) RSTB Clock/OSC Manager DGND VDD CLKIO XTO XTI B0004-05 16 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 470 pF CINPL 10 2.2 µF + 1 VINL 9 CINNL 15 kΩ − − 1 kΩ + (+) + 1 kΩ 4 4.7 µF (−) Delta-Sigma Modulator VREFL + VREF S0011-04 Figure 17. Analog Front-End (Single-Channel) PCM AUDIO INTERFACE The four-wire digital audio interface for the PCM3000/3001 is on LRCIN (pin 16), BCKIN (pin 17), DIN (pin 18), and DOUT (pin 19). The PCM3000/3001 can operate with seven different data formats. For the PCM3000, these formats are selected through program register 3 in the software mode. For the PCM3001, data formats are selected by pin-strapping the three format pins. Figure 18, Figure 19, Figure 20 and Figure 21 illustrate the audio data input/output format. Figure 22 shows the audio data input/output timing. The PCM3000/3001 can accept 32, 48, or 64 bit clocks (BCKIN) during one clock of LRCIN. Only formats 0, 2, and 6 can be selected when 32 bit clocks/LRCIN are applied. 17 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 0: FMT[2:0] = 000 DAC: 16-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB ADC: 16-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 3 14 15 16 MSB 1 LSB 2 3 1 14 15 16 MSB LSB FORMAT 1: FMT[2:0] = 001 DAC: 18-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 18 1 2 3 16 17 18 MSB 1 2 3 16 17 18 MSB LSB LSB ADC: 18-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 MSB 3 16 17 18 LSB 1 2 3 16 17 18 MSB 1 LSB T0016-07 Figure 18. Audio Data Input/Output Format (Formats 0 and 1) 18 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 2: FMT[2:0] = 010 DAC: 16-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 16 1 2 3 MSB 14 15 16 1 2 3 MSB LSB 14 15 16 LSB ADC: 16-Bit, MSB-First, Right-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 16 1 2 3 MSB 14 15 16 1 2 3 MSB LSB 14 15 16 LSB FORMAT 3: FMT[2:0] = 011 DAC: 18-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 18 1 2 3 16 17 18 MSB LSB 1 2 3 16 17 18 MSB LSB ADC: 18-Bit, MSB-First, Right-Justified LRCIN Left-Channel Right-Channel BCKIN DOUT 18 1 2 MSB 3 16 17 18 LSB 1 2 3 MSB 16 17 18 LSB T0016-08 Figure 19. Audio Data Input/Output Format (Formats 2 and 3) 19 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 4: FMT[2:0] = 100 DAC: 18-Bit, MSB-First, Left-Justified LRCIN Left-Channel Right-Channel BCKIN DIN 1 2 3 16 17 18 MSB 1 LSB 2 3 1 16 17 18 MSB LSB ADC: 18-Bit, MSB-First, Left-Justified Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 3 16 17 18 MSB 1 LSB 2 3 1 16 17 18 MSB LSB FORMAT 5: FMT[2:0] = 101 DAC: 18-Bit, MSB-First, I2S Left-Channel LRCIN Right-Channel BCKIN DIN 1 2 3 16 17 18 MSB LSB 1 2 3 16 17 18 MSB LSB ADC: 18-Bit, MSB-First, I2S Left-Channel LRCIN Right-Channel BCKIN DOUT 1 2 MSB 3 16 17 18 LSB 1 2 3 MSB 16 17 18 LSB T0016-09 Figure 20. Audio Data Input/Output Format (Formats 4 and 5) 20 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 6: FMT[2:0] = 110 DAC: 16-Bit, MSB-First, DSP-Frame LRCIN Left-Channel Right-Channel BCKIN DIN 16 1 2 3 14 15 16 1 MSB 2 3 14 15 16 1 LSB MSB LSB ADC: 16-Bit, MSB-First, DSP-Frame Left-Channel LRCIN Right-Channel BCKIN DOUT 16 1 2 MSB 3 14 15 16 1 2 3 LSB MSB 14 15 16 1 LSB T0016-10 Figure 21. Audio Data Input/Output Format (Format 6) 21 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 t(LRP) 1.4 V LRCIN t(BCL) t(BCH) t(LB) t(BL) 1.4 V BCKIN t(BCY) t(DIS) t(DIH) 1.4 V DIN t(BDO) t(LDO) 0.5 VDD DOUT T0021−02 BCKIN pulse cycle time t(BCY) 300 ns (min) BCKIN pulse duration, HIGH t(BCH) 120 ns (min) BCKIN pulse duration, LOW t(BCL) 120 ns (min) BCKIN rising edge to LRCIN edge t(BL) 40 ns (min) LRCIN edge to BCKIN rising edge t(LB) 40 ns (min) LRCIN pulse duration t(LRP) t(BCY) (min) DIN setup time t(DIS) 40 ns (min) DIN hold time t(DIH) 40 ns (min) DOUT delay time to BCKIN falling edge t(BDO) 40 ns (max) DOUT delay time to LRCIN edge t(LDO) 40 ns (max) Rising time of all signals t(RISE) 20 ns (max) Falling time of all signals t(FALL) 20 ns (max Figure 22. Audio Data Input/Output Timing SYSTEM CLOCK The system clock for the PCM3000/3001 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling frequency. The system clock can be either a crystal oscillator placed between XTI (pin 20) and XTO (pin 21), or an external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (pin 22), and XTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating. When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected to ground, the external clock must be tied to CLKIO. For best performance, the external-clock-input-2 circuit in Figure 23 is recommended. The PCM3000/3001 also has a system-clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided into 256 fS automatically. The 256-fS clock is used to operate the digital filters and the modulators. Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 23 and Figure 24 illustrate the typical system clock connections and external system clock timing. 22 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 CLKIO 256-fS Internal System Clock Clock Divider C1 Xtal XTI R C2 XTO C1 = C2 = 10 to 33 pF PCM3000/3001 Crystal Resonator Connection (Xtal must be fundamental mode, parallel resonant) CLKIO External Clock (CMOS I/F) External Clock (TTL I/F) CLKIO 256-fS Internal System Clock 256-fS Internal System Clock Clock Divider Clock Divider XTI XTI R XTO R XTO PCM3000/3001 External Clock Input 1 : (XTO is open) PCM3000/3001 External Clock Input 2 : (XTO is open) S0017−01 Figure 23. System Clock Connections 23 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz) 256 fS 384 fS 512 fS 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 t(CLKIH) XTI CLKIO 3.2 V 2.0 V 1.4 V 0.8 V XTI or CLKIO t(CLKIL) T0005-06 System clock pulse duration, HIGH t(CLKIH) 12 ns (min) System clock pulse duration, LOW t(CLKIL) 12 ns (min) Figure 24. External System Clock Timing POWER-ON RESET The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI or CLKIO) is active and VDD > 4 V. For the PCM3001, the system clock must complete a minimum of 3 complete cycles prior to VDD > 4 V to ensure proper reset operation. The initialization sequence requires 1024 system cycles for completion, as shown in Figure 25. Figure 26 shows the state of the DAC and ADC outputs during and after the reset sequence. VDD 4.4 V 4.0 V 3.6 V Reset Reset Removal Internal Reset 3 Clocks Minimum 1024 System Clock Periods System Clock (XTI or CLKIO) T0014-04 Figure 25. Internal Power-On Reset Timing 24 PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Reset Removal or Power Down(1) Off Reset Internal Reset Ready/Operation 32/fS DAC VOUT VCOM (0.5 VCC2) 4096/fS ADC DOUT Zero Data Zero Data Normal Data(2) T0019-03 (1) Power down is for PCM3000 only. (2) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appears initially. Figure 26. DAC Output and ADC Output for Reset and Power Down EXTERNAL RESET The PCM3000/3001 includes a reset input, RSTB (pin 28). As shown in Figure 27, the external reset signal must drive RSTB low for a minimum of 40 nanoseconds while the system clock is active in order to initiate the reset sequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion. Figure 26 shows the state of the DAC and ADC outputs during and after the reset sequence. RSTB Pulse Duration t(RST) = 40 ns (min) RSTB t(RST) Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock (XTI or CLKIO) T0015-04 Figure 27. External Forced-Reset Timing SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM The PCM3000/3001 operates with LRCIN synchronized to the system clock. The codec does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC stops within 1/fS, and the analog output is forced to bipolar zero (VCC2/2) until the system clock is resynchronized to LRCIN. Internal operation of the ADC also stops within 1/fS, and the digital output codes are set to bipolar zero until resynchronization occurs. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation remains normal. Figure 28 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero (