®
PCM1744
PCM
1744
For most current data sheet and other product
information, visit www.burr-brown.com
24 Bits, 96kHz,
Sampling Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
DESCRIPTION
● COMPLETE STEREO DAC: Includes Digital
Filter and Output Amp
The PCM1744 is a complete low cost stereo audio
digital-to-analog converter (DAC), operating off of a
256fS or 384fS system clock. The DAC contains a 3rdorder ∆Σ modulator, a digital interpolation filter, and
an analog output amplifier. The PCM1744 accepts
24-bit input data in a I2S format.
● DYNAMIC RANGE: 95dB
● MULTIPLE SAMPLING FREQUENCIES:
Up to 96kHz
● 8x OVERSAMPLING DIGITAL FILTER
● SYSTEM CLOCK: 256fS / 384fS
● 24-BIT I2S DATA INPUT FORMAT
● SMALL 14-PIN SOIC PACKAGE
The digital filter performs an 8x interpolation function
and includes de-emphasis at 44.1kHz. The PCM1744
can accept digital audio sampling frequencies from
16kHz to 96kHz, always at 8X oversampling.
The PCM1744 is ideal for low-cost, CD-quality consumer audio applications.
Multi-level
Delta-Sigma
Modulator
BCKIN
LRCIN
DIN
Serial
Input
I/F
Low-pass
Filter
8X Oversampling
Digital Filter
VOUTL
CAP
Multi-level
Delta-Sigma
Modulator
FORMAT
DAC
DAC
Low-pass
Filter
VOUTR
Mode
Control
I/F
DM
Power Supply
256fS/384fS
VCC
SCKI
GND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1999 Burr-Brown Corporation
SBAS130
PDS-1553A
1
PCM1744
Printed in U.S.A. September, 1999
SPECIFICATIONS
All specifications at +25°C, +VCC = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1744
PARAMETER
CONDITIONS
RESOLUTION
DATA FORMAT
Audio Data Interface Format
Audio Data Format
Sampling Frequency (fS)
Internal System Clock Frequency
THD+N at FS (0dB)
THD+N at –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
MAX
UNITS
Bits
I2S
Two’s Binary Complement
16
96
kHz
0.8
±0.8
VDC
VDC
µA
256fS /384fS
TTL
2.0
f = 991kHz
EIAJ, A-weighted
EIAJ, A-weighted
90
90
88
VOUT = VCC/2 at BPZ
Full Scale (0dB)
AC Load
–83
–32
95
97
95
–79
dB
dB
dB
dB
dB
±1.0
±1.0
±20
±10.0
±5.0
±50
% of FSR
% of FSR
mV
0.62 x VCC
VCC/2
Vp-p
VDC
kΩ
10
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
TYP
24
DIGITAL INPUT/OUTPUT
Logic Level
Input Logic Level
VIH(1)
VIL(1)
Input Logic Current: IIN(1)
DYNAMIC PERFORMANCE(2)
MIN
0.445
11.125/fS
fS
fS
dB
dB
sec
100
–0.16
kHz
dB
0.555
±0.17
–35
f = 20kHz
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current
Power Dissipation
4.5
TEMPERATURE RANGE
Operation
Storage
–25
–55
5
13
65
5.5
18
90
VDC
mA
mW
+85
+125
°C
°C
NOTES: (1) Pins 1, 2, 3, 12, 13, 14: LRCIN, DIN, BCKIN, DM, FORMAT, SCKI. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N
specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1744
2
PIN ASSIGNMENTS
PIN CONFIGURATION
TOP VIEW
SOIC
PIN
NAME
I/O
FUNCTION
1(1)
LRCIN
IN
Sample Rate Clock Input
2(1)
DIN
IN
Audio Data Input
3(1)
BCKIN
IN
Bit Clock Input for Audio Data.
NC
—
No Connection
Common Pin of Analog Output Amp
4
LRCIN
DIN
1
14
2
13
SCKI
5
CAP
—
6
VOUTR
OUT
7
GND
—
Ground
Power Supply
TEST
BCKIN
3
12
DM
8
VCC
—
NC
4
11
NC
9
VOUTL
OUT
CAP
5
10
NC
10
NC
—
VOUTR
6
9
VOUTL
GND
7
PCM1744
8
Right-Channel Analog Output
Left-Channel Analog Output
No Connection
11
NC
—
No Connection
12(2)
DM
IN
De-Emphasis Control
HIGH: De-emphasis ON
LOW: De-emphasis OFF
13(2)
TEST
—
Test Pin. Must be left open.
14(1)
SCKI
IN
System Clock Input (256fS or 384fS)
VCC
NOTE: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with internal pull-up.
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ...................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Power Dissipation .......................................................................... 290mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
Thermal Resistance, θJA .............................................................. +90°C/W
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
PCM1744
"
SO-14
"
235
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
–25°C to +85°C
"
PCM1744U
PCM1744U
PCM1744U
PCM1744U/2K
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book, or visit the Burr-Brown web site
at www.burr-brown.com. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering
2000 pieces of “PCM1744U/2K” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown
IC Data Book.
®
3
PCM1744
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256fS, unless otherwise noted.
DYNAMIC PERFORMANCE
0.008
3.1
2.8
0.005
2.7
–60dB
0.003
2.6
0.002
2.5
0.001
2.4
SNR (dB)
2.9
THD+N at –60dB (%)
3.0
0.006
99
97
97
96
96
95
95
94
2.3
0
25
50
75
85
93
–25
100
93
0
Temperature (°C)
THD+N vs POWER SUPPLY
THD+N at 0dB (%)
3.0
0dB
0.006
2.9
0.005
2.8
0.004
2.7
0.003
2.6
0.002
2.5
–60dB
0.001
0
2.3
5.25
97
97
96
96
95
95
Dynamic Range
93
4.5
4.75
5.0
98
5.2
98
97
0.012
4.2
3.7
0dB
0.008
3.2
0.006
2.7
–60dB
0.004
97
SNR
96
96
95
95
94
94
93
93
Dynamic Range
92
91
90
90
89
89
88
44.1
96
48
88.2
Sampling Rate (kHz)
Sampling Rate (kHz)
®
4
92
91
88
2.2
88.2
SNR (dB)
4.7
THD+N AT –60dB (%)
0.014
THD+N at 0dB (%)
5.5
SNR, DYNAMIC RANGE vs SAMPLING RATE
THD+N vs SAMPLING RATE
PCM1744
5.25
VCC (V)
0.016
48
94
93
5.5
VCC (V)
44.1
100
98
SNR
94
2.4
0.01
85
99
98
SNR (dB)
3.1
5.0
75
99
THD+N at –60dB (%)
0.008
4.75
50
SNR, DYNAMIC RANGE vs POWER SUPPLY
3.2
4.5
25
Temperature (°C)
0.009
0.007
94
Dynamic Range
Dynamic Range (dB)
0
–25
98
SNR
96
Dynamic Range (dB)
0.004
99
98
0dB
0.007
THD+N at 0dB (%)
SNR, DYNAMIC RANGE vs TEMPERATURE
3.2
Dynamic Range (dB)
THD+N vs TEMPERATURE
0.009
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
0
–20
–0.2
–40
–0.4
dB
dB
0
–60
–0.6
–80
–0.8
–100
0 0.4536fS
1.3605fS
2.2675fS
3.1745fS
–1
4.0815fS
0
0.1134fS
Frequency (Hz)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
0.3402fS
0.4535fS
DE-EMPHASIS FREQUENCY ERROR (44.1kHz)
0
0.6
–2
0.4
–4
0.2
Error (dB)
Level (dB)
0.2268fS
Frequency (Hz)
–6
0.0
–8
–0.2
–10
–0.4
–12
–0.6
0
5
10
15
20
25
0
Frequency (kHz)
4999.8375
9999.675
14999.5125
19999.35
Frequency (kHz)
®
5
PCM1744
1/fS
L_ch
LRCIN (pin 1)
R_ch
BCKIN (pin 3)
AUDIO DATA WORD = 24-BIT
DIN (pin 2)
1
2
3
20
21 22 23 24
MSB
1
LSB
2
3
MSB
1
20 21 22 23 24
2
LSB
FIGURE 1. I2S Data Input Timing.
LRCKIN
1.4V
tBCH
tBCL
tLB
BCKIN
1.4V
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
: tBCY
: 100ns (min)
BCKIN Pulse Width High
: tBCH
: 50ns (min)
BCKIN Pulse Width Low
: tBCL
: 50ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
: 30ns (min)
LRCIN Edge to BCKIN Rising Edge : tLB
: 30ns (min)
DIN Set-up Time
: tDS
: 30ns (min)
DIN Hold Time
: tDH
: 30ns (min)
FIGURE 2. Audio Data Input Timing.
SYSTEM CLOCK
The system clock for PCM1744 must be either 256fS or
384fS, where fS is the audio sampling frequency (LRCIN),
typically 32kHz, 44.1kHz, 48kHz, 88.2kHz or 96kHz. The
system clock is used to operate the digital filter and the noise
shaper. The system clock input (SCKI) is at pin 14. Timing
conditions for SCKI are shown in Figure 3.
tSCKIH
2.0V
SCKI
0.8V
tSCKIL
System Clock Pulse Width High
System Clock Pulse Width Low
tSCKIH
tSCKIL
PCM1744 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The
system clock should be synchronized with LRCIN (pin 1),
but PCM1744 can compensate for phase differences. If the
phase difference between LRCIN and system clock is greater
13ns (min)
13ns (min)
FIGURE 3. System Clock Timing Requirements.
®
PCM1744
6
than ±6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a
bipolar zero state (VCC/2) during the synchronization function. Table I shows the typical system clock frequency
inputs for the PCM1744.
RESET
PCM1744 has an internal power-on reset circuit. The internal
power-on reset initializes (resets) when the supply voltage
VCC > 2.2V (typ). The power-on reset has an initialization
period equal to 1024 system clock periods after VCC > 2.2V.
During the initialization period, the outputs of the DAC are
invalid, and the analog outputs are forced to VCC/2. Figure 5
illustrates the power-on reset and reset-pin reset timing.
SYSTEM CLOCK
FREQUENCY (MHz)
SAMPLING
RATE (LRCIN)
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
256fS
384fS
8.192
11.2896
12.288
22.5792
24.576
12.288
16.9340
18.432
33.868
36.864
DE-EMPHASIS CONTROL
Pin 12 (DM) enables PCM1744’s de-emphasis function. Deemphasis operates only at 44.1kHz.
TABLE I. System Clock Frequencies vs Sampling Rate.
DM
0
1
TYPICAL CONNECTION DIAGRAM
Figure 4 illustrates the typical connection diagram for
PCM1744 used in a stand-alone application.
De-emphasis OFF
De-emphasis ON (44.1kHz)
TABLE II. De-emphasis Control Selection.
INPUT DATA FORMAT
PCM1744 can accept input data a 24-bit I2S format, as
shown in Figure 1.
10µF
+5V Analog
+
2
3
PCM
Audio Data
Processor
1
7
8
GND
VCC
DIN
VOUTL
BCKIN
CAP
9
5
+
LRCIN
PCM1744
VOUTR
Post
LPF
Lch Analog Out
Post
LPF
Rch Analog Out
10µF
6
13
14
SCKI
256fS or 384fS System Clock
TEST
DM
12
De-Emphasis Control
FIGURE 4. Typical Connection Diagram.
VCC
2.6V
2.2V
1.8V
Reset
Reset Removal
Internal Reset
1024 system (= SCKI) clocks
SCKI Clock
FIGURE 5. Internal Power-On Reset Timing.
®
7
PCM1744
APPLICATION
CONSIDERATIONS
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
DELAY TIME
1.0
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1744:
dB
0.5
0
TD = 11.125 x 1/fS
–0.5
For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc,
etc., generally are not affected by delay time. For some
professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms.
–1.0
20
100
1k
Frequency (Hz)
10k
24k
FIGURE 6. Low-Pass Filter Frequency Response.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1744 using a 20kHz low-pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and dynamic range readings than are found in the
specifications. The low-pass filter removes out-of-band noise.
Although it is not audible, it may affect dynamic specification numbers.
dB
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
10
100
1k
10k
100k
1M
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 6. The higher frequency roll-off of
the filter is shown in Figure 7. If the user’s application has
the PCM1744 driving a wideband amplifier, it is recommended to use an external low-pass filter. A simple 3rdorder filter is shown in Figure 8. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
10M
Frequency (Hz)
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. It is also recommended to include a 0.1µF ceramic
capacitor in parallel with the 10µF tantalum bypass capacitor.
FIGURE 7. Low-Pass Filter Wideband Frequency Response.
GAIN vs FREQUENCY
6
90
+
10kΩ
VSIN
10kΩ
680pF
OPA134
10kΩ
0
–34
–90
–54
–180
Phase
100pF
–
–74
–270
–94
–360
100
FIGURE 8. 3rd-Order LPF.
®
PCM1744
8
1k
10k
Frequency (Hz)
100k
1M
Phase (°)
1500pF
Gain (dB)
Gain
–14
+
In
+
8fS
24-Bit
+
Z–1
+
+
–
+
Z–1
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
48fS (384fS)
64fS (256fS)
2
1
0
FIGURE 9. 5-Level ∆Σ Modulator Block Diagram.
THEORY OF OPERATION
5-LEVEL DELTA SIGMA MODULATOR
The delta-sigma section of PCM1744 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 9. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter over
the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8x interpolation filter is 96fS for a
384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 10.
20
0
Gain (–dB)
–20
–40
–60
–80
–100
–120
–140
–160
0
5
10
15
20
25
Frequency (kHz)
FIGURE 10. Quantization Noise Spectrum.
®
9
PCM1744
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1744U
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM1744U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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