PCM1750U/1KG4

® PCM1750P PCM1750U Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● DUAL 18-BIT LOW-POWER CMOS AUDIO A/D CONVERTER ● FAST 4.5µs MIN CONVERSION TIME INCLUDING S/H ● TWO CO-PHASE SAMPLED, ±2.75V AUDIO INPUTS ● CAPABLE OF 4X PER CHANNEL OVERSAMPLING RATE The PCM1750 is a low cost, dual 18-bit CMOS analog-to-digital converter optimized for dynamic signal applications. The PCM1750 features true co-phased inputs with an internal sample/hold function for each channel. The PCM1750 also comes complete with an internal reference. Total power dissipation is less than 300mW max using ±5V voltage supplies. Low maximum Total Harmonic Distortion + Noise (–88dB max) is 100% tested. The very fast PCM1750 is capable of 4X x audio bandwidth oversampling rates on both input channels simultaneously, providing greater freedom to designers in selecting input anti-aliasing filters. ● RUNS ON ±5V SUPPLIES AND DISSIPATES 300mW MAX ● COMPACT 28-PIN PLASTIC DIP OR SOIC PCM1750 outputs serial data in a format that is compatible with many digital filter chips and comes packaged in a space saving 28-pin plastic DIP or SOIC. ● VERY LOW MAX THD+N: –88dB Without External Adjust ● COMPLETE WITH INTERNAL REFERENCE AND DUAL S/H FUNCTION MSB Adj Left Reference Offset Adj Left S/H VIN Left CDAC Left Comp S OUT Left 18-Bit SAR Latch Shift Register Control Logic SOUT Right VIN Right Offset Adj Right Clock Convert Latch Comp S/H 18-Bit SAR CDAC Right Reference MSB Adj Right International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1084B ® SBAS007 1 Printed in U.S.A. October, 1993 PCM1750 SPECIFICATIONS ELECTRICAL At 25°C, and ±VA = ±5.0V; +VD = +5.0V, unless otherwise noted. Where relevant, specifications apply to both left and right input/output channels. PCM1750P, U PARAMETER CONDITIONS MIN THD + N at –60dB Referred to Full Scale +88 RESOLUTION TYP MAX 18 DYNAMIC RANGE ANALOG INPUT Input Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Full Power Input Bandwidth DIGITAL INPUT/OUTPUT Logic Family Logic Level: VIH VIL VOH VOL Output Data Format Convert Command Convert Command Pulse Width Conversion Time UNITS Bits +90 dB ±2.75 20 10 50 500 V pF ns psrms kHz CMOS Compatible IIH = ±5µA IIL = ±5µA ISOURCE = 1.0mA ISINK = 3.2mA Throughput Including Sample/Hold(2) +3.5 –0.3 +2.7 +VD + 0.3 +1.5 +4.7 +0.2 +0.4 Serial, MSB First, BTC(1) Positive Edge 81 4.5 5.2 20.8 V V V V ns µs DYNAMIC CHARACTERISTICS (20Hz to 24kHz; 4X data decimated to 1X) Signal-to-Noise Ratio(3) Total Harmonic Distortion + N(7) fIN = 1kHz (0dB) fIN = 1kHz (–20dB) fIN = 1kHz (–60dB) Channel Separation fs = 192kHz(4); fIN = 1kHz (0dB)(5) Without External Adjustments fs = 192kHz fs = 192kHz fs = 192kHz fs = 192kHz; fIN = 1kHz (0dB) and 0V dB(6) +88 +90 –88 –68 –28 +96 –90 –70 –30 +108 dB dB dB dB ±5 ±2.0 Channel to Channel ±2 ±0.5 ±2 ±3 ±0.002 ±0.003 1 % % mV mV % of FSR(10) % of FSR ms DRIFT (With Internal Reference) Gain Bipolar Zero 0°C to 70°C 0°C to 70°C ±50 ±10 ppm/°C ppm of FSR/°C DRIFT (Exclusive of Internal Reference) Gain Bipolar Zero 0°C to 70°C 0°C to 70°C ±10 ±3 ppm/°C ppm of FSR/°C 0°C to 70°C +2.75 ±100 0.2 ±25 ±50 V µA Ω mV ppm/°C 363 || 120 Ω || pF 0.03 %/% ACCURACY Gain Error Gain Mismatch BPZ (Bipolar Zero) Error(8) BPZ Error Mismatch BPZ Differential Linearity Error(9) Linearity Error Warm-up Time REFERENCE VREF Output (Pins 19, 24): Voltage Current Impedance Accuracy Drift VREF Input (Pins 18, P25): Impedance(11) POWER SUPPLY REJECTION POWER SUPPLY REQUIREMENTS ±VA Supply Voltage Range +VD Supply Voltage Range +IA; +ID Combined Supply Current –IA Supply Current Power Dissipation Channel to Channel % of VIN / % of VSUPPLY (12) ±4.75 +4.75 +VA; +VD = +5.0V –VA = –5.0V ±VA = ±5.0V; +VD = +5.0V TEMPERATURE RANGE Specification Operating Storage 0 –40 –60 ±5.00 +5.00 +28 –13 210 ±5.25 +5.25 300 V V mA mA mW +70 +85 +100 °C °C °C NOTES: (1) Binary Two’s Complement coding. (2) The PCM1750 is tested and guaranteed at 5.2µs, however it will operate at 4.5µs. The dynamic performance is not guaranteed or tested at this conversion rate. (3) Ratio of SignalRMS / (DistortionRMS + NoiseRMS). (4) A/D converter sample frequency (4 x 48kHz; 4X oversampling per channel). (5) A/D converter input frequency (signal level). (6) Referred to input signal level. (7) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (8) Externally adjustable to zero error. (9) Differential non-linearity error at bipolar major carry input code. Externally adjustable to zero error. (10) Full scale range (5.50V). (11) Refer to equivalent circuit in Figure 1. (12) Worst case operating condition. Refer to typical performance curves. ® PCM1750 2 PIN ASSIGNMENTS ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 –5V Analog Supply Voltage +5V Analog Supply Voltage Serial Output (Left Channel) External Clock Input +5V Analog Supply Voltage +5V Digital Voltage Supply +5V Digital Voltage Supply Digital Common Connection Analog Common Connection Digital Common Connection Convert Command Input Serial Output (Right Channel) +5V Analog Supply Voltage –5V Analog Supply Voltage Offset Adjust (Right Channel) MSB Adjust (Right Channel) Analog Voltage Input (Right Channel; ±2.75V) Reference Voltage Input (Right Channel) Reference Voltage Output (Right Channel) Analog Common Connection Reference Voltage Decouple Reference Common Connection Analog Common Connection Reference Voltage Output (Left Channel) Reference Voltage Input (Left Channel) Analog Voltage Input (Left Channel; ±2.75V) MSB Adjust (Left Channel) Offset Adjust (Left Channel) MNEMONIC Analog Input Voltage (VIN) .................................. –VA –0.3V to +VA + 0.3V +VA; +VD to ACOM/DCOM ............................................................ 0 to +7V –VA to ACOM/DCOM .................................................................... 0 to –7V –VA to +VA; +VD ......................................................................... 0 to +14V ACOM to DCOM .................................................................................. ±1V Digital Inputs (pins 4, 11) to DCOM ........................... –0.3V to +VD + 0.3V Power Dissipation .......................................................................... 400mW Lead Temperature, (soldering 10s) ................................................ +300°C Max Junction Temperature .............................................................. 165°C Thermal Resistance, θJA: Plastic DIP ............................................ 80°C/W Thermal Resistance, θJA: Plastic SOIC ....................................... 100°C/W –VA +VA SOUTL CLK +VA +VD +VD DCOM ACOM DCOM CONVERT SOUTR +VA –VA OFFADJR MSBADJR VINR VREFINR VREFOUTR ACOM VREFCAP RCOM ACOM VREFOUTL VREFINL VINL MSBADJL OFFADJL NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE INFORMATION MODEL PCM1750P PCM1750U PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 28-Pin Plastic SOIC 215 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. TYPICAL PERFORMANCE CURVES At 25°C, and ±VA = ±5.0V; +VD = +5V, unless otherwise noted. Where relevant, specifications apply to both left and right input output channels. THD+N vs FREQUENCY (Without 4X Digital Filter) THD+N vs FREQUENCY (With 4X Digital Filter) –20 –20 VIN = –60dB VIN = –60dB –40 VIN = –40dB THD+N (dB) THD+N (dB) –40 –60 VIN = –20dB VIN = –40dB –60 VIN = –20dB VIN = 0dB –80 –80 V IN = 0dB –100 –100 0 4 8 12 16 20 0 24 20 40 60 80 100 Frequency (kHz) Frequency (kHz) The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1750 TYPICAL PERFORMANCE CURVES (CONT) At 25°C, and ±VA = ±5.0V; +VD = +5.0V, unless otherwise noted. Where relevant, specifications apply to both left and right input-output channels. THD vs FREQUENCY (With 4X Digital Filter) THD vs FREQUENCY (Without 4X Digital Filter) –70 –70 –80 –80 THD (dB) THD (dB) VIN = 0dB VIN = 0dB –90 –100 –100 –110 –110 0 4 8 12 16 20 24 0 60 PSR vs FREQUENCY (–5V SUPPLY) PSR vs FREQUENCY (+5V SUPPLIES) 1 0.1 0.1 0.01 % of VIN /% of V SUPPLY At BPZ: % of FSR / % of VSUPPLY 80 100 100k 1M % of VIN /% of V SUPPLY 0.01 At BPZ: % of FSR / % of VSUPPLY 0.001 0.0001 0.0001 1 10 100 1k 10k 100k 1 1M 10 100 1k 10k Frequency (Hz) Frequency (Hz) V REF vs TEMPERATURE (VREF Outputs) FFT 850Hz (24kHz BW; 2048 POINTS) 2.80 0 2.78 –25 Amplitude (dB) VREF (V) 40 Frequency (kHz) 1 0.001 20 Frequency (kHz) %/% %/% –90 2.76 2.74 2.72 –50 –75 –100 –125 2.70 –150 –40 –20 0 20 40 60 80 0 100 Temperature in °C 10 15 Frequency (kHz) ® PCM1750 5 4 20 24 TYPICAL PERFORMANCE CURVES (CONT) At 25°C, and ±VA; +VD = ±5V, unless otherwise noted. Where relevant, specifications apply to both left and right input-output channels. FFT 17kHz and 21kHz (24kHz BW; 16384 POINTS) 0 –25 –25 –6dB Amplitude (dB) Amplitude (dB) FFT 20kHz (24kHz BW; 2048 POINTS) 0 –50 –75 –100 –50 –75 –100 –125 –125 –150 –150 0 5 10 15 20 0 24 5 15 20 24 FFT 52kHz (96kHz BW; 2048 POINTS) 0 0 –25 –25 Amplitude (dB) Amplitude (dB) FFT 3.7kHz (96kHz BW; 2048 POINTS) –50 –75 –100 –125 –50 –75 –100 –125 –150 –150 0 20 40 60 80 96 0 20 Frequency (kHz) 40 60 80 96 Frequency (kHz) FFT 92kHz (96kHz BW; 2048 POINTS) FFT 88kHz and 92kHz (96kHz BW; 16384 POINTS) 0 0 –25 –25 –50 Amplitude (dB) Amplitude (dB) 10 Frequency (kHz) Frequency (kHz) –75 –100 –125 –6dB –50 –75 –100 –125 –150 0 20 40 60 80 –150 96 0 Frequency (kHz) 20 40 60 80 96 Frequency (kHz) ® 5 PCM1750 THEORY OF OPERATION OVERVIEW co-phase sampling which means that both S/H circuits are switched at the same time into the HOLD mode to capture their respective input signals simultaneously. This eliminates phasing errors produced by alternative architecture ADCs which do not sample the two input channels at the same time. The PCM1750 is a dual 18-bit successive approximation CMOS analog-to-digital converter with serial data outputs designed especially for digital audio and similar applications. The single-chip converter is fabricated on a 3µ P-well CMOS process which includes poly-poly capacitors, lasertrimmable nichrome resistors, and two layers of interconnect metal. The dual converter employs a switched capacitor architecture which provides separate, simultaneous S/H (sample/hold) functions for each input channel. The separate S/H for each channel results in a desired feature called VREF Switched binary-weighted poly-poly capacitors are used in CDAC (capacitive digital-to-analog converter) configurations to form the successive approximation converter sec- CDAC H1 S1 VIN S2 S3 C1 (MSB) 20PF AZ 3 AZ 1 H2 CAZ 3 CAZ 1 A1 Latch A2 C2 10PF CAZ 2 AZ 2 Comparator Data Out CAZ 4 AZ 4 L C3 5PF Auto-Zeroed Comparator P18, P25 P19, P24 VREF = 2.75V C1T Ra VREFIN VREFOUT 150k Ω R1a 47k Ω Rb S1T 13.25k Ω C2T TDAC R1b 500 Ω 5k Ω R2a +VA (+5V) +VA (+5V) S 2T C 3T 600Ω P18, P25 R2b P16, P27 R 3a VREFIN 917Ω 0 to 120pF (Code dependent) 47k Ω 25k Ω S 3T MSB Adj R 3b .01µF Simplified VREFIN Circuit C12T R12a +VA (+5V) S12T Coff R12b P15, P28 Roffa 25k Ω 100mV Soff Off Adj 13.25kΩ 5k Ω R offb 500Ω .01µF Optional External Adjustment Circuitry FIGURE 1. PCM1750 Simplified Circuit Diagram. ® PCM1750 6 tions of the PCM1750. Two other switched-capacitor TDACs (trim-DACs, which employ laser-trimmed nichrome resistors) are also used to provide small correction voltages to the latching comparators. These small correction voltages compensate for ratio matching errors of the binary-weighted capacitors in the CDAC. The comparators contain autozeroed preamplifier stages ahead of the latching amplifier stage to produce a one bit, serial data stream that controls the successive approximation algorithm for each channel of the PCM1750. input channel, provide binary-two’s-complement coded output to an optional external digital decimation filter when over sampling operation is desired. The use of the optional companion digital filter, the DF1750, is described later in the installation and application sections of this product data sheet. A separate product data sheet is also available for the Burr-Brown DF1750 giving all the specifications and performance diagrams associated with this digital filter. To simplify user application, the PCM1750 includes an internal band-gap reference with fast settling buffer amplifiers to drive the CDACs. The dual converters operate synchronously (to minimize digital noise conversion errors) using an external system clock (normally at 1X, 2X or 4X the standard 48kHz audio sampling rate). By operating at a 2X or 4X oversampling rate the roll-off requirement for the input anti-aliasing filters is relaxed. For example, 1X systems typically use a 9 to 11 pole LPF (low pass filter) whereas a 4X system can use a 6th (or smaller) order filter when an appropriate digital filter such as the DF1750 is used in conjunction with the sampling system. Oversampling also has the added benefit of improved signal to noise ratio and total harmonic distortion. Two serial outputs, one for each After each conversion, the dual ADC returns to the SAMPLE mode in order to track the input signals. The switches shown in the simplified circuit diagram of Figure 1 will then be in the following states: S1 connects VIN to C1 ; S2 to S18 connect C2 to C18 to VREF; H1 and H2 connect the top plates of the capacitor arrays to analog common; and the latching comparator is switched into its auto-zero mode by closing AZ1 to AZ4. Notice that C1 serves two purposes: it samples and stores the input signal VIN and it is the MSB of the CDAC. Storing VREF on C2 to C18 creates a bipolar offset, enabling VIN to cover a span from –VREF to +VREF. SAMPLE (TRACKING) MODE The 1/f noise as well as the DC input offset voltage of the comparator are removed by an autozeroing cycle which 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 *Master System Clock P11 (CONVERT) 3 2 1 16 4 17 18 19 P4 (EXT CLK IN) INTERNAL S/H CONTROL SR1 HOLD SAMPLE Bit 1 test time SR2 Bit 2 test time SR3 Bit 3 test time P3 (SOUT L) Bit 1 MSB Bit 2 Bit 3 Bit 4 Bit 16 Bit 17 Bit 18 LSB P12 (SOUT R) Bit 1 MSB Bit 2 Bit 3 Bit 4 Bit 16 Bit 17 Bit 18 LSB * Clock from optional digital filter chip (DF1750 4x decimation filter). FIGURE 2. PCM1750 Input/Output Timing Diagram. ® 7 PCM1750 occurs during the SAMPLE period (see the timing diagram shown in Figure 2). These errors are stored on the AC coupling capacitors (CAZ1 to CAZ4, shown in Figure 1) between the gain stages. During the SAMPLE period the inputs to gain stages A1 and A2 and the latch are grounded by switches H1, H2, and AZ1 to AZ4. Capacitors CAZ1 and CAZ2 track the amplified offset voltage of gain stage A1 and capacitors CAZ3 and CAZ4 do the same for A2. At the beginning of a conversion cycle, the autozeroing switches open and the instantaneous amplified value of both the DC offset voltage and the low-frequency flicker noise is stored on the coupling capacitors to produce zero comparator offset during a conversion cycle. analog common (see Figure 1). This terminates the comparator auto-zero cycle and simultaneously switches (cophase sampling) both converters from tracking their respective input signals into the HOLD mode, thus capturing the instantaneous value of VIN (with a small delay specified as the aperture time). At the start of a conversion cycle when S1 is switched to analog common, the sampled input signal VIN will appear at the comparator input as –VIN/2 due to the 2-to-1 capacitive divider action of Cl = C2 + C3 + ... C18. In a somewhat similar manner, VREF is transferred to the comparator input as –VREF/2 to create a bipolar offset. The 19-bit shift register, shown in Figure 4, controls testing of the bits of the dual ADCs beginning with bit-1 (MSB) and proceeding one bit at a time to bit-18 (LSB), leaving ON those bits that don’t cause the cumulative value of the CDAC to exceed the original input value and leaving OFF those bits that do. Since the bits of both channels are tested together, only one shift register is required to control both ranks of 18 data latches. SUCCESSIVE APPROXIMATION CONVERSION PROCESS The timing diagram in Figure 2 illustrates the successive approximation routine of the PCM1750. Control signals CONVERT and CLK are derived from a master system clock which comes from a 256fS (256 X the base sampling frequency of 48kHz) clock used by the optional digital filter. There are 64 clocks shown in the timing diagram because the PCM1750 is shown operating at 4 times the standard 48kHz sample rate (192kHz). For example, the testing of bit-2 proceeds in the following manner. The positive pulse from the second shift register element SR2, (see Figure 2 and 4) is applied to the bit-2 data latch and NOR gate. The NOR gate in turn drives S2 and switches bit-2 at the beginning of the bit-2 test interval. Note that the bit interval must be long enough to allow both the comparator input to settle and the comparator to respond. On Several events occur on the rising edge of the CONVERT command. Switches AZ1 to AZ4, H1 and H2 open and switch S1 reconnects the MSB capacitor, C1, from VIN to TREF 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 7 6 5 8 10 11 12 9 *Optional Digital Filter T1 Convert T4 T2 18 Ext Clk In T3 T5 1 19 T6 3 2 T7 SOUT Bit 17 Bit 18 LSB Bit 1 MSB T8 PARAMETER T1 (1 x TREF) T2 (6 x TREF) T3 (4 x TREF) T4 (3 x TREF) T5 (1 x TREF) T6 (2 x TREF) T7 T8 T9 TCONV (64 x TREF) TREF (Sample Rate /64) Bit 2 T9 DESCRIPTION MIN NOMINAL MAX UNITS Convert Command High S/H Acquisition Time Convert to Clock time Master Clock Input Clock High Clock Low Data Hold Time Data Setup Time Data Valid Time Conversion Throughput Time Ext Digital Filter Clock 24 420 281 211 24 45 10 33 486 326 244 33 67 55 1302 977 55 76 120 4.5 70 154 5.2 81 100 1212 20.8 326 % of T4 ns ns ns % of T4 % of T4 ns ns ns µs ns Note: The nominal timing shown in this diagram is all done automatically by the DF1750 digital filter. Only the optional digital filter clock is required when the DF1750 is used. FIGURE 3. PCM1750 Setup and Hold Timing Diagram. ® PCM1750 8 the next rising edge of CLKIN, at the end of the test interval, the comparator latch is strobed, providing a feedback logic level which tells the second data latch if bit-2 should be kept or rejected. This logic level is stored in the data latch and is passed on to switch S2 via the NOR gate on the falling edge of the pulse from SR2. This decision to keep or reject bit-2 moves the comparator input closer to a null condition, namely, zero potential. This sequential process continues for bit-3 through bit-18 and nulls the comparator inputs to within a value limited by the total system noise and the resolution/speed of the comparator. controlled process, ratio matching is typically 0.1% — a very respectable number for an untrimmed component. Even more impressive is their ratio tracking versus temperature of approximately 0.1ppm/°C. Achieving DLE (differential linearity error) of less than 1/2 LSB at the 16-bit level requires ratio matching of the more significant bits to about 0.001%. Since the untrimmed ratio matching of poly capacitors is about two orders of magnitude larger than this requirement, a one-time factory calibration of the upper bits is required as described in the next section. Next, consider the effect of temperature due to the ratio tracking of 0.lppm/°C. Over a 50°C span, DLE will change less than 1LSB at 18-bits; therefore, recalibration at temperature extremes is not necessary. Because of this excellent stability versus temperature (and versus time, also), the one-time factory calibration to correct initial DLE is more than satisfactory in meeting the accuracy requirements of the PCM1750. Notice from the timing diagram in Figure 2 that the successive approximation algorithm operates synchronously with an external clock to minimize digitally-coupled switching noise from corrupting either the sample-to-hold operation or the critical comparator bit decisions. The two serial output data streams are derived synchronously from the respective latched comparator outputs and are available after a delay of one CLKIN cycle as illustrated in Figure 2. The serial output driver cells are TTL and CMOS compatible. TDAC OPERATION Operation of the TDAC (trim DAC), which is laser trimmed at the wafer level, is described using bit-1 as an example. Switch S1T (see Figure 1) operates between two voltage levels—a reference level set by voltage divider Ra, Rb and a laser trimmable level set by R1a, R1b. The differences of these two levels is coupled by capacitor C1T to the minus input of the comparator to generate a correction voltage for DIFFERENTIAL LINEARITY CALIBRATION To understand the calibration of the PCM1750 it is necessary to discuss some of the characteristics of poly-poly capacitors. Poly capacitors are known to have equal or better stability and matching properties when compared to other precision components such as thin film resistors. On a well Serial Data From Latching Comparator To MSB Switches Left D Data Latches Left Channel 19-Bit Shift Register Data Latches Right Channel D Q To Bit 18 Switches Left D Q L R L R L R D Q SR1 S D Q SR2 R D Q SR18 R L R L R L R D Serial Data From Latching Comparator Q To Bit 2 Switches Left Q D Q D To MSB Switches Right To Bit 2 Switches Right D Q SR19 R Control Logic Q To Bit 18 Switches Right FIGURE 4. PCM1750 Successive Approximation Logic Diagram. ® 9 PCM1750 bit-1. The switches of the CDAC and the switches of the TDAC operate concurrently with each other, that is, when a decision is made to keep or reject bit-1, the same decision is made for the correction voltage for bit-1. Even though the ratio stability of the nichrome resistors used in the TDAC may not be as good as the poly capacitors, it is inconsequential because the correction voltage of each bit has a limited range of adjustment. A Gain Change Rotates Transfer Function 1FFFFH Digital Output 1FFFEH The DLE at the major carry (a code change from 111...111 to 000...000; in binary two’s complement coding) is typically ±1/2 LSB at the 16-bit level, which is sufficient to provide 90dB SNR and –30dB low level distortion (–60dB input). For applications requiring less DLE at the major carry, a pin is provided for each channel to make an external MSB adjustment. 00001H 00000H 3FFFFH –2.75 –20.98µV Offset Change Shifts Transfer Function +2.749979 0.00V 20001H 20000H * Gain drift (mostly due to reference drift) rotates the transfer function around the bipolar zero code (00000HEX ). DISCUSSION OF SPECIFICATIONS NOTE: As the power supply voltages change (mostly due to the +V supply), the transfer function rotates around BPZ. See the power supply rejection specification in the spec table. RESOLUTION AND DYNAMIC RANGE FIGURE 5. Analog Input to Digital Output Diagram. The theoretical resolution of the PCM1750 is 18-bits. The maximum possible number of output codes or counts at 18bits is 262,144 or 108dB (calculated by raising 2 to the 18th power). The relative accuracy of any A/D converter, however, is more a function of it’s absolute linearity and signalto-noise ratio than how many bits of resolution it has. These more pertinent specifications are described later in this section. From Figure 5, the effects of offset and gain errors can be visualized. These errors can change value in response to changes in temperature and/or supply voltage. In addition, gain error (or the full scale range, FSR) changes in direct proportion to the VREFIN voltage value. SAMPLE AND HOLD PARAMETERS Aperture Delay and Uncertainty Dynamic range, as it is usually defined for digital audio converters, is the measure of THD+N at an effective input signal level of –60dB referred to 0dB. For the PCM1750 this value is typically 90dB and a minimum of 88dB (for audio bandwidth = 20Hz to 24kHz, THD+N at –60db = –30 db typ, –28dB max; fIN = 1kHz and fS = 192kHz). Resolution is also commonly used as a theoretical measure of dynamic range, but it does not take into account the effects of distortion and noise at low signal levels. Aperture delay is the time required to switch from the SAMPLE to HOLD mode. This time is typically 10ns for the PCM1750 and it is constant. Aperture uncertainty (jitter) is the amount of uncertainty associated with the aperture delay. Aperture uncertainty affects the overall accuracy of the converter and is greatest at the maximum input frequency of the converter. The formula for determining the maximum input frequency (fMAX) for a given error contribution due to aperture uncertainty is: fMAX = (2 X π X tjitter X 2N)–1 where tjitter is the RMS aperture uncertainty and 2N is the desired SNR (signal-to-noise ratio) expressed in total number of quantization levels. A 15-bit SNR, therefore, would be expressed as 215 or 32768. Using the typical PCM1750 aperture jitter of 50psrms and an SNR at the 15-bit level, fMAX = (2 X π X 50ps X 32768)–1 or 97.1kHz. This matches very closely with the rated dynamic accuracy of the PCM1750 where THD+N = –88dB max. This means the typical aperture jitter of PCM1750 only becomes a factor when input signals to it exceed 97kHz and/or an SNR greater than 15 bits is desired. ANALOG INPUT RANGE The analog input range for the PCM1750 is a bipolar ±2.75V (nominal). Table I gives the precise input/output and voltage/code relationships for the PCM1750. Figure 5 shows these same relationships in a graphical format. It should be noted that the computed voltage input levels represent center values (the midpoint between code transitions). Output coding is in binary two’s complement. DIGITAL OUTPUT 262144 LSBs 1 LSB 1FFFFHEX 00000HEX 3FFFFHEX 20000HEX ANALOG INPUT VOLTAGE INPUT Full Scale Range Minimum Step Size +Full Scale Bipolar Zero Bipolar Zero –1LSB –Full Scale 5.50000000V 20.98083496µV +2.74997902V 0.00000000V –0.00002098V –2.75000000V Input Bandwidth The full power bandwidth of the PCM1750 is that input frequency above which significant distortion is observed (THD+N > 10-bits or –60dB for a full scale input signal). In the data sheet, this number is specified as typically being 500kHz. In wideband operation (when no digital filter is used) the additional full power bandwidth of the PCM1750 TABLE I. Analog Input to Digital Output Relationships. ® PCM1750 10 can be used to purposely alias a band-limited signal down into the baseband of the converter. This technique is called undersampling and can be used to directly down-convert an intermediate frequency riding on a much higher carrier frequency. Clock Lockout Any number of clocks can be given to the PCM1750 beyond the 19 required for normal operation. If a continuous clock is used, all clocks beyond the 19th are gated off by the PCM1750’s internal logic until the next positive going edge of the convert command. The converter also goes into the sample (track) mode starting on the positive edge of the 19th clock until the next positive edge of the convert command, regardless of how many additional clocks are offered. The ideal operation of the converter stops the clock input after the 19th during this critical signal acquisition time. This is the timing shown in Figure 3 . The critical timing aspect that must be observed if a clock input other than the recommended is used, is that ample time following the positive edge of convert command proceed the next rising clock edge. If this time is shortened, the most important bit-1 (MSB) decision, which is finalized on the first clock edge after convert command, will be adversely affected. In other words, the clock input cannot have a rising edge during the time interval T3 shown in Figure 3. DIGITAL I/O AND TIMING Input/Output Logic Compatibility Digital logic on the PCM1750 is CMOS compatible. Digital outputs on the PCM1750 are capable of driving a minimum of two standard TTL input loads. Digital output coding is in binary two’s complement. Table I gives the precise input/output voltage/code relationships for the PCM1750. Figure 5 shows these same relationships in a graphical format. Convert Command and External Clock Input A conversion is initiated on its positive going edge of the convert command. Although the convert command can return low at any time (prior to 50ns before the rising edge of the 19th clock), a typical convert command pulse width of 81ns (as called out in Figure 3) is specified for a 192kHz sample rate (fS). The reason for a pulse width spec is to reduce problems associated with digital logic feedthrough noise. The return of convert command to a logic low level in the specified time interferes least with the successive approximation process. Also, it should be noted that putting fast logic edges (