PCM1733

® PCM PCM1733 173 3 Stereo Audio DIGITAL-TO-ANALOG CONVERTER 18 Bits, 96kHz Sampling TM FEATURES q COMPLETE STEREO DAC: Includes Digital Filter and Output Amp q DYNAMIC RANGE: 95dB q MULTIPLE SAMPLING FREQUENCIES: 16kHz to 96kHz q 8X OVERSAMPLING DIGITAL FILTER q SYSTEM CLOCK: 256fS / 384fS q NORMAL OR I2S DATA INPUT FORMATS q SMALL 14-PIN SOIC PACKAGE DESCRIPTION The PCM1733 is a complete low cost stereo audio digital-to-analog converter (DAC), operating off of a 256fS or 384fS system clock. The DAC contains a 3rdorder ∆Σ modulator, a digital interpolation filter, and an analog output amplifier. The PCM1733 accepts 18-bit input data in either normal or I2S formats. The digital filter performs an 8X interpolation function and includes de-emphasis at 44.1kHz. The PCM1733 can accept digital audio sampling frequencies from 16kHz to 96kHz, always at 8X oversampling. The PCM1733 is ideal for low-cost, CD-quality consumer audio applications. BCKIN LRCIN DIN Serial Input I/F 8X Oversampling Digital Filter Multi-level Delta-Sigma Modulator DAC Low-pass Filter VOUTL CAP Multi-level Delta-Sigma Modulator Low-pass Filter VOUTR DAC FORMAT Mode Control I/F Power Supply DM 256fS/384fS SCKI VCC GND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1998 Burr-Brown Corporation PDS-1435A 1 Printed in U.S.A. PCM1733 January, 1998 SPECIFICATIONS All specifications at +25°C, +VCC = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1733 PARAMETER RESOLUTION DATA FORMAT Audio Data Interface Format Audio Data Format Sampling Frequency (fS) Internal System Clock Frequency DIGITAL INPUT/OUTPUT Logic Level Input Logic Level VIH(1) VIL(1) Input Logic Current: IIN(1) DYNAMIC PERFORMANCE(2) THD+N at FS (0dB) THD+N at –60dB Dynamic Range Signal-to-Noise Ratio Channel Separation DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Current Power Dissipation TEMPERATURE RANGE Operation Storage f = 991kHz –83 –32 95 97 95 ±1.0 ±1.0 ±20 –78 dB dB dB dB dB % of FSR % of FSR mV CONDITIONS MIN TYP 18 Standard /I2S Two’s Binary Complement 16 256fS /384fS TTL 2.0 0.8 ±0.8 VDC VDC µA 96 kHz MAX UNITS Bits EIAJ, A-weighted EIAJ, A-weighted 90 90 88 VOUT = VCC/2 at BPZ ±5.0 ±5.0 ±50 Full Scale (0dB) AC Load 10 0.62 x VCC VCC/2 Vp-p VDC kΩ 0.445 fS fS dB dB sec kHz dB 5.5 18 90 +85 +125 VDC mA mW °C °C 0.555 ±0.17 –35 11.125/fS 100 –0.16 4.5 5 13 65 f = 20kHz –25 –55 NOTES: (1) Pins 1, 2, 3, 12, 13, 14: LRCIN, DIN, BCKIN, DM, FORMAT, SCKI. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1733 2 PIN CONFIGURATION TOP VIEW SOIC PIN ASSIGNMENTS PIN 1(1) 2(1) 3(1) NAME LRCIN DIN BCKIN NC CAP VOUTR GND VCC VOUTL NC NC DM I/O IN IN IN — — OUT — — OUT — — IN FUNCTION Sample Rate Clock Input Audio Data Input Bit Clock Input for Audio Data. No Connection Common Pin of Analog Output Amp Right-Channel Analog Output Ground Power Supply Left-Channel Analog Output No Connection No Connection De-emphasis Control HIGH: De-emphasis ON LOW: De-emphasis OFF Audio Data Format Select HIGH: I2S Data Format LOW: Standard Data Format System Clock Input (256fS or 384fS) LRCIN DIN BCKIN NC CAP VOUTR GND 1 2 3 4 5 6 7 PCM1733 14 13 12 11 10 9 8 SCKI FORMAT DM NC NC VOUTL VCC 4 5 6 7 8 9 10 11 12(2) 13(2) FORMAT IN PACKAGE INFORMATION PRODUCT PCM1733U PACKAGE 14 Pin SOIC PACKAGE DRAWING NUMBER(1) 235 14 SCKI IN NOTES: (1) Schmitt Trigger input. (2) Schmitt Trigger input with internal pull-up. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Power Dissipation .......................................................................... 290mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Thermal Resistance, θJA .............................................................. +90°C/W ® 3 PCM1733 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256fS, unless otherwise noted. DYNAMIC PERFORMANCE THD+N vs TEMPERATURE 0.009 0.008 0.007 THD+N at 0dB (%) SNR, DYNAMIC RANGE vs TEMPERATURE 3.2 3.1 THD+N at –60dB (%) 99 98 97 SNR (dB) 99 98 97 96 95 94 93 0 25 50 75 85 100 Temperature (°C) Dynamic Range (dB) Dynamic Range (dB) Dynamic Range (dB) 0dB 3.0 2.9 2.8 –60dB 2.7 2.6 2.5 2.4 2.3 SNR 0.006 0.005 0.004 0.003 0.002 0.001 0 –25 0 25 50 75 85 100 96 95 94 93 –25 Dynamic Range Temperature (°C) THD+N vs POWER SUPPLY 0.009 0.008 0.007 THD+N at 0dB (%) SNR, DYNAMIC RANGE vs POWER SUPPLY 3.2 3.1 98 THD+N at –60dB (%) 99 99 98 97 96 95 Dynamic Range 94 93 4.5 4.75 5.0 VCC (V) 5.25 5.5 0dB 3.0 2.9 2.8 2.7 2.6 SNR 0.006 0.005 0.004 0.003 0.002 0.001 0 4.5 4.75 5.0 VCC (V) 5.25 5.5 –60dB 97 SNR (dB) 96 95 94 2.5 2.4 2.3 93 THD+N vs SAMPLING RATE 0.016 0.014 THD+N at 0dB (%) 0.012 0.01 0.008 0.006 –60dB 0.004 44.1 48 88.2 96 Sampling Rate (kHz) 2.2 0dB 5.2 4.7 THD+N AT –60dB (%) 4.2 3.7 3.2 2.7 98 97 96 95 SNR (dB) SNR, DYNAMIC RANGE vs SAMPLING RATE 98 SNR 97 96 95 94 93 Dynamic Range 92 91 90 89 88 44.1 48 88.2 96 Sampling Rate (kHz) 94 93 92 91 90 89 88 ® PCM1733 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted. DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC 0 0 PASSBAND RIPPLE CHARACTERISTIC –20 –0.2 –40 dB –0.4 –60 dB –0.6 –80 –0.8 –100 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS Frequency (Hz) –1 0 0.1134fS 0.2268fS Frequency (Hz) 0.3402fS 0.4535fS DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 –2 –4 Level (dB) DE-EMPHASIS FREQUENCY ERROR (44.1kHz) 0.6 0.4 0.2 Error (dB) –6 –8 –10 –12 0 5 10 15 20 25 Frequency (kHz) 0.0 –0.2 –0.4 –0.6 0 4999.8375 9999.675 Frequency (kHz) 14999.5125 19999.35 ® 5 PCM1733 1/fs L_ch LRCIN (pin 1) BCKIN (pin 3) AUDIO DATA WORD = 18-BIT DIN (pin 2) 16 17 18 1 2 3 MSB 16 LSB 17 18 1 2 3 MSB 16 LSB 17 18 R_ch FIGURE 1. “Normal” Data Input Timing. 1/fs LRCIN (pin 1) BCKIN (pin 3) AUDIO DATA WORD = 18-BIT DIN (pin 2) 1 2 3 MSB 16 LSB 17 18 1 2 3 MSB 16 LSB 17 18 1 2 L_ch R_ch FIGURE 2. “I2S” Data Input Timing. LRCKIN tBCH BCKIN tBCY DIN tDS tDH tBL tBCL tLB 1.4V 1.4V 1.4V BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width Low : tBCY : tBCH : tBCL : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns (min) : 30ns (min) BCKIN Rising Edge to LRCIN Edge : tBL LRCIN Edge to BCKIN Rising Edge : tLB DIN Set-up Time DIN Hold Time : tDS : tDH FIGURE 3. Audio Data Input Timing. SYSTEM CLOCK The system clock for PCM1733 must be either 256fS or 384fS, where fS is the audio sampling frequency (LRCIN), typically 32kHz, 44.1kHz or 48kHz. The system clock is used to operate the digital filter and the noise shaper. The system clock input (SCKI) is at pin 14. Timing conditions for SCKI are shown in Figure 4. tSCKIH 2.0V SCKI 0.8V tSCKIL System Clock Pulse Width High System Clock Pulse Width Low tSCKIH tSCKIL 13ns (min) 13ns (min) FIGURE 4. System Clock Timing Requirements. ® PCM1733 6 PCM1733 has a system clock detection circuit which automatically detects the frequency, either 256fS or 384fS. The system clock should be synchronized with LRCIN (pin 1), but PCM1733 can compensate for phase differences. If the phase difference between LRCIN and system clock is greater than ±6 bit clocks (BCKIN), the synchronization is performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization function. Table I shows the typical system clock frequency inputs for the PCM1733. SYSTEM CLOCK FREQUENCY (MHz) 256fS 8.192 11.2896 12.288 384fS 12.288 16.9340 18.432 FORMAT 0 1 Normal Format (MSB-first, right-justified) I2S Format (Philips serial data protocol) TABLE II. Input Format Selection. RESET PCM1733 has an internal power-on reset circuit. The internal power-on reset initializes (resets) when the supply voltage VCC > 2.2V (typ). The power-on reset has an initialization period equal to 1024 system clock periods after VCC > 2.2V. During the initialization period, the outputs of the DAC are invalid, and the analog outputs are forced to VCC/2. Figure 6 illustrates the power-on reset and reset-pin reset timing. DE-EMPHASIS CONTROL Pin 12 (DM) enables PCM1733’s de-emphasis function. Deemphasis operates only at 44.1kHz. DM 0 1 SAMPLING RATE (LRCIN) 32kHz 44.1kHz 48kHz TABLE I. System Clock Frequencies vs Sampling Rate. TYPICAL CONNECTION DIAGRAM Figure 5 illustrates the typical connection diagram for PCM1733 used in a stand-alone application. INPUT DATA FORMAT PCM1733 can accept input data in either normal (MSB-first, right-justified) or I2S formats. When pin 13 (FORMAT) is LOW, normal data format is selected; a HIGH on pin 13 selects I2S format. De-emphasis OFF De-emphasis ON (44.1kHz) TABLE III. De-emphasis Control Selection. +5V Analog 7 2 PCM Audio Data Processor 3 1 GND DIN BCKIN LRCIN PCM1733 VOUTR 6 8 VCC VOUTL CAP 9 5 + 10µF Post LPF Post LPF Lch Analog Out Rch Analog Out 14 256fS/384fS CLK SCKI FORMAT DM 13 12 Mode Control FIGURE 5. Typical Connection Diagram. VCC 2.6V 2.2V 1.8V Reset Reset Removal Internal Reset 1024 system (= SCKI) clocks SCKI Clock FIGURE 6. Internal Power-On Reset Timing. ® 7 PCM1733 INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0 APPLICATION CONSIDERATIONS DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1733: TD = 11.125 x 1/fS For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1733 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. The performance of the internal low pass filter from DC to 24kHz is shown in Figure 7. The higher frequency rolloff of the filter is shown in Figure 8. If the user’s application has the PCM1733 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 9. For some applications, a passive RC filter or 2nd-order filter may be adequate. 0.5 dB 0 –0.5 –1.0 20 100 1k Frequency (Hz) 10k 24k FIGURE 7. Low Pass Filter Frequency Response. INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M 10M Frequency (Hz) dB FIGURE 8. Low Pass Filter Wideband Frequency Response. BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. It is also recommended to include a 0.1µF ceramic capacitor in parallel with the 10µF tantalum bypass capacitor. GAIN vs FREQUENCY 6 Gain –14 1500pF + VSIN – –74 –270 10kΩ 10kΩ 680pF 10kΩ 100pF 0 90 –54 Phase –180 –94 100 1k 10k Frequency (Hz) 100k 1M –360 FIGURE 9. 3rd-Order LPF. ® PCM1733 8 Phase (°) OPA134 Gain (dB) –34 –90 + In 8fS 18-Bit + – Z–1 + + Z–1 – + + Z–1 + + 5-level Quantizer + 4 3 Out 48fS (384fS) 64fS (256fS) 2 1 0 FIGURE 10. 5-Level ∆Σ Modulator Block Diagram. THEORY OF OPERATION The delta-sigma section of PCM1733 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 10. This 5-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 96fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 11. 5-LEVEL DELTA SIGMA MODULATOR 20 0 –20 Gain (–dB) –40 –60 –80 –100 –120 –140 –160 0 5 10 15 20 25 Frequency (kHz) FIGURE 11. Quantization Noise Spectrum. ® 9 PCM1733