PCM1794DB

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         FEATURES D 24-Bit Resolution D Analog Performance: − Dynamic Range: 132 dB (9 V RMS, Mono) 129 dB (4.5 V RMS, Stereo) 127 dB (2 V RMS, Stereo) − THD+N: 0.0004% D Differential Current Output: 7.8 mA p-p D 8× Oversampling Digital Filter: − Stop-Band Attenuation: –130 dB − Pass-Band Ripple: ±0.00001 dB D Sampling Frequency: 10 kHz to 200 kHz D System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect D Accepts 16- and 24-Bit Audio Data D PCM Data Formats: Standard, I2S, and Left-Justified D Optional Interface Available to External Digital Filter or DSP D D D D Digital De-Emphasis Digital Filter Rolloff: Sharp or Slow Soft Mute Zero Flag D Dual-Supply Operation: − 5-V Analog, 3.3-V Digital D 5-V Tolerant Digital Inputs D Small 28-Lead SSOP Package APPLICATIONS D A/V Receivers D DVD Players D Musical Instruments D HDTV Receivers D Car Audio Systems D Digital Multitrack Recorders D Other Applications Requiring 24-Bit Audio DESCRIPTION The PCM1794 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1794 provides balanced current outputs, allowing the user to optimize analog performance externally. Sampling rates up to 200 kHz are supported. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1794DB 28-lead SSOP 28DB –25°C to 85°C PCM1794 ORDERING NUMBER TRANSPORT MEDIA PCM1794DB Tube PCM1794DBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1794 VCC1, VCC2L, VCC2R VDD Supply voltage –0.3 V to 6.5 V –0.3 V to 4 V ±0.1 V Supply voltage differences: VCC1, VCC2L, VCC2R ±0.1 V Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE, RST, Digital input voltage –0.3 V to 6.5 V ZERO –0.3 V to (VDD + 0.3 V) < 4 V –0.3 V to (VCC + 0.3 V) < 6.5 V Analog input voltage ±10 mA Input current (any pins except supplies) Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 250°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794DB PARAMETER TEST CONDITIONS MIN RESOLUTION TYP MAX 24 UNIT Bits DATA FORMAT Standard, I2S, left justified Audio data interface format Audio data bit length fS 16-, 24-bit selectable Audio data format MSB first, 2s complement Sampling frequency 10 System clock frequency 200 kHz 128, 192, 256, 384, 512, 768 fS DIGITAL INPUT/OUTPUT Logic family TTL compatible VIH VIL Input logic level IIH IIL Input logic current VIN = VDD VIN = 0 V VOH VOL Output logic level IOH = –2 mA IOL = 2 mA 2 2 0.8 10 –10 VDC µA 2.4 0.4 VDC 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794DB PARAMETER TEST CONDITIONS MIN TYP MAX 0.0004% 0.0008% UNIT DYNAMIC PERFORMANCE (2-V RMS OUTPUT) (1)(2) THD+N at VOUT = 0 dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz Dynamic range Channel separation Dynamic range Signal-to-noise ratio Channel separation 127 127 EIAJ, A-weighted, fS = 192 kHz 127 123 127 EIAJ, A-weighted, fS = 192 kHz 127 fS = 44.1 kHz fS = 96 kHz 120 dB 127 EIAJ, A-weighted, fS = 96 kHz fS = 192 kHz Level linearity error VOUT = –120 dB DYNAMIC PERFORMANCE (4.5-V RMS Output) (1)(3) THD+N at VOUT = 0 dB 0.0015% 123 EIAJ, A-weighted, fS = 96 kHz EIAJ, A-weighted, fS = 44.1 kHz Signal-to-noise ratio 0.0008% dB 123 122 dB 120 ±1 fS = 44.1 kHz fS = 96 kHz 0.0004% fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz 0.0015% dB 0.0008% 129 EIAJ, A-weighted, fS = 96 kHz 129 EIAJ, A-weighted, fS = 192 kHz 129 EIAJ, A-weighted, fS = 44.1 kHz 129 EIAJ, A-weighted, fS = 96 kHz 129 EIAJ, A-weighted, fS = 192 kHz 129 fS = 44.1 kHz fS = 96 kHz 124 fS = 192 kHz 121 fS = 44.1 kHz fS = 96 kHz 0.0004% fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz 0.0015% 123 dB dB dB DYNAMIC PERFORMANCE (MONO MODE) (1)(3) THD+N at VOUT = 0 dB Dynamic range Signal-to-noise ratio 0.0008% 132 EIAJ, A-weighted, fS = 96 kHz 132 EIAJ, A-weighted, fS = 192 kHz 132 EIAJ, A-weighted, fS = 44.1 kHz 132 EIAJ, A-weighted, fS = 96 kHz 132 EIAJ, A-weighted, fS = 192 kHz 132 dB dB (1) Filter condition: THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Twot Cascade audio measurement system by Audio Precision in the averaging mode. (2) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 24. (3) Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 25. Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners. 3 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794DB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT Gain error –6 ±2 6 % of FSR Gain mismatch, channel-to-channel –3 ±0.5 3 % of FSR –2 ±0.5 2 % of FSR Bipolar zero error At BPZ Output current Full scale (0 dB) 7.8 mA p-p Center current At BPZ –6.2 mA DIGITAL FILTER PERFORMANCE ±0.004 De-emphasis error dB FILTER CHARACTERISTICS-1: SHARP ROLLOFF Pass band ±0.00001 dB 0.454 fS –3 dB Stop band 0.49 fS 0.546 fS ±0.00001 Pass-band ripple Stop-band attenuation Stop band = 0.546 fS –130 Delay time dB dB 55/fS s FILTER CHARACTERISTICS-2: SLOW ROLLOFF Pass band ±0.04 dB 0.254 fS –3 dB Stop band 0.46 fS 0.732 fS ±0.001 Pass-band ripple Stop-band attenuation Stop band = 0.732 fS –100 Delay time dB dB 18/fS s POWER SUPPLY REQUIREMENTS VDD VCC1 VCC2L VCC2R 3 3.3 3.6 VDC 4.75 5 5.25 VDC fS = 44.1 kHz fS = 96 kHz 12 15 fS = 192 kHz fS = 44.1 kHz 45 fS = 96 kHz fS = 192 kHz 35 fS = 44.1 kHz fS = 96 kHz 205 fS = 192 kHz 335 Voltage range IDD Supply current (1) ICC Power dissipation (1) 23 33 mA 40 mA 37 250 250 mW TEMPERATURE RANGE Operation temperature θJA Thermal resistance (1) Input is BPZ data. 4 –25 28-pin SSOP 85 100 °C °C/W 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 PIN ASSIGNMENTS PCM1794 (TOP VIEW) MONO CHSL DEM LRCK DATA BCK SCK DGND VDD MUTE FMT0 FMT1 ZERO RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC2L AGND3L IOUTL– IOUTL+ AGND2 VCC1 VCOML VCOMR IREF AGND1 IOUTR– IOUTR+ AGND3R VCC2R 5 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 Terminal Functions TERMINAL NAME PIN I/O DESCRIPTIONS AGND1 19 – Analog ground (internal bias) AGND2 24 – Analog ground (internal bias) AGND3L 27 – Analog ground (L-channel DACFF) AGND3R 16 – BCK 6 I Analog ground (R-channel DACFF) Bit clock input (1) CHSL 2 I DATA 5 I L-, R-channel select (1) Serial audio data input (1) DEM 3 I De-emphasis enable (1) DGND 8 – Digital ground FMT0 11 I FMT1 12 I Audio data format select (1) Audio data format select (1) IOUTL+ IOUTL– 25 O L-channel analog current output + 26 O L-channel analog current output – IOUTR+ IOUTR– 17 O R-channel analog current output + 18 O R-channel analog current output – IREF LRCK 20 – 4 I Output current reference bias pin Left and right clock (fS) input (1) MONO 1 I MUTE 10 I Monaural mode enable (1) Mute control (1) RST 14 I Reset(1) SCK 7 I System clock input(1) VCC1 VCC2L 23 – Analog power supply, 5 V 28 – Analog power supply (L-channel DACFF), 5 V VCC2R VCOML 15 – Analog power supply (R-cahnnel DACFF), 5 V 22 – L-channel internal bias decoupling pin VCOMR VDD 21 – R-channel internal bias decoupling pin 9 – Digital power supply, 3.3 V ZERO 13 O (1) Schmitt-trigger input, 5-V tolerant 6 Zero flag 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 FUNCTIONAL BLOCK DIAGRAM IOUTL– LRCK BCK DATA Audio Data Input I/F Current Segment DAC VOUTL IOUTL+ MUTE FMT1 FMT0 MONO CHSL Function Control I/F 8 Oversampling Digital Filter and Function Control VCOML Advanced Segment DAC Modulator Bias and Vref I/V and Filter IREF VCOMR IOUTR– Current Segment DAC DEM RST VOUTR IOUTR+ I/V and Filter System Clock Manager VCC2R VCC2L VCC1 AGND3R AGND3L AGND2 AGND1 VDD Power Supply DGND Zero Detect SCK ZERO 7 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY 0 2 0.00002 −50 1 0.00001 −100 Amplitude – dB Amplitude – dB AMPLITUDE vs FREQUENCY −150 −1 –0.00001 −200 0 1 2 3 4 0 −2 –0.00002 0.0 0.1 Frequency [× fS] 0.2 0.3 0.4 0.5 Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2. Pass-Band Ripple, Sharp Rolloff AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 −2 −4 −50 Amplitude – dB Amplitude – dB −6 −100 −8 −10 −12 −14 −150 −16 −18 −200 0 1 2 3 4 Frequency [× fS] Figure 3. Frequency Response, Slow Rolloff 8 −20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [× fS] Figure 4. Transition Characteristics, Slow Rolloff 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 20 0.020 fS = 44.1 kHz fS = 44.1 kHz 15 0.015 De-Emphasis Error – dB De-Emphasis Level – dB −2 −4 −6 10 0.010 5 0.005 0 −5 –0.005 −10 –0.010 −8 −15 –0.015 −10 −20 –0.020 0 2 4 6 8 10 12 14 f – Frequency – kHz Figure 5 16 18 20 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz Figure 6 9 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 132 130 fS = 96 kHz Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 0.01 fS = 192 kHz 0.001 fS = 96 kHz fS = 48 kHz 128 fS = 192 kHz 126 124 fS = 48 kHz 0.0001 4.50 4.75 5.00 5.25 122 4.50 5.50 VCC – Supply Voltage – V 4.75 Figure 7 130 128 Channel Separation – dB SNR – Signal-to-Noise Ratio – dB 130 fS = 96 kHz fS = 192 kHz fS = 48 kHz 126 124 126 124 fS = 96 kHz fS = 48 kHz fS = 192 kHz 122 4.75 5.00 5.25 5.50 120 4.50 VCC – Supply Voltage – V Figure 9 NOTE: TA = 25°C, VDD = 3.3 V, measurement circuit is Figure 25 (VOUT = 4.5 V rms). 10 5.50 CHANNEL SEPARATION vs SUPPLY VOLTAGE 132 122 4.50 5.25 Figure 8 SIGNAL-to-NOISE RATIO vs SUPPLY VOLTAGE 128 5.00 VCC – Supply Voltage – V 4.75 5.00 5.25 VCC – Supply Voltage – V Figure 10 5.50 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 132 130 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 0.01 fS = 192 kHz 0.001 fS = 96 kHz 128 fS = 96 kHz fS = 48 kHz 126 124 fS = 48 kHz 0.0001 −50 −25 0 25 50 75 122 −50 100 TA – Free-Air Temperature – °C −25 25 50 75 100 Figure 12 SIGNAL-to-NOISE RATIO vs FREE-AIR TEMPERATURE CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 132 130 130 128 Channel Separation – dB fS = 96 kHz 128 fS = 192 kHz fS = 48 kHz 126 124 122 −50 0 TA – Free-Air Temperature – °C Figure 11 SNR – Signal-to-Noise Ratio – dB fS = 192 kHz 126 fS = 48 kHz 124 fS = 192 kHz fS = 96 kHz 122 −25 0 25 50 75 100 120 −50 TA – Free-Air Temperature – °C Figure 13 −25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 14 NOTE: VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25 (VOUT = 4.5 V rms). 11 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 −20 −20 −40 −60 Amplitude – dB Amplitude – dB −40 −80 −100 −120 −60 −80 −100 −120 −140 −140 −160 −180 −160 0 2 4 6 8 10 12 14 16 18 20 0 10 20 f – Frequency – kHz 30 40 50 60 70 80 90 100 f – Frequency – kHz NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V, NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25. VCC = 5 V, measurement circuit is Figure 25. Figure 15. –60-db Output Spectrum, BW = 20 kHz Figure 16. –60-db Output Spectrum, BW = 100 kHz TOTAL HARMONIC DISTORTION + NOISE vs INPUT LEVEL THD+N – Total Harmonic Distortion + Noise – % 10 1 0.1 0.01 0.001 0.0001 −100 −80 −60 −40 −20 Input Level – dBFS NOTE: fS = 48 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 25. Figure 17. THD+N vs Input Level 12 0 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1794 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1794 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators is an excellent choice for providing the PCM1794 system clock. Table 1. System Clock Rates for Common Audio Sampling Frequencies SYSTEM CLOCK FREQUENCY (fSCK) (MHz) SAMPLING FREQUENCY 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1 kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688 48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 96 kHz 12.288 18.432 24.576 36.864 192 kHz 24.576 36.864 49.152 73.728 49.152 (1) 73.728 (1) (1) This system clock rate is not supported for the given sampling frequency. t(SCKH) H 2V System Clock (SCK) 0.8 V L t(SCKL) PARAMETERS t(SCY) MIN MAX UNITS t(SCY) System clock pulse cycle time t(SCKH) System clock pulse duration, HIGH 13 ns 0.4t(SCY) ns t(SCKL) System clock pulse duration, LOW 0.4t(SCY) ns Figure 18. System Clock Input Timing Power-On and External Reset Functions The PCM1794 includes a power-on reset function. Figure 19 shows the operation of this function. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V. The PCM1794 also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the PCM1794 to initialize to its default reset state. Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1794 power up and system clock activation. 13 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Reset Removal Internal Reset 1024 System Clocks System Clock Figure 19. Power-On Reset Timing RST (Pin 14) 50 % of VDD t(RST) Reset Reset Removal Internal Reset 1024 System Clocks System Clock t(RST) PARAMETERS MIN Reset pulse duration, LOW 20 Figure 20. External Reset Timing 14 MAX UNITS ns 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1794 on the rising edge of BCK. LRCK is the serial audio left/right word clock. The PCM1794 requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock. If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized within 1/fS and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system clock is completed. PCM Audio Data Formats and Timing The PCM1794 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits, FMT1 (pin 12), and FMT0 (pin 11) as shown in Table 2. All formats require binary twos-complement, MSB-first audio data. Figure 21 shows a detailed timing diagram for the serial audio interface. 50% of VDD LRCK t(BCH) t(BCL) t(LB) 50% of VDD BCK t(BCY) t(BL) 50% of VDD DATA t(DS) t(DH) PARAMETERS MIN MAX UNITS t(BCY) t(BCL) BCK pulse cycle time 70 ns BCK pulse duration, LOW 30 ns t(BCH) t(BL) BCK pulse duration, HIGH 30 ns BCK rising edge to LRCK edge 10 ns t(LB) t(DS) LRCK edge to BCK rising edge 10 ns DATA setup time 10 ns t(DH) — DATA hold time 10 ns LRCK clock duty 50% ± 2 bit clocks Figure 21. Timing of Audio Interface 15 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 (1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW 1/fS LRCK R-Channel L-Channel BCK Audio Data Word = 16-Bit DATA 14 15 16 1 2 MSB 15 16 1 2 15 16 LSB Audio Data Word = 24-Bit DATA 22 23 24 1 2 23 24 1 2 23 24 LSB MSB (2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK R-Channel L-Channel BCK Audio Data Word = 24-Bit DATA 1 2 23 24 MSB 1 2 23 24 1 2 LSB (3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK Audio Data Word = 24-Bit DATA 1 23 24 2 MSB 1 2 LSB Figure 22. Audio Data Input Formats 16 23 24 1 2 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 FUNCTION DESCRIPTIONS Audio data format Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1794 also supports monaural mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1794 can select the DF rolloff characteristics. Table 2. Audio Data Format Select MONO CHSL FMT1 FMT0 STEREO/MONO DF ROLLOFF 0 FORMAT I2S 0 0 0 0 0 0 Stereo Sharp 1 Left-justified format Stereo 0 0 Sharp 1 0 Standard, 16-bit Stereo Sharp 0 0 0 1 1 Sharp 0 0 Standard, 24-bit I2S Stereo 1 Stereo Slow 0 1 0 1 Left-justified format Stereo Slow 0 1 1 0 Standard, 16-bit Stereo Slow 0 1 1 1 Mono – 1 0 0 0 Digital filter bypass I2S Mono, L-channel Sharp 1 0 0 1 Left-justified format Mono, L-channel Sharp 1 0 1 0 Standard, 16-bit Mono, L-channel Sharp 1 0 1 1 Sharp 1 0 0 Standard, 24-bit I2S Mono, L-channel 1 Mono, R-channel Sharp 1 1 0 1 Left-justified format Mono, R-channel Sharp 1 1 1 0 Standard, 16-bit Mono, R-channel Sharp 1 1 1 1 Standard, 24-bit Mono, R-channel Sharp Soft Mute The PCM1794 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned to the bipolar zero level in –0.5-dB steps with a transition speed of 1/fS per step. This system provides pop-free muting of the DAC output. De-Emphasis The PCM1794 has a de-emphasis filters for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled using DEM (pin 3). Zero Detect When the PCM1794 detects that the audio input data in the L-channel and the R-channel is continuously zero for 1024 LRCKs in the PCM mode or that the audio input data is continuously zero for 1024 WDCKs in the external filter mode, the PCM1794 sets ZERO (pin 13) to HIGH. 17 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 TYPICAL CONNECTION DIAGRAM Cf 5V Rf 0.1 µF Controller PCM Audio Data Source 0.1 µF Controller 1 MONO VCC2L 28 2 CHSL AGND3L 27 3 DEM IOUTL– 26 4 LRCK IOUTL+ 25 5 DATA AGND2 24 6 BCK VCC1 23 7 SCK VCOML 22 8 DGND 9 VDD PCM1794 VCOMR 21 IREF 20 10 MUTE AGND1 19 11 FMT0 IOUTR– 18 12 FMT1 IOUTR+ 17 13 ZERO AGND3R 16 VCC2R 15 14 RST + 10 µF – + Cf Rf 5V – 47 µF + – + Cf Rf 5V – 10 µF + 3.3 V + 10 µF Figure 23. Typical Application Circuit 18 VOUT R-Channel Rf 10 kΩ + Differential to Single Converter With Low-Pass Filter Cf 47 µF 0.1 µF VOUT L-Channel + + 10 µF + Differential to Single Converter With Low-Pass Filter 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 APPLICATION INFORMATION APPLICATION CIRCUIT The design of the application circuit is very important in order to actually realize the high S/N ratio of which the PCM1794 is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the circuit of Figure 24, the output level is 2 V RMS, and 127 dB S/N is achieved. The circuit of Figure 25 can realize the highest performance. In this case the output level is set to 4.5 V RMS and 129 dB S/N is achieved (stereo mode). In monaural mode, if the output of the L-channel and R-channel is used as a balanced output, 132 dB S/N is achieved (see Figure 26). I/V Section The current of the PCM1794 on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 7.8 mA p-p at 0 dB (full scale). The voltage output level of the I/V converter (Vi) is given by following equation: Vi = 7.8 mA p–p × Rf (Rf : feedback resistance of I/V converter) An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic performance of the I/V section. Differential Section The PCM1794 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function. The operational amplifier recommended for the differential circuit is the Linear Technology LT1028, because its input noise is low. 19 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 C1 2200 pF R1 750 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 270 Ω 6 + C3 2700 pF R3 560 Ω C19 33 pF 7 2 U1 NE5534 4 C15 0.1 µF 3 5 – 6 + 4 C12 0.1 µF VEE R4 560 Ω R6 270 Ω U3 LT1028 C16 0.1 µF C4 2700 pF VEE C2 2200 pF R2 750 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 5 – VCC = 15 V VEE = –15 V fC = 217 kHz 8 6 + 4 U2 NE5534 C14 0.1 µF VEE Figure 24. Measurement Circuit, VOUT = 2 V RMS 20 R7 100 Ω 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 360 Ω 6 + C3 2700 pF R3 360 Ω C19 33 pF 7 2 U1 NE5534 4 C15 0.1 µF 3 5 – 6 + 4 C12 0.1 µF VEE R4 360 Ω R6 360 Ω R7 100 Ω U3 LT1028 C16 0.1 µF C4 2700 pF VEE C2 2200 pF R2 820 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 VCC = 15 V VEE = –15 V fC = 162 kHz 5 – 8 6 + 4 U2 NE5534 C14 0.1 µF VEE Figure 25. Measurement Circuit, VOUT = 4.5 V RMS 21 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 IOUTL– (Pin 26) IOUT– OUT+ Figure 25 Circuit IOUTL+ (Pin 25) IOUT+ 3 1 2 IOUTR– (Pin 18) IOUT– OUT– Figure 25 Circuit IOUTR+ (Pin 17) Balanced Out IOUT+ Figure 26. Measurement Circuit for Monaural Mode APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE VDD 1 MONO 2 VCC2L 28 CHSL AGND3L 27 3 DEM IOUTL– 26 WDCK 4 LRCK IOUTL+ 25 DATA 5 DATA AGND2 24 BCK 6 BCK VCC1 23 SCK 7 SCK VCOML 22 VCOMR 21 IREF 20 10 MUTE AGND1 19 11 FMT0 IOUTR– 18 12 FMT1 IOUTR+ 17 13 ZERO AGND3R 16 VCC2R 15 External Filter Device PCM1794 8 DGND 9 VDD 14 RST Analog Output Stage (See Figure 23) Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application 22 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter to perform the interpolation function. The following pin settings enable the external digital filter application mode. D D D D MONO (pin 1) = LOW CHSL (Pin 2) = HIGH FMT0 (Pin 11) = HIGH FMT1 (pin 12) = HIGH The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 27. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, fS. System Clock (SCK) and Interface Timing The PCM1794 in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is shown in Figure 29. Audio Format The PCM1794 in the external digital filter interface mode supports right-justified audio formats including 24-bit audio data, as shown in Figure 28. 1/4 fS or 1/8 fS WDCK BCK Audio Data Word = 24-Bit DATA 23 24 1 2 3 MSB 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LSB Figure 28. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application 23 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 WDCK 50% of VDD t(BCH) t(BCL) t(LB) 50% of VDD BCK t(BCY) t(BL) 50% of VDD DATA t(DS) t(DH) PARAMETER MIN t(BCY) BCK pulse cycle time t(BCL) BCK pulse duration, LOW MAX UNITS 20 ns 7 ns t(BCH) BCK pulse duration, HIGH t(BL) BCK rising edge to WDCK falling edge 7 ns 5 ns t(LB) t(DS) WDCK falling edge to BCK rising edge 5 ns DATA setup time 5 ns t(DH) DATA hold time 5 ns Figure 29. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application THEORY OF OPERATION Upper 6 Bits ICOB Decoder 0–62 Level 0–66 Advanced DWA Digital Input 24 Bits 8 fS MSB and Lower 18 Bits 3rd-Order 5-Level Sigma-Delta Current Segment DAC Analog Output 0–4 Level Figure 30. Advanced Segment DAC The PCM1794 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1794 provides balanced current outputs. Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed by a five-level third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the modulator is equivalent to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order delta-sigma modulator are summed together to create an up-to-66-level digital code, and then processed by data-weighted averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is converted to an analog output in the differential-current segment section. This architecture has overcome the various drawbacks of conventional multibit processing and also achieves excellent dynamic performance. 24 
 www.ti.com SLES080C – MAY 2003 – REVISED NOVEMBER 2006 Analog output The following table and Figure 31 show the relationship between the digital input code and analog output. IOUTN [mA] IOUTP [mA] VOUTN [V] VOUTP [V] 800000 (–FS) 000000 (BPZ) 7FFFFF (+FS) –2.3 –6.2 –10.1 –10.1 –6.2 –2.3 –1.725 –4.65 –7.575 –7.575 –4.65 –1.725 VOUT [V] –2.821 0 2.821 NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the measurement circuit of Figure 24. OUTPUT CURRENT vs INPUT CODE 0 IO – Output Current – mA −2 IOUTN −4 −6 −8 −10 IOUTP −12 800000(–FS) 000000(BPZ) 7FFFFF(+FS) Input Code – Hex Figure 31. The Relationship Between Digital Input and Analog Output 25 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PCM1794DB NRND SSOP DB 28 47 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 PCM1794 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of