PCM1800EG4

PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 SINGLE-ENDED ANALOG-INPUT 20-BIT STEREO ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • Dual 20-Bit Monolithic ΔΣ ADC • Single-Ended Voltage Input • 64× Oversampling Decimation Filter: – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB • High Performance: – THD+N: –88 dB (typical) – SNR: 95 dB (typical) – Dynamic Range: 95 dB (typical) – Internal High-Pass Filter • PCM Audio Interface: – Master/Slave Modes – Four Data Formats • Sampling Rate: 4 kHz to 48 kHz • System Clock: 256 fS, 384 fS, or 512 fS • Single 5-V Power Supply • Small 24-Pin SSOP Package • • • • 1 23 DVD Recorders DVD Receivers AV Amplifier Receivers Electric Musical Instruments DESCRIPTION The PCM1800 is a low-cost, single-chip stereo analog-to-digital converter (ADC) with single-ended analog voltage inputs. The PCM1800 uses a delta-sigma modulator with 64 times oversampling, including a digital decimation filter and a serial interface which supports both master and slave modes and four data formats. The PCM1800 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. The PCM1800 is fabricated using a highly advanced CMOS process and is available in a small 24-pin SSOP package. Digital Output Analog Input (L) Analog Front-End Analog Input (R) Delta-Sigma Modulator Digital Decimation Filter Serial Interface and Format Control Mode/Format Control System Clock B0003-01 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2008, Texas Instruments Incorporated PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted PARAMETER TEST CONDITIONS RESOLUTION PCM1800E MIN TYP MAX 20 UNITS Bits DIGITAL INPUT/OUTPUT VIH (1) VIL (1) IIN (2) IIN (3) VOH (4) VOL fS (4) 2 Input logic level 0.8 ±1 Input logic current Output logic level 100 IOH = –1.6 mA 4.5 IOL = 3.2 mA Sampling frequency 0.5 VDC µA VDC 4 44.1 48 256 fS 1.024 11.2896 12.288 384 fS 1.536 16.9344 18.432 512 fS 2.048 22.5792 24.576 Gain mismatch, channel-to-channel ±1 ±2.5 Gain error ±2 ±5 Gain drift ±20 ppm of FSR/°C System clock frequency kHz MHz DC ACCURACY % of FSR % of FSR Bipolar zero error High-pass filter bypassed ±2 % of FSR Bipolar zero drift High-pass filter bypassed ±20 ppm of FSR/°C DYNAMIC PERFORMANCE (5) THD+N at FS (–0.5 dB) –88 THD+N at –60 dB –80 dB –92 dB Dynamic range A-weighted 90 95 dB Signal-to-noise ratio A-weighted 90 95 dB 88 93 dB Channel separation DYNAMIC PERFORMANCE (5) Dynamic range 16-bit, A-weighted 94 dB Signal-to-noise ratio 16-bit, A-weighted 94 dB Channel separation 16-bit 92 dB FS (VIN = 0 dB) 2.828 Vp-p Center voltage 2.1 VDC Input impedance 30 kΩ 170 kHz ANALOG INPUT Input range Antialiasing filter frequency response CEXT = 470 pF, –3 dB DIGITAL FILTER PERFORMANCE (1) (2) (3) (4) (5) 2 Pins 6, 7, 8, 9, 10, 11, 16 and 12, 13, 14: RSTB, BYPAS, FMT0, FMT1, MODE0, MODE1, SYSCLK, and FSYNC, LRCK, BCK in slave mode Pins 16 and 12, 13, 14: SYSCLK and FSYNC, LRCK, BCK in slave mode (Schmitt-trigger input) Pins 6, 7, 8, 9, 10, 11: RSTB, BYPAS, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 100-kΩ typical pulldown resistor) Pins 15 and 12, 13, 14: DOUT and FSYNC, LRCK, BCK in master mode fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF and 400-Hz HPF in the performance calculation. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted PARAMETER TEST CONDITIONS PCM1800E MIN TYP Pass band 0.454 fS Stop band 0.583 fS ±0.05 Stop-band attenuation –65 Delay time (latency) –3 dB UNITS Hz Hz Pass-band ripple High-pass frequency response MAX dB dB 17.4/fS s 0.019 fS mHz POWER SUPPLY REQUIREMENTS VCC VDD Voltage range 4.5 5 5.5 4.5 5 5.5 VDC Supply current (6) VCC = VDD = 5 V 18 25 mA Power dissipation VCC = VDD = 5 V 90 125 mW °C TEMPERATURE RANGE TA Operation –25 85 Tstg Storage –55 125 θJA Thermal resistance (6) 100 °C °C/W No load on DOUT (pin 15) in the slave mode Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 3 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com PIN CONFIGURATION PCM1800 (TOP VIEW) VINL VREF1 REFCOM VREF2 VINR RSTB BYPAS FMT0 FMT1 MODE0 MODE1 FSYNC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 AGND VCC CINPL CINNL CINPR CINNR VDD DGND SYSCLK DOUT BCK LRCK P0004-01 PIN ASSIGNMENTS (1) NAME PIN I/O DESCRIPTION AGND 24 – BCK 14 I/O BYPAS 7 I High-pass filter bypass control (1) CINNL 21 – Antialias filter capacitor (–), Lch CINNR 19 – Antialias filter capacitor (–), Rch CINPL 22 – Antialias filter capacitor (+), Lch CINPR 20 – Antialias filter capacitor (+), Rch DGND 17 – Digital ground DOUT 15 O Audio data output FMT0 8 I Audio data format 0 (1) FMT1 9 I Audio data format 1 (1) FSYNC 12 I/O Frame synchronization, input/output LRCK 13 I/O Sampling clock input/output (fS) MODE0 10 I Master/slave mode selection 0 (1) MODE1 11 I Master/slave mode selection 1 (1) REFCOM 3 – Reference decoupling common SYSCLK 16 I System clock input, 256 fS, 384 fS, or 512 fS RSTB 6 I Reset input, active LOW (1) VCC 23 – Analog power supply VDD 18 – Digital power supply Analog ground Bit clock input/output VINL 1 I Analog input, Lch VINR 5 I Analog input, Rch VREF1 2 – Reference 1 decoupling capacitor VREF2 4 – Reference 2 decoupling capacitor With 100-kΩ typical pulldown resistor PACKAGE/ORDERING INFORMATION 4 PRODUCT PACKAGE TYPE PACKAGE CODE PACKAGE MARKING PCM1800E 24-pin SSOP DB PCM1800E ORDERING NUMBER TRANSPORT MEDIA QUANTITY PCM1800E Rails 58 PCM1800E/2K Tape and reel 2000 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ABSOLUTE MAXIMUM RATINGS Supply voltage: VDD, VCC –0.3 V to 6.5 V Supply voltage differences ±0.1 V GND voltage differences ±0.1 V Digital input voltage –0.3 V to (VDD + 0.3 V), < 6.5 V Analog input voltage –0.3 V to (VCC + 0.3 V), < 6.5 V Input current (any pin except supplies) ±10 mA Power dissipation 300 mW Operating temperature range –25°C to 85°C Storage temperature –55°C to 125°C Lead temperature, soldering 260°C, 5 s Package temperature (IR reflow, peak) 235°C RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Analog supply voltage, VCC 4.5 5 5.5 Digital supply voltage, VDD 4.5 5 5.5 Analog input voltage, full-scale (–0 dB) 2.828 Digital input logic family Digital input clock frequency UNIT V V Vp-p TTL System clock Sampling clock 8.192 24.576 MHz 32 48 kHz Digital output load capacitance 10 Operating free-air temperature, TA –25 pF 85 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 °C 5 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com BLOCK DIAGRAM ADC CINPL CINNL (+) VINL Single-End/ Differential Converter (−) 5th Order Delta-Sigma Modulator ×1/64 Decimation and High-Pass Filter VREF1 REFCOM VREF2 BCK Reference LRCK Serial Data Interface FSYNC (−) VINR Single-End/ Differential Converter (+) 5th Order Delta-Sigma Modulator DOUT CINNR MODE0 CINPR Mode/Format Control Interface MODE1 FMT0 FMT1 BYPAS Clock/Timing Control Reset/Power Control Power Supply VCC AGND DGND SYSCLK RSTB VDD B0004-01 6 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ANALOG FRONT-END (Single Channel) CEXT 470 pF CINPL 22 1.0 µF + 1 CINNL 21 30 kΩ VINL − − 1 kΩ (+) + + 1 kΩ 2 4.7 µF (−) Delta-Sigma Modulator VREF1 + REFCOM VREF 3 4.7 µF + 4 VREF2 S0011-01 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted DYNAMIC RANGE AND SNR vs TEMPERATURE 0.008 3 −60 dB 0.006 2 −0.5 dB 0.004 0.002 −25 1 0 25 50 75 TA − Free-Air Temperature − °C 98 Dynamic Range 96 96 SNR 94 94 92 92 90 −25 0 100 98 G001 Figure 1. 0 25 50 75 SNR − Signal-to-Noise Ratio − dB 4 Dynamic Range − dB 0.010 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N vs TEMPERATURE 90 100 TA − Free-Air Temperature − °C G002 Figure 2. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 7 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted DYNAMIC RANGE AND SNR vs POWER SUPPLY −60 dB 0.006 2 0.004 1 −0.5 dB 4.50 4.75 5.00 5.25 5.50 SNR 94 92 92 4.50 4.75 5.00 5.25 Figure 4. THD+N vs SYSTEM CLOCK and SAMPLING FREQUENCY THD+N vs OUTPUT DATA RESOLUTION 0.010 4 3 0.008 44.1 kHz −60 dB 0.006 2 32 kHz 48 kHz 44.1 kHz 0.004 1 −0.5 dB 32 kHz 48 kHz 0.002 0 384 fS 90 5.75 G004 G003 Figure 3. 256 fS 0.010 4 3 0.008 −60 dB 0.006 2 −0.5 dB 0.004 1 0.002 0 16-Bit 512 fS System Clock 20-Bit Resolution G005 Figure 5. 8 5.50 VCC − Supply Voltage − V VCC − Supply Voltage − V THD+N − Total Harm. Dist. + Noise at −0.5 dB − % 96 94 90 4.25 0 5.75 THD+N − Total Harm. Dist. + Noise at −0.5 dB − % 0.002 4.25 Dynamic Range 96 SNR − Signal-to-Noise Ratio − dB 3 98 THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.008 98 Dynamic Range − dB 4 THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N vs POWER SUPPLY G006 Figure 6. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted THD+N vs AMPLITUDE –60 dBFS FFT THD+N − Total Harmonic Distortion + Noise − dB 0 −20 Amplitude − dB −40 −60 −80 −100 −120 −140 2 4 6 8 10 12 14 16 18 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 −160 0 0 20 0 Amplitude − dBr f − Frequency − kHz G008 G007 Figure 7. Figure 8. THD+N − Total Harmonic Distortion + Noise − dB THD+N vs FREQUENCY −80 −82 −84 −86 −88 −90 −92 −94 −96 −98 −100 20 100 1k 10k 20k f − Frequency − Hz G009 Figure 9. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 9 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com TYPICAL PERFORMANCE CURVES FOR INTERNAL FILTERS All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted DECIMATION FILTER STOP-BAND ATTENUATION CHARACTERISTICS 0 0 −50 −25 Amplitude − dB Amplitude − dB OVERALL CHARACTERISTICS −100 −50 −75 −150 −100 0.00 −200 0 8 16 24 32 Normalized Frequency [× fS Hz] 0.25 0.50 0.75 Normalized Frequency [× fS Hz] G010 Figure 10. Figure 11. PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 1.00 G011 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS Hz] 0.5 −4.13 dB at 0.5 fS −10 0.45 0.47 0.49 G012 Figure 12. 0.51 0.53 Normalized Frequency [× fS Hz] 0.55 G013 Figure 13. All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless 10 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 TYPICAL PERFORMANCE CURVES FOR INTERNAL FILTERS (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, slave mode, fS = 44.1 kHz, 20-bit input data, and SYSCLK = 384 fS, unless otherwise noted otherwise noted HIGH-PASS FILTER HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.00 0.05 0.10 0.15 0.20 0.25 −1.0 0.0 0.30 0.35 0.40 Normalized Frequency [× fS/1000 Hz] 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency [× fS/1000 Hz] G014 Figure 14. G015 Figure 15. ANTIALIASING FILTER ANTIALIASING FILTER OVERALL FREQUENCY RESPONSE (CEXT = 470 pF, 1000 pF) ANTIALIASING FILTER PASS-BAND FREQUENCY RESPONSE (CEXT = 470 pF, 1000 pF) 0.2 0 470 pF 470 pF 0.0 Amplitude − dB Amplitude − dB −10 −20 1000 pF −30 −40 −0.2 1000 pF −0.4 −0.6 −0.8 −1.0 −50 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz G017 G016 Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 11 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com THEORY OF OPERATION The PCM1800 consists of a band-gap reference, two channels of a single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram illustrates the total architecture of the PCM1800 and the analog front-end diagram illustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 18 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. An internal high-precision reference with two external capacitors provides all the reference voltages that are required by the converter, and defines the full-scale voltage range of both channels. The internal single-to-differential voltage converter saves the design, space, and extra parts needed for external circuitry required by many delta-sigma converters. The internal full-differential architecture provides a wide dynamic range and excellent power-supply rejection performance. The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64-fS, 1-bit stream from the modulator is converted to 1-fS, 20-bit digital data by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a high-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial interface which provides flexible serial formats and master/slave modes. Analog In X(z) + − 1st SW-CAP Integrator + − 2nd SW-CAP Integrator + 3rd SW-CAP Integrator + + + − 4th SW-CAP Integrator + + H(z) 5th SW-CAP Integrator + + Qn(z) Digital Out Y(z) + Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] B0005-01 Figure 18. Simplified Diagram of the PCM1800 5th-Order Delta-Sigma Modulator SYSTEM CLOCK The system clock for the PCM1800 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling frequency. The system clock must be supplied on SYSCLK (pin 16). The PCM1800 also has a system-clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS. When the 384-fS or 512-fS system clock is in slave mode, the system clock is divided into 256 fS automatically. The 256-fS clock is used to operate the digital filter and the modulator. Table 1 lists the relationship of typical sampling frequencies and system clock frequencies. Figure 19 illustrates the system clock timing. 12 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz) 256 fs 384 fs 512 fs 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 tCLKIH tCLKIL 2.0 V SYSCLK 0.8 V T0005-03 System clock pulse duration, HIGH t(CLKIH) 12 ns (min) System clock pulse duration, LOW t(CLKIL) 12 ns (min) Figure 19. System Clock Timing RESET AND POWER DOWN The PCM1800 has both an internal power-on reset circuit and an external forced reset (RSTB, pin 6). The internal power-on reset initializes (resets) when the supply voltage (VCC/VDD) exceeds 4 V (typical). To initiate the reset sequence externally, apply a logic-level LOW to the RSTB pin. The RSTB pin is terminated by an internal pulldown resistor. If the RSTB pin is unconnected, the ADC remains in the reset state. Because the system clock is used as the clock signal for the reset circuit, the system clock must be supplied as soon as power is applied; more specifically, the device must receive at least three system clock cycles before VDD > 4 V and RSTB = HIGH. If this system clock requirement cannot be assured in an application, RSTB must be held LOW until the system clock is supplied. While VCC/VDD < 4 V (typical), RSTB = LOW, and for 1024 system clock periods after VCC/VDD > 4.0 V and RSTB = HIGH, the PCM1800 stays in the reset state and the digital output is forced to zero. The digital output is valid 18,436 fS periods after release from the reset state. During reset, the logic circuits and the digital filter stop operating and enter the power-down mode. Figure 20 and Figure 21 illustrate the internal power-on reset and external reset timing. VCC / VDD 4.4 V 4.0 V 3.6 V Reset Reset Removal Internal Reset 3 Clocks Minimum 1024 System Clock Periods System Clock T0014-01 Figure 20. Internal Power-On Reset Timing Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 13 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com t(RST) = 40 ns (min) RSTB Pulse Duration RSTB-Pin t(RST) Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock T0015-01 Figure 21. RSTB-Pin Reset Timing SERIAL AUDIO DATA INTERFACE The PCM1800 interfaces with the audio system through BCK (pin 14), LRCK (pin 13), FSYNC (pin 12), and DOUT (pin 15). INTERFACE MODE The PCM1800 supports master and slave modes as interface modes, which are selected by MODE1 (pin 11) and MODE0 (pin 10), as shown in Table 2. When in master mode, the PCM1800 provides the timing for serial audio data communications between the PCM1800 and the digital audio processor or external circuit. When in slave mode, the PCM1800 receives the timing for data transfer from an external controller. Table 2. Interface Mode MODE1 MODE0 0 0 Slave mode (256/384/512 fS) INTERFACE MODE 0 1 Master mode (512 fS) 1 0 Master mode (384 fS) 1 1 Master mode (256 fS) MASTER MODE In master mode, BCK, LRCK, and FSYNC are output pins and are controlled by timing generated in the clock circuitry of the PCM1800. FSYNC is used to designate the valid data from the PCM1800. The rising edge of FSYNC indicates the starting point of the converted audio data, and the following edge of this signal indicates the ending point of data. The frequency of this signal is fixed at 2× LRCK, and the duty-cycle ratio depends on the data bit length. The frequency of BCK is fixed at 64× LRCK. SLAVE MODE In slave mode, BCK, LRCK, and FSYNC are input pins. The PCM1800 accepts 64-BCK/LRCK, 48-BCK/LRCK (only for a 384-fS system clock) or 32-BCK/LRCK format (only for 16-bit, right-justified format). FSYNC is used to enable the BCK signal, and the PCM1800 can shift out the converted data when FSYNC is HIGH. DATA FORMAT The PCM1800 supports four audio data formats in both master and slave modes. These data formats are selected by FMT1 (pin 9) and FMT0 (pin 8), as shown in Table 3. Figure 22 and Figure 23 illustrate the data formats in slave mode and master mode, respectively. 14 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 Table 3. Data Format FORMAT NO. (1) FMT1 (1) FMT0 (1) DATA FORMAT 0 0 0 20-bit, left-justified 1 0 1 20-bit, I2S 2 1 0 16-bit, right-justified 3 1 1 20-bit, right-justified FMT1 and FMT0 must be stable when RSTB changes from LOW to HIGH. FORMAT 0: FMT[1:0] = 00 20-Bit, MSB-First, Left-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 18 19 20 MSB 1 LSB 2 3 1 18 19 20 MSB LSB FORMAT 1: FMT[1:0] = 01 20-Bit, MSB-First, I2S FSYNC LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 18 19 20 1 LSB MSB 2 3 18 19 20 LSB MSB FORMAT 2: FMT[1:0] = 10 16-Bit, MSB-First, Right-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 20 1 2 3 MSB 18 19 20 LSB 1 2 3 18 19 20 MSB LSB T0016-01 Figure 22. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK Are Inputs) Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 15 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com FORMAT 0: FMT[1:0] = 00 20-Bit, MSB-First, Left-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 18 19 20 MSB 1 LSB 2 3 1 18 19 20 MSB LSB FORMAT 1: FMT[1:0] = 01 20-Bit, MSB-First, I2S FSYNC LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 18 19 20 1 LSB MSB 2 3 18 19 20 LSB MSB FORMAT 2: FMT[1:0] = 10 16-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified FSYNC Left-Channel LRCK Right-Channel BCK DOUT 20 1 2 3 MSB 18 19 20 LSB 1 2 3 18 19 20 MSB LSB T0016-02 Figure 23. Audio Data Format (Master Mode: FSYNC, LRCK, and BCK Are Outputs) 16 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 INTERFACE TIMING Figure 24 and Figure 25 illustrate the interface timing in slave mode and master mode, respectively. 1.4 V FSYNC t(FSSU) t(FSHD) t(LRCP) 1.4 V LRCK t(BCKL) t(BCKH) t(LRSU) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0017-01 SYMBOL MIN BCK period DESCRIPTION t(BCKP) 300 TYP MAX UNITS ns BCK pulse duration, HIGH t(BCKH) 120 ns BCK pulse duration, LOW t(BCKL) 120 ns LRCK setup time to BCK rising edge t(LRSU) 80 ns LRCK hold time to BCK rising edge t(LRHD) 40 ns LRCK period t(LRCP) 20 µs FSYNC setup time to BCK rising edge t(FSSU) 40 ns FSYNC hold time to BCK rising edge t(FSHD) 40 ns Delay time, BCK falling edge to DOUT valid t(CKDO) –20 40 ns Delay time, LRCK edge to DOUT valid t(LRDO) –20 40 ns Rising time of all signals t(RISE) 20 ns Falling time of all signals t(FALL) 20 ns NOTE: Timing measurement reference level is (VIH + VIL)/2. Rising and falling time is measured from 10% to 90% of the I/O signal swing. Load capacitance of the DOUT signal is 20 pF. Figure 24. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Are Inputs) Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 17 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com t(FSYP) 0.5 VDD FSYNC t(CKFS) t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0018-01 DESCRIPTION SYMBOL MIN TYP MAX UNITS BCK period t(BCKP) 300 1/64 fS 4800 ns BCK pulse duration, HIGH t(BCKH) 150 2400 ns BCK pulse duration, LOW t(BCKL) 150 2400 ns Delay time, BCK falling edge to LRCK valid t(CKLR) –20 40 ns LRCK period t(LRCP) 20 320 µs Delay time, BCK falling edge to FSYNC valid t(CKFS) –20 FSYNC period t(FSYP) 10 Delay time, BCK falling edge to DOUT valid t(CKDO) Delay time, LRCK edge to DOUT valid t(LRDO) Rising time of all signals Falling time of all signals 1/fS 40 ns 160 µs –20 40 ns –20 40 ns t(RISE) 20 ns t(FALL) 20 ns 1/2 fS NOTE: Timing measurement reference level is (VIH + VIL)/2. Rising and falling time is measured from 10% to 90% of the I/O signal swing. Load capacitance of the DOUT signal is 20 pF. Figure 25. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK Are Outputs) SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1800 operates with LRCK synchronized to the system clock (SYSCLK). The PCM1800 does not require a specific phase relationship between LRCK and SYSCLK, but does require the synchronization of LRCK and SYSCLK. If the relationship between LRCK and SYSCLK changes more than 6 bit clocks (BCK) during one sample period due to LRCK or SYSCLK jitter, internal operation of the ADC halts within 1/fS and the digital output is forced into the BPZ mode until resynchronization between LRCK and SYSCLK is completed. In case of changes less than 5 bit clocks (BCK), resynchronization does not occur, and the previously described digital output control and discontinuity does not occur. ADC DATA OUTPUT AT RESET Figure 26 and Figure 27 illustrate the ADC digital output when the reset operation is done and when synchronization is lost, respectively. During undefined data, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity in the data on the digital output, and may generate some noise in the audio signal. 18 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 Power ON RSTB ON Reset Release Reset Internal Reset Ready/Operation 18436/fS DOUT(1) Normal Data(2) Zero Data T0019-01 (1) In the master mode, FSYNC, BCK, and LRCK are outputs similar to DOUT. (2) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially. Figure 26. ADC Digital Output for Power-On Reset and RSTB Control Synchronization Lost State of Synchronization Synchronous Resynchronization Asynchronous Synchronous 1/fS DOUT(1) Normal Data Undefined Data 32/fS Zero Data Normal Data(2) T0020-01 (1) Applies only for slave mode—the loss of synchronization never occurs in master mode. (2) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially. Figure 27. ADC Digital Output During Loss of Synchronization Resynchronization HPF BYPASS CONTROL The built-in function for dc component rejection can be bypassed by BYPAS (pin 7) control (see Table 4). In bypass mode, the dc component of the input analog signal, the internal dc offset, etc., are also converted and output in the digital output data. Table 4. HPF Bypass Control BYPAS HIGH-PASS FILTER (HPF) MODE Low Normal (dc cut) mode High Bypass (through) mode Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 19 PCM1800 SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com APPLICATION INFORMATION BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD PINS The digital and analog power supply lines to the PCM1800 should be bypassed to the corresponding ground pins with both 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. Although the PCM1800 has two power lines to maximize the potential of dynamic performance, using one common power supply is recommended to avoid unexpected power supply problems, such as latch-up or power supply sequence. AGND, DGND PINS To maximize the dynamic performance of the PCM1800, the analog and digital grounds are not internally connected. These points should have low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the part to reduce potential noise problems. VIN PINS A 1-µF tantalum capacitor is recommended as an ac-coupling capacitor, which establishes a 5.3-Hz cutoff frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a series resistor to the VIN pins. VREF INPUTS A 4.7-µF tantalum capacitor is recommended between VREF1, VREF2, and REFCOM to ensure low source impedance for the ADC references. These capacitors should be located as close as possible to the VREF1 and VREF2 pins to reduce dynamic errors on the ADC references. The REFCOM pin also should be connected directly to AGND under the part. CINP and CINN INPUTS A 470-pF to 1000-pF film capacitor is recommended between CINPL and CINNL, CINPR and CINNR to create an antialiasing filter which has a 170-kHz to 80-kHz cutoff frequency. These capacitors should be located as close as possible to the CINP and CINN pins to avoid introducing unexpected noise or dynamic errors into the delta-sigma modulator. Four 10-pF–47-pF capacitors between CINXX and AGND may improve dynamic performance under disadvantageous actual conditions. DOUT, BCK, LRCK, FSYNC PINS In master mode, the DOUT, BCK, LRCK and FSYNC pins have a large load-drive capability, but locating the buffer near the PCM1800 and minimizing the load capacitance is recommended in order to minimize the digital-analog crosstalk and to maximize dynamic performance potential. SYSTEM CLOCK The quality of the system clock can influence dynamic performance in the PCM1800. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and can degrade long-term reliability if the maximum power dissipation limit is exceeded. RSTB CONTROL If the capacitance between VREF1 and VREF2 exceeds 4.7 µF, an external reset control with a delay-time circuit must be used. 20 Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 PCM1800 www.ti.com ............................................................................................................................................... SBAS071B – OCTOBER 2000 – REVISED AUGUST 2008 TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 28 is a typical circuit connection diagram for which the cutoff frequency of the input HPF is about 5 Hz. Signal Gnd Line In Left-Channel 1.0 µF(2) + 1 4.7 µF + 2 3 4.7 µF Line In Right-Channel 1.0 µF(2) + Pin Program or Control + 24 Analog Front-End 23 Analog Front-End 22 Ref 4 21 5 20 RSTB 6 BYPAS 7 FMT0 8 FMT1 9 MODE0 10 MODE1 11 0.1 µF/10 µF(1) + Reset Delta-Sigma CEXT 470 pF CEXT 470 pF 19 18 Decimation Filter +5 V + 0.1 µF/10 µF(1) 17 Clock Digital Audio Interface 12 GND 16 SYSCLK 15 DOUT 14 BCK 13 LRCK Audio Data Processor SYNC S0012-01 (1) Bypass capacitor = 0.1-µF ceramic and 10-µF tantalum, depending on layout and power supply. (2) A 1-µF capacitor gives a 5.3-Hz cutoff frequency for the input HPF in normal operation and requires a power-on settling period with a 30-ms time constant during power-on initialization. Figure 28. Typical Circuit Connection Submit Documentation Feedback Copyright © 2000–2008, Texas Instruments Incorporated Product Folder Link(s): PCM1800 21 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PCM1800E ACTIVE SSOP DB 24 58 RoHS & Green NIPDAU Level-1-260C-UNLIM PCM1800E Samples PCM1800E/2K ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM PCM1800E Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of