PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
Check for Samples: PCM1808-Q1
FEATURES
1
•
•
•
•
23
•
•
•
•
•
•
•
Qualified for Automotive Applications
24-Bit Delta-Sigma Stereo A/D Converter
Single-Ended Voltage Input: 3 Vp-p
High Performance:
– THD + N: –93 dB (Typical)
– SNR: 99 dB (Typical)
– Dynamic Range: 99 dB (Typical)
Oversampling Decimation Filter:
– Oversampling Frequency: ×64
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
Flexible PCM Audio Interface
– Master/Slave Mode Selectable
– Data Formats: 24-Bit I2S, 24-Bit LeftJustified
Power Down and Reset by Halting System
Clock
Analog Antialias LPF Included
Sampling Rate: 8 kHz–96 kHz
System Clock: 256 fS, 384 fS, 512 fS
Dual Power Supplies:
– 5-V for Analog
– 3.3-V for Digital
•
Package: 14-Pin TSSOP
DESCRIPTION
The PCM1808-Q1 is high-performance, low-cost,
single-chip, stereo analog-to-digital converter with
single-ended analog voltage input. The PCM1808-Q1
uses a delta-sigma modulator with 64-times
oversampling and includes a digital decimation filter
and high-pass filter that removes the dc component
of the input signal. For various applications, the
PCM1808-Q1 supports master and slave mode and
two data formats in serial audio interface.
The PCM1808-Q1 supports the power-down and
reset function by means of halting the system clock.
The PCM1808-Q1 is suitable for wide variety of costsensitive consumer applications where good
performance and operation with a 5-V analog supply
and 3.3-V digital supply is required. The PCM1808Q1 is fabricated using a highly advanced CMOS
process and is available in a small, 14-pin TSSOP
package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
PCM1808-Q1
Analog supply voltage, VCC
–0.3 V to 6.5 V
Digital supply voltage, VDD
–0.3 V to 4 V
Ground voltage differences, AGND, DGND
±0.1 V
Digital input voltage, LRCK, BCK, DOUT
–0.3 V to (VDD + 0.3 V) < 4 V
Digital input voltage, SCKI, MD0, MD1, FMT
–0.3 V to 6.5 V
Analog input voltage, VINL, VINR, VREF
–0.3 V to (VCC + 0.3 V) < 6.5 V
Input current (any pins except supplies)
±10 mA
Ambient temperature under bias, TA
–40°C to 125°C
Storage temperature, Tstg
–55°C to 150°C
Junction temperature, TJ
150°C
Lead temperature (soldering)
260°C, 5 s
Package temperature (reflow, peak)
(1)
260°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Analog supply voltage, VCC
4.5
5
5.5
V
Digital supply voltage, VDD
2.7
3.3
3.6
V
3
3.23
Vp-p
2.048
49.152
MHz
8
96
kHz
20
pF
–40
125
°C
Analog input voltage, full scale (–0 dB)
VCC = 5 V
2.93
Digital input logic family
Digital input clock frequency, system clock
Digital input clock frequency, sampling clock
TTL compatible
Digital output load capacitance
Operating free-air temperature, TA
2
UNIT
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
24
UNIT
Bits
DATA FORMAT
I2S, left-justified
Audio data interface format
Audio data bit length
24
Audio data format
fS
Bits
MSB-first, 2s complement
Sampling frequency
System clock frequency,
–40°C ≤ TA ≤ 125°C (1)
8
48
96
256 fS
2.048
12.288
24.576
384 fS
3.072
18.432
36.864
512 fS
4.096
24.576
49.152
kHz
MHz
INPUT LOGIC
VIH
(2)
VIL
(2)
VIH
(4) (5)
VIL
(4) (5)
IIH
(4)
IIL
(4)
IIH
(2) (5)
IIL
(2) (5)
Input logic level,
–40°C ≤ TA ≤ 125°C (3)
2
VDD
0
0.8
2
5.5
0
0.8
VIN = VDD
±10
VIN = 0 V
Input logic current
VDC
±10
VIN = VDD
at 25°C
65
100
–40°C ≤ TA ≤ 125°C
65
150
VIN = 0 V
μA
±10
OUTPUT LOGIC
VOH
(6)
VOL
(6)
Output logic level
(3)
IOUT = –4 mA
at 25°C
2.8
–40°C ≤ TA ≤ 125°C
2.7
VDC
IOUT = 4 mA, –40°C ≤ TA ≤ 125°C
0.5
DC ACCURACY, –40°C ≤ TA ≤ 125°C
Gain mismatch, channel-tochannel
±1
±3
% of
FSR
Gain error
±3
±6
% of
FSR
at 25°C
–93
–87
–40°C ≤ TA ≤ 125°C
–93
–85
DYNAMIC PERFORMANCE
(7)
VIN = –0.5 dB, fS = 48 kHz
THD + N
Total harmonic distortion +
noise
(8)
VIN = –0.5 dB, fS = 96 kHz
–87
VIN = –60 dB, fS = 48 kHz
VIN = –60 dB, fS = 96 kHz
Dynamic range
S/N
Signal-to-noise ratio
(8)
–39
at 25°C
95
–40°C ≤ TA ≤ 125°C
93
(8)
fS = 48 kHz, A-weighted
fS = 96 kHz, A-weighted
(1)
(2)
(3)
(4)
(5)
(6)
(7)
–37
(8)
fS = 48 kHz, A-weighted
fS = 96 kHz, A-weighted
dB
(8)
99
99
dB
101
at 25°C
95
–40°C ≤ TA ≤ 125°C
93
99
99
dB
101
384 fs where fs = 96kHz, and 512 where fs = 48 kHz and 96kHz are functionally tested. Other options are specified by design.
Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode)
Specified by design
Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)
Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)
Pins 7–9: LRCK, BCK (in master mode), DOUT
Analog performance specifications are tested using a System Two™ audio measurement system by Audio Precision™ with 400-Hz HPF
and 20-kHz LPF in RMS mode.
fS = 96 kHz, system clock = 256 fS.
Copyright © 2011–2012, Texas Instruments Incorporated
3
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
Channel separation
fS = 48 kHz
fS = 96 kHz
MIN
TYP
at 25°C
93
97
–40°C ≤ TA ≤ 125°C
91
97
(8)
MAX
UNIT
dB
91
ANALOG INPUT
Input voltage,
–40°C ≤ TA ≤ 125°C
Center voltage input range,
–40°C ≤ TA ≤ 125°C
0.58 VCC
0.6 VCC
0.65 VCC
Vp-p
0.2 VCC
0.5 VCC
0.8 VCC
V
Input impedance
Antialiasing filter frequency
response
–3 dB
DIGITAL FILTER PERFORMANCE, –40°C ≤ TA ≤ 125°C
60
kΩ
1.3
MHz
(3)
Pass band
0.454 fS
Stop band
0.583 fS
Hz
Pass-band ripple
±0.05
Stop-band attenuation
–65
Delay time
Hz
dB
dB
17.4/fS
HPF frequency response
0.019
fS/1000
–3 dB
POWER SUPPLY REQUIREMENTS
VCC
VDD
Voltage range,
–40°C ≤ TA ≤ 125°C
fS = 48 kHz, 96 kHz, –40°C ≤ TA ≤ 125°C
ICC
Powered down
Supply current
(9)
fS = 96 kHz
5
5.5
2.7
3.3
3.6
8.6
11
(10)
(11)
fS = 48 kHz
IDD
4.5
Powered down
at 25°C
5.9
8
–40°C ≤ TA ≤ 125°C
5.9
10
10.2
(11)
Power dissipation
(9)
fS = 96 kHz
62
(10)
Powered down
μA
81
77
(11)
mA
mA
150
fS = 48 kHz
mA
μA
1
(10)
VDC
mW
μW
500
TEMPERATURE RANGE
TA
Operation temperature
θJA
Thermal resistance
–40
125
170
°C
°C/W
(9) Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9)
(10) fS = 96 kHz, system clock = 256 fS.
(11) Power-down and reset functions enabled by halting SCKI, BCK, LRCK.
4
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
PIN ASSIGNMENTS
PW PACKAGE
(TOP VIEW)
VREF
AGND
VCC
VDD
DGND
SCKI
LRCK
1
2
3
4
5
6
7
VINR
VINL
FMT
MD1
MD0
DOUT
BCK
14
13
12
11
10
9
8
P0032-02
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
PIN
AGND
2
–
BCK
8
I/O
DGND
5
–
Digital GND
DOUT
9
O
Audio data digital output
FMT
12
I
Audio interface format select
LRCK
7
I/O
MD0
10
I
Audio interface mode select 0
(2)
MD1
11
I
Audio interface mode select 1
(2)
SCKI
6
I
System clock input; 256 fS, 384 fS or 512 fS
VCC
3
–
Analog power supply, 5-V
VDD
4
–
Digital power supply, 3.3-V
VINL
13
I
Analog input, L-channel
VINR
14
I
Analog input, R-channel
VREF
1
–
Reference voltage decoupling (= 0.5 VCC)
(1)
(2)
(3)
Analog GND
Audio data bit clock input/output
(1)
(2)
Audio data latch enable input/output
(1)
(3)
Schmitt-trigger input with internal pulldown (50-kΩ, typical)
Schmitt-trigger input with internal pulldown (50-kΩ, typical), 5-V tolerant
Schmitt-trigger input, 5-V tolerant
Copyright © 2011–2012, Texas Instruments Incorporated
5
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
Functional Block Diagram
Antialias
LPF
VINL
VREF
Delta-Sigma
Modulator
BCK
×1/64
Decimation
Filter
with
High-Pass Filter
Reference
Antialias
LPF
VINR
DOUT
FMT
Mode/
Format
Control
MD1
Delta-Sigma
Modulator
MD0
Clock and Timing Control
Power Supply
VCC
LRCK
Serial
Interface
AGND DGND
SCKI
VDD
B0004-10
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
DECIMATION FILTER FREQUENCY RESPONSE
OVERALL CHARACTERISTICS
STOP-BAND ATTENUATION CHARACTERISTICS
50
0
−10
0
−20
Amplitude − dB
Amplitude − dB
−30
−50
−100
−40
−50
−60
−70
−150
−80
−90
−200
0
8
16
24
Normalized Frequency [× fS]
Figure 1.
6
32
G001
−100
0.00
0.25
0.50
Frequency [× fS]
0.75
1.00
G002
Figure 2.
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
DECIMATION FILTER FREQUENCY RESPONSE (Continued)
PASS-BAND RIPPLE CHARACTERISTICS
TRANSITION BAND CHARACTERISTICS
0.2
0
−1
−2
−3
−0.2
Amplitude − dB
Amplitude − dB
0.0
−0.4
−0.6
−4
–4.13 dB at 0.5 fS
−5
−6
−7
−8
−0.8
−9
−1.0
0.0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency [× fS]
−10
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
0.6
Normalized Frequency [× fS]
G003
Figure 3.
G004
Figure 4.
HIGH-PASS FILTER FREQUENCY RESPONSE
HPF STOP-BAND CHARACTERISTICS
HPF PASS-BAND CHARACTERISTICS
0.2
0
−10
0.0
−20
Amplitude − dB
Amplitude − dB
−30
−40
−50
−60
−70
−80
−0.2
−0.4
−0.6
−0.8
−90
−100
0.0
−1.0
0.1
0.2
0.3
Normalized Frequency [× fS/1000]
Figure 5.
Copyright © 2011–2012, Texas Instruments Incorporated
0.4
G005
0
1
2
3
Normalized Frequency [× fS/1000]
4
G006
Figure 6.
7
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
DYNAMIC RANGE AND SNR
vs
TEMPERATURE
−87
105
−88
104
−89
103
Dynamic Range and SNR − dB
THD + N − Total Harmonic Distortion + Noise − dB
THD + N
vs
TEMPERATURE
−90
−91
−92
−93
−94
−95
−96
−97
−50
−25
0
25
50
75
100
99
SNR
97
−25
0
25
50
75
TA − Free-Air Temperature − °C
G007
Figure 7.
Figure 8.
THD + N
vs
SUPPLY VOLTAGE
DYNAMIC RANGE AND SNR
vs
SUPPLY VOLTAGE
−87
105
−88
104
−89
103
−90
−91
−92
−93
−94
−95
100
G008
102
101
100
Dynamic Range
99
SNR
98
97
96
−96
−97
4.25
Dynamic Range
98
95
−50
100
Dynamic Range and SNR − dB
THD + N − Total Harmonic Distortion + Noise − dB
101
96
TA − Free-Air Temperature − °C
4.50
4.75
5.00
5.25
VCC − Supply Voltage − V
Figure 9.
8
102
5.50
5.75
G009
95
4.25
4.50
4.75
5.00
5.25
VCC − Supply Voltage − V
5.50
5.75
G010
Figure 10.
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
TYPICAL PERFORMANCE CURVES (Continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
DYNAMIC RANGE AND SNR
vs
fSAMPLE CONDITION
−87
105
−88
104
−89
103
Dynamic Range and SNR − dB
THD + N − Total Harmonic Distortion + Noise − dB
THD + N
vs
fSAMPLE CONDITION
−90
−91
−92
−93
−94
−95
Dynamic Range
SNR
102
101
100
99
98
97
(1) System
(1) System
Clock = 384 fS
(2) System Clock = 512 f
S
(3) System Clock = 256 f
S
−96
−97
44.1(1)
48(2)
Clock = 384 fS
System Clock = 512 fS
(3) System Clock = 256 f
S
(2)
96
95
96(3)
44.1(1)
fSAMPLE Condition − kHz
48(2)
96(3)
fSAMPLE Condition − kHz
G011
Figure 11.
G012
Figure 12.
OUTPUT SPECTRUM
OUTPUT SPECTRUM (–0.5 dB, N = 8192)
OUTPUT SPECTRUM (–60 dB, N = 8192)
0
0
Input Level = −60 dB
Data Points = 8192
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
Input Level = −0.5 dB
Data Points = 8192
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
0
5
10
15
20
f − Frequency − kHz
0
5
10
G013
Figure 13.
Copyright © 2011–2012, Texas Instruments Incorporated
15
20
f − Frequency − kHz
G014
Figure 14.
9
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
TYPICAL PERFORMANCE CURVES (Continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
OUTPUT SPECTRUM (Continued)
THD + N − Total Harmonic Distortion + Noise − dB
THD + N
vs
SIGNAL LEVEL
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Signal Level − dB
G015
Figure 15.
SUPPLY CURRENT
SUPPLY CURRENT
vs
fSAMPLE CONDITION
15
ICC and IDD − Supply Current − mA
ICC
IDD
10
5
(1) System
Clock = 384 fS
System Clock = 512 fS
(3) System Clock = 256 f
S
(2)
0
44.1(1)
48(2)
96(3)
fSAMPLE Condition − kHz
G016
Figure 16.
10
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
SYSTEM CLOCK
The PCM1808-Q1 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency.
The system clock must be supplied on SCKI (pin 6).
The PCM1808-Q1 has a system clock detection circuit which automatically senses if the system clock is
operating at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, the system clock frequency must be
controlled through the serial control port, which uses MD1 (pin 111) and MD0 (pin 10). The system clock is
divided down automatically to generate frequencies of 128 fS and 64 fS, which are used to operate the digital filter
and the delta-sigma modulator, respectively.
Table 1 shows some typical relationships between sampling frequency and system clock frequency, and
Figure 17 shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
256 fS
384 fS
512 fS
4.096
8
2.048
3.072
16
4.096
6.144
8.192
32
8.192
12.288
16.384
44.1
11.2896
16.9344
22.5792
48
12.288
18.432
24.576
64
16.384
24.576
32.768
88.2
22.5792
33.8688
45.1584
96
24.576
36.864
49.152
tw(SCKH)
tw(SCKL)
SCKI
2V
SCKI
0.8 V
T0005B07
SYMBOL
PARAMETER
MIN
tw(SCKH)
System clock pulse duration, HIGH
8
tw(SCKL)
System clock pulse duration, LOW
8
System clock duty cycle
40%
MAX
UNIT
ns
ns
60%
Figure 17. System Clock Timing
FADE-IN AND FADE-OUT FUNCTIONS
The PCM1808-Q1 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions
come into operation in some cases as described in several following sections. The level changes from 0 dB to
mute or mute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection.
Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog input
frequency (fin). It takes 48/fin until processing is completed. If there is no zero cross during 8192/fS, DOUT is
faded in or out by force during 48/fS (TIME OUT). Figure 18 illustrates the fade-in and fade-out operation
processing.
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PCM1808-Q1
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Fade-Out Start
Fade-In Complete
Fade-In Start
DOUT
(Contents)
Fade-Out Complete
BPZ
48/fin or 48/fS
48/fin or 48/fS
T0080-01
Figure 18. Fade-In and Fade-Out Operations
POWER ON
The PCM1808-Q1 has an internal power-on-reset circuit, and initialization (reset) is performed automatically
when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock
counts after VDD > 2.2 V (typical), the PCM1808-Q1 stays in the reset state and the digital output is forced to
zero. The digital output is valid after the reset state is released and the time of 8960/fS has elapsed. Because the
fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the data corresponding to the analog
input signal is obtained. Figure 19 illustrates the power-on timing and the digital output.
VDD
2.6 V
2.2 V
1.8 V
Reset
Reset Release
Internal
Reset
Operation
1024 System Clocks
8960/fS
System
Clock
DOUT
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
DOUT
BPZ
(Contents)
48/fin or 48/fS
T0014-09
Figure 19. Power-On Timing
12
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
CLOCK-HALT POWER-DOWN AND RESET FUNCTION
The PCM1808-Q1 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both
master and slave modes. The function is available anytime after power on. Reset and power down are performed
automatically 4 μs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808-Q1 stays
in the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the
reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024
SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS
until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset
timing.
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI
within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI,
SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the
typical circuit connection diagram, Figure 26.
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor
the audio interface clocks BCK and LRCK (sampling rate fS) are changed on the fly.
SCKI Halt
SCKI Resume
Fixed to Low or High
SCKI
t(CKR)
Reset: t(RST)
Clock-Halt Reset
Internal
Reset
DOUT
Reset Release: t(REL)
Operation
Operation
Normal Data
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
DOUT
BPZ
(Contents)
Normal Data
48/fin or 48/fS
T0081-01
SYMBOL
PARAMETER
MIN
MAX
UNIT
μs
t(CKR)
Delay time from SCKI halt to internal reset
4
t(RST)
Delay time from SCKI resume to reset release
1024 SCKI
μs
t(REL)
Delay time from reset release to DOUT output
8960/fS
μs
Figure 20. Clock-Halt Power-Down and Reset Timing
Copyright © 2011–2012, Texas Instruments Incorporated
13
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
SERIAL AUDIO DATA INTERFACE
The PCM1808-Q1 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9).
INTERFACE MODE
The PCM1808-Q1 supports master mode and slave mode as interface modes, which are selected by MD1 (pin
11) and MD0 (pin 10), as shown in Table 2. MD1 and MD0 must be set prior to power on.
In master mode, the PCM1808-Q1 provides the timing of serial audio data communications between the
PCM1808-Q1 and the digital audio processor or external circuit. While in slave mode, the PCM1808-Q1 receives
the timing for data transfer from an external controller.
Table 2. Interface Modes
MD1 (Pin 11)
MD0 (Pin 10)
Low
Low
Slave mode (256 fS, 384 fS, 512 fS autodetection)
INTERFACE MODE
Low
High
Master mode (512 fS)
High
Low
Master mode (384 fS)
High
High
Master mode (256 fS)
Master mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated
in the clock circuit of the PCM1808-Q1. The frequency of BCK is fixed at 64 BCK/frame.
Slave mode
In slave mode, BCK and LRCK work as input pins. The PCM1808-Q1 accepts 64-BCK/frame or 48-BCK/frame
format (only for a 384-fS system clock), not 32-BCK/frame format.
DATA FORMAT
The PCM1808-Q1 supports two audio data formats in both master and slave modes. The data formats are
selected by FMT (pin 12), as shown in Table 3. Figure 21 illustrates the data formats in slave mode and master
mode.
Table 3. Data Format
FORMAT NO.
14
FMT (Pin 12)
FORMAT
2
0
Low
I S, 24-bit
1
High
Left-justified, 24-bit
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
FORMAT 0: FMT = LOW
24-Bit, MSB-First, I2S
Left-Channel
LRCK
Right-Channel
BCK
DOUT
1
2
3
22 23 24
MSB
1
LSB
2
3
22 23 24
MSB
LSB
FORMAT 1: FMT = HIGH
24-Bit, MSB-First, Left-Justified
Left-Channel
LRCK
Right-Channel
BCK
DOUT
1
2
3
MSB
22 23 24
LSB
1
2
MSB
3
22 23 24
1
LSB
T0016-17
Figure 21. Audio Data Format (LRCK and BCK Work as Inputs in Slave Mode
and as Outputs in Master Mode)
Copyright © 2011–2012, Texas Instruments Incorporated
15
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
INTERFACE TIMING
Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively.
t(LRCP)
1.4 V
LRCK
t(BCKL)
t(BCKH)
t(LRSU)
t(LRHD)
1.4 V
BCK
t(BCKP)
t(CKDO)
t(LRDO)
0.5 VDD
DOUT
T0017-02
SYMBOL
PARAMETER
t(BCKP)
BCK period
t(BCKH)
t(BCKL)
t(LRSU)
MIN
TYP
MAX
UNIT
1/(64 fS)
ns
BCK pulse duration, HIGH
1.5 × t(SCKI)
ns
BCK pulse duration, LOW
1.5 × t(SCKI)
ns
LRCK setup time to BCK rising edge
50
ns
t(LRHD)
LRCK hold time to BCK rising edge
10
ns
t(LRCP)
LRCK period
10
t(CKDO)
Delay time, BCK falling edge to DOUT valid
–10
40
ns
t(LRDO)
Delay time, LRCK edge to DOUT valid
–10
40
ns
tr
Rise time of all signals
20
ns
tf
Fall time of all signals
20
ns
μs
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to
90% of the input/output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period.
Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)
16
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
t(LRCP)
0.5 VDD
LRCK
t(BCKL)
t(BCKH)
t(CKLR)
0.5 VDD
BCK
t(BCKP)
t(CKDO)
t(LRDO)
0.5 VDD
DOUT
T0018-02
MIN
TYP
MAX
UNIT
t(BCKP)
SYMBOL
BCK period
PARAMETER
150
1/(64 fS)
2000
ns
t(BCKH)
BCK pulse duration, HIGH
65
1200
ns
t(BCKL)
BCK pulse duration, LOW
65
1200
ns
t(CKLR)
Delay time, BCK falling edge to LRCK valid
–10
20
ns
t(LRCP)
LRCK period
10
125
μs
t(CKDO)
Delay time, BCK falling edge to DOUT valid
–10
20
ns
t(LRDO)
Delay time, LRCK edge to DOUT valid
–10
20
ns
tr
Rise time of all signals
20
ns
tf
Fall time of all signals
20
ns
1/fS
NOTE: Timing measurement reference level is 0.5 VDD. Rise and fall times are from 10% to 90% of the input/output signal
swing. Load capacitance of all signals is 20 pF.
Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)
1.4 V
SCKI
t(SCKBCK)
t(SCKBCK)
0.5 VDD
BCK
T0074-01
SYMBOL
t(SCKBCK)
PARAMETER
Delay time, SCKI rising edge to BCK edge
MIN
5
TYP
MAX
UNIT
30
ns
NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This
timing is applied when SCKI frequency is less than 25 MHz.
Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output)
Copyright © 2011–2012, Texas Instruments Incorporated
17
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
In slave mode, the PCM1808-Q1 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6).
The PCM1808-Q1 does not require a specific phase relationship between LRCK and SCKI, but does require the
synchronization of LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48
BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS
and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is
established.
In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization
does not occur and the previously described digital output control and discontinuity do not occur.
Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1808-Q1 can generate some noise in the audio signal. Also, the transition of normal
data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the
audio signal. The digital output is valid after resynchronization completes and the time of 32/fS has elapsed.
Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding
to the analog input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the
operation stops and DOUT (pin 9) is forced to zero data immediately. The fade-in operation resumes from mute
after the time of 32/fS following resynchronization.
Resynchronization
Resynchronization
Synchronization Lost
State of
Synchronization
Synchronous
Asynchronous
1/fS
DOUT
Normal Data
Synchronization Lost
Asynchronous
Synchronous
Synchronous
32/fS
Undefined
Data
Zero Data
Normal Data
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
DOUT
BPZ
(Contents)
Fade-In Restart
Normal Data
32/fS
48/fin or 48/fS
48/fin or 48/fS
T0082-01
Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization
18
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION DIAGRAM
Figure 26 is a typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog
inputs, VINL and VINR. If the performance of these filters is not adequate for an application, appropriate external
antialiasing filters are needed. A passive RC filter (100 Ω and 0.01 μF to 1 kΩ and 1000 pF) generally is used.
PCM1808
C5(3)
C4(2)
4 µs (min)
5V
3.3 V
+
(2) +
1
X1(4)
VREF
VINR
14
2
AGND
VINL
13
3
VCC
FMT
12
4
VDD
MD1
11
5
DGND
MD0
10
6
SCKI
DOUT
9
7
LRCK
BCK
8
C3
Mask
PLL170x
(5)
+
+
C1(1)
+
C2(1)
R-ch IN
L-ch IN
High/Low
Pin
Setting
DSP
or
Audio
Processor
S0113-02
(1)
C1, C2: A 1-μF electrolytic capacitor gives 2.7 Hz (τ = 1 μF × 60 kΩ) cutoff frequency for the input HPF in normal
operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period.
(2)
C3, C4: Bypass capacitors, 0.1-μF ceramic and 10-μF electrolytic, depending on layout and power supply
(3)
C5: 0.1-μF ceramic and 10-μF electrolytic capacitors are recommended.
(4)
X1: X1 masks the system clock input when using the clock-halt reset function with external control.
(5)
Optional external antialiasing filter could be required, depending on the application.
Figure 26. Typical Circuit Connection Diagram
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD PINS
The digital and analog power supply lines to the PCM1808-Q1 should be bypassed to the corresponding ground
pins with both 0.1-μF ceramic and 10-μF electrolytic capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC.
AGND, DGND PINS
To maximize the dynamic performance of the PCM1808-Q1, the analog and digital grounds are not internally
connected. These grounds should have low impedance to avoid digital noise feedback into the analog ground.
They should be connected directly to each other under the PCM1808-Q1 package to reduce potential noise
problems.
VINL, VINR PINS
VINL and VINR are single-ended inputs. The antialias low-pass filters are integrated on these inputs to remove the
high-frequency noise outside the audio band. If the performance of these filters is not adequate for an
application, appropriate external antialiasing filters are required. A passive RC filter (100 Ω and 0.01 μF to 1 kΩ
and 1000 pF) is generally used.
Copyright © 2011–2012, Texas Instruments Incorporated
19
PCM1808-Q1
SLES265A – MARCH 2011 – REVISED AUGUST 2012
www.ti.com
VREF PIN
To ensure low source impedance of the ADC references, 0.1-μF ceramic and 10-μF electrolytic capacitors are
recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF
pin to reduce dynamic errors on the ADC references.
DOUT PIN
The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the
PCM1808-Q1 and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and
maximize the dynamic performance of the ADC.
SYSTEM CLOCK
The quality of the system clock can influence dynamic performance, as the PCM1808-Q1 operates based on a
system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK or LRCK transition in slave mode.
20
Copyright © 2011–2012, Texas Instruments Incorporated
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
REVISION HISTORY
Changes from Original (March, 2011) to Revision A
Page
•
ROC CHANGES: Added 2.93 min and 3.23 max to analog input voltage row .................................................................... 2
•
ELEC CHAR CHANGES: Added -40°C ≤ TA ≤ 125°C to the header for DC accuracy and the rows for system clock
frequency, input logic level, and output logic level ............................................................................................................... 3
•
Added test condition row to VIN = VDD (input logic current) at -40°C ≤ TA ≤ 125°C with typ value 65 and max value
150 ........................................................................................................................................................................................ 3
•
Added test condition row to IOUT = –4 mA (output logic level) at -40°C ≤ TA ≤ 125°C with a min value of 2.7; added
test condition of 25°C with min value of 2.8 ......................................................................................................................... 3
•
Added test condition of 25°C to VIN = –0.5 dB, fS = 48 kHz (THD + N) with max value of –87, and added row with
test condition of -40°C ≤ TA ≤ 125°C and max value –85 ..................................................................................................... 3
•
Added test condition 25°C and min value of 95; added test condition row for -40°C ≤ TA ≤ 125°C with min value of
93 to fS = 48 kHz, A-weighted row (dynamic range and signal-to-noise) ............................................................................. 3
•
Added test condition 25°C and min value of 93; added test condition row for -40°C ≤ TA ≤ 125°C with min value of
91 to fS = 48 kHz (channel separation) ................................................................................................................................. 4
•
Added min value 0.58 VCC and max value 0.65 VCC to input voltage; added 0.2 VCC min and 0.8 VCC max to center
voltage; changed center voltage Vref to center voltage input range .................................................................................... 4
•
Added -40°C ≤ TA ≤ 125°C to input voltage, center voltage, digital filter performance header, supply current, and
voltage range rows ............................................................................................................................................................... 4
•
Added test condition row with -40°C ≤ TA ≤ 125°C to fS = 48 kHz (supply current) with a typ value of 5.9 and a max
value of 10 ............................................................................................................................................................................ 4
Copyright © 2011–2012, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1808QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
P1808Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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