PTB48501AAZ

PTB48500A and PTB48502A are Not Recommended for New Designs PTB48500 PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 DUAL-OUTPUT, 48-V INPUT ISOLATED DC/DC CONVERTER for xDSL FEATURES DESCRIPTION • • • • • • • • • • • The PTB4850x power modules are a dual-output isolated DC/DC converter, designed to provide the logic supply voltages for AC-7 based xDSL applications. The PTB48500 is rated for 13 A of total output current, making it suitable for 32-channel xDSL applications. The PTB48501 and PTB48502 provide output current for powering up to 64 xDSL channels. The PTB48501 is rated for 16.5 A total output current, and the PTB48502, 21 A. The PTB48502 incorporates 10 W of additional capacity for powering peripheral circuitry. Any of these converters can be used for other applications with similar power requirements. • • Dual Outputs (Independently Regulated) Input Voltage Range: 36 V to 75 V Power-Up/Down Sequencing 1500 VDC Isolation Over-Current Protection Over-Temperature Shutdown Under-Voltage Lockout Fixed Frequency Operation Temp Range: –40°C to 85°C Industry Standard Outline Operates with PTB4851x for Complete AC7 Power Solution Powers up to 64 DSL Ports Safety Approvals: – UL/cUL 60950 – EN 60950 The modules operate from a standard telecom (–48 V) central office (CO) supply and include an on/off enable control, output current limit, over-temperature protection, input under-voltage lockout (UVLO). The PTB48500 and PTB48501 also incorporates a power-up reset (POR) output. The modules are designed to operate with one of the PTB4851x DC/DC converter modules. The combination of PTB4850x and PTB4851x converter provides the complete the power supply for an AC7 chipset. The EN Out and Sync Out pins provide compatible output signals for controlling both the power up sequence and switching frequency the PTB48510. The PTB4850x modules employ double-sided surface mount construction, and are an industry standard size. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated PTB48500 PTB48500A and PTB48502A are Not Recommended for New Designs PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 STAND-ALONE APPLICATION PTB4850x SyncOut +VI 1 +VI ENOut 2 4 (8)* POR VO1 −VI 5 −VI VO2 3 Enable 10 6 Vo 1 Vo 2 VO2Adj 9 COM L O A D L O A D 7, (8)* COM * Pin 8 is COM on PTB48502 ORDERING INFORMATION Base Part No. (PTB4850_xxx) Output Voltage (PTB4850x_xx) Package Options (PT4850xx_ _) Order Prefix Description Code Voltage Code Description PTB48500xxx 13 A A 3.3 V / 1.2 V AH Horiz. T/H (32-Ports) (ERH) Standard (2) PTB48501xxx 16.5 A (48/64-Ports) AS SMD, PTB48502xx 21 A (64-Ports + 10 W) AZ SMD, Pb-free (1) (2) Pkg Ref. (1) (ERJ) (ERJ) Reference the applicable package reference drawing for the dimensions and PC board layout. Standard option specifies 63/37, Sn/Pb pin solder material. Environmental and General Specifications (Unless otherwise stated, all voltages are with respect to –VI) VI TA VDC Over output load range 36 to 75 Isolation Voltage Input-output/input/case 1500 V Capacitance Input to output 1500 pF Resistance Input to output 10 mΩ Operating Temperature Range Over Vin Range –40 to 85 °C Over-Temperature Protection Treflow Solder Reflow Temperature Ts Storage Temperature Mechanical Shock Mechanical Vibration Mil-STD-883D Shutdown threshold 115 Hysterisis 10 Flammability °C 235 (1) °C –40 to 125 °C Per Mil-STD-883D, Method 2002.3 1 msec, 1/2 Sine, mounted 500 G Method 2007.2 Suffix H 20 20-2000 Hz Suffix C 5 Surface temperature of module body or pins Weight 2 UNIT Input Voltage Range OTP (1) VALUE G grams Meets UL 94V-O During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum. Submit Documentation Feedback PTB48500A and PTB48502A are Not Recommended for New Designs www.ti.com PTB48500 PTB48501 PTB48502 SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS (PTB48500A) (Unless otherwise stated, TA = 25°C, VI = 48 V, CI = 0 µF, CO = 0 µF, and IO = 50% Iomax) PARAMETER Po1, Po2 Output Power Po total Both outputs Io1, Io2 Output Current Io1 + Io2 Vo1 MIN Vo2 Temperature Variation TYP MAX Vo1 (3.3 V) 19.8 Vo2 (1.2 V) 8.4 28 Over VI range Vo1 (3.3 V) 0 6 (1) Vo2 (1.2 V) 0 7 (1) Total (both outputs) Output Voltage ∆Regtemp PTB48500A TEST CONDITIONS 0 Includes set point, line, load, –40°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 85°C, IO = IO min 13 3.2 3.3 3.4 1.16 1.2 1.24 Vo1 ±0.5 Vo2 ±0.8 UNIT W W A A V %VO ∆Regline Line Regulation Over VI range Vo1, Vo2 ±1 ±10 mV ∆Regload Load Regulation Over IO range Vo1, Vo2 ±3 ±12 mV IO min ≤ Io2≤ Iomax, Io1 = 1 A ∆Vo1 10 IO min ≤ Io1≤ Iomax, Io2 = 1 A ∆Vo2 10 ∆Regcross Cross Regulation η Efficiency Vr VO Ripple (pk-pk) ttr Transient Response ∆Vtr Io1, Io2 = Iomax 20 MHz bandwidth 82% Vo1 20 50 Vo2 20 50 1 A/µs load step, 50% to 100% Iomax ±2.0 Vo1, Vo2 over/undershoot Over Current Threshold VI = 36 V, reset followed by auto-recovery Vadj Output Voltage Adjust Range Vo2 only –10 fS Switching Frequency Over VI and IO ranges 500 VI off Under-Voltage Lockout On/Off Enable (pin 3) Io1 + Io2 13.5 VI decreasing 32 3.6 VIL Input Low Voltage –0.2 Input Low Current Standby Input Current CI Internal Input Capacitance Co1 Co2 External Output Capacitance MTBF Reliability (1) (2) (3) A 20 %Vo 600 kHz V Referenced to –VI (pin 5) Input High Voltage II standby 550 34 VIH IIL %VO 16 VI increasing mVpp µs 30 Iotrip VI on mV Pins 3 and 5 connected Per Telcordia SR-332 50% stress, TA = 40°C, ground benign 75 (2) 0.8 –1 mA 2 mA 2 µF 0 (3) 5000 0 (3) 5000 1.5 V µF 106 Hrs See Safe Operating Area curves or contact the factory for the appropriate derating. The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is diode protected and may be connected to +VI. The maximum open-circuit voltage is 7 V. If it is left open circuit the converter will operate when input power is applied. An output capacitor is not required. Submit Documentation Feedback 3 PTB48500 PTB48500A and PTB48502A are Not Recommended for New Designs PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS (PTB48501A) (Unless otherwise stated, TA = 25°C, VI = 48 V, CI = 0 µF, CO = 0 µF, and IO = 50% Iomax) PARAMETER Po1, Po2 Output Power Po total Both outputs Io1, Io2 Output Current Io1 + Io2 Vo1 Vo2 Temperature Variation TYP MAX Vo1 (3.3 V) 19.8 Vo2 (1.2 V) 12.6 32.4 Over VI range Vo1 (3.3 V) 0 6 (1) Vo2 (1.2 V) 0 10.5 (1) 0 Includes set point, line, load, –40°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 85°C, IO = IO min 16.5 3.2 3.3 3.4 1.16 1.2 1.24 Vo1 ±0.5 Vo2 ±0.8 UNIT W W A A V %VO ∆Regline Line Regulation Over VI range Vo1, Vo2 ±1 ±10 mV ∆Regload Load Regulation Over IO range Vo1, Vo2 ±3 ±12 mV IO min ≤ Io2≤ Iomax, Io1 = 1 A ∆Vo1 10 IO min ≤ Io1≤ Iomax, Io2 = 1 A ∆Vo2 10 ∆Regcross Cross Regulation η Efficiency Vr VO Ripple (pk-pk) ttr Transient Response ∆Vtr Io1, Io2 = Iomax 20 MHz bandwidth 20 50 Vo2 20 50 1 A/µs load step, 50% to 100% Iomax ±2.0 Vo1, Vo2 over/undershoot VI = 36 V, reset followed by auto-recovery Vadj Output Voltage Adjust Range Vo2 only –20 fS Switching Frequency Over VI and IO ranges 500 Under-Voltage Lockout On/Off Enable (pin 3) Io1 + Io2 VI decreasing 32 3.6 VIL Input Low Voltage –0.2 Input Low Current Standby Input Current CI Internal Input Capacitance Co1 Co2 External Output Capacitance MTBF Reliability (1) (2) (3) A 10 %Vo 600 kHz V Referenced to –VI (pin 5) Input High Voltage II standby 550 34 VIH IIL %VO 24 VI increasing mVpp µs 30 Over Current Threshold VI off mV 81% Vo1 Iotrip VI on 4 MIN Total (both outputs) Output Voltage ∆Regtemp PTB48501A TEST CONDITIONS Pins 3 and 5 connected Per Telcordia SR-332 50% stress, TA = 40°C, ground benign 75 (2) 0.8 –1 mA 2 mA 2 µF 0 (3) 5000 0 (3) 5000 1.5 V µF 106 Hrs See Safe Operating Area curves or contact the factory for the appropriate derating. The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is diode protected and may be connected to +VI. The maximum open-circuit voltage is 7 V. If it is left open circuit the converter will operate when input power is applied. An output capacitor is not required. Submit Documentation Feedback PTB48500A and PTB48502A are Not Recommended for New Designs www.ti.com PTB48500 PTB48501 PTB48502 SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS (PTB48502A) (Unless otherwise stated, TA = 25°C, VI = 48 V, CI = 0 µF, CO = 0 µF, and IO = 50% Iomax) PARAMETER Po1, Po2 Output Power Po total Both outputs Io1, Io2 Output Current Io1 + Io2 Vo1 ∆Regtemp MIN Temperature Variation TYP MAX Vo1 (3.3 V) 33 Vo2 (1.2 V) 15.6 45 Over VI range Vo1 (3.3 V) 0 10 (1) Vo2 (1.2 V) 0 13 (1) Total (both outputs) Output Voltage Vo2 PTB48502A TEST CONDITIONS 0 Includes set point, line, load, –40°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 85°C, IO = IO min 21 3.2 3.3 3.4 1.16 1.2 1.24 Vo1 ±0.5 Vo2 ±0.8 UNIT W W A A V %VO ∆Regline Line Regulation Over VI range Vo1, Vo2 ±1 ±10 mV ∆Regload Load Regulation Over IO range Vo1, Vo2 ±3 ±12 mV IO min ≤ Io2≤ Iomax, Io1 = 1 A ∆Vo1 10 IO min ≤ Io1≤ Iomax, Io2 = 1 A ∆Vo2 10 ∆Regcross Cross Regulation η Efficiency Vr VO Ripple (pk-pk) ttr Transient Response ∆Vtr Io1, Io2 = Iomax 20 MHz bandwidth 82% Vo1 20 50 Vo2 20 50 1 A/µs load step, 50% to 100% Iomax ±2.0 Vo1, Vo2 over/undershoot Over Current Threshold VI = 36 V, reset followed by auto-recovery Vadj Output Voltage Adjust Range Vo2 only –20 fS Switching Frequency Over VI and IO ranges 500 VI off Under-Voltage Lockout On/Off Enable (pin 3) Io1 + Io2 %VO 24 550 VI increasing 34 VI decreasing 32 A 10 %Vo 600 kHz V Referenced to –VI (pin 5) VIH Input High Voltage 3.6 75 (2) VIL Input Low Voltage –0.2 0.8 IIL Input Low Current II standby Standby Input Current CI Internal Input Capacitance Co1 Co2 External Output Capacitance MTBF Reliability (1) (2) (3) mVpp µs 30 Iotrip VI on mV Pins 3 and 5 connected Per Telcordia SR-332 50% stress, TA = 40°C, ground benign –1 mA 2 mA 2 µF 0 (3) 5000 0 (3) 5000 1.5 V µF 106 Hrs See Safe Operating Area curves or contact the factory for the appropriate derating. The On/Off Enable (pin 3) has an internal pull-up and may be controlled with an open-collector (or open-drain) transistor. The input is diode protected and may be connected to +VI. The maximum open-circuit voltage is 7 V. If it is left open circuit the converter will operate when input power is applied. An output capacitor is not required. Submit Documentation Feedback 5 PTB48500 PTB48500A and PTB48502A are Not Recommended for New Designs PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NO. +VI (1) 1 The positive input supply for the module with respect to –VI. When powering the module from a –48 V telecom central office supply, this input is connected to the primary system ground. –VI 5 The negative input supply for the module, and the 0 VDC reference for the Enable, EN Out, and Sync Out signals. When the module is powered from a +48-V supply, this input is connected to the 48-V Return. VO1 10 The higher regulated power output voltage, which is referenced to the COM node. VO2 6 The lower regulated power output voltage, which is referenced to the COM node. COM 7 The secondary return reference for the module's two regulated output voltages. It is dc isolated from the input supply pins. VO2 Adjust 9 Using a single resistor, this pin allows VO2 to be adjusted higher or lower than the preset value. If not used, this pin should be left open circuit. Enable (2) 3 This is an open-collector (open-drain) positive logic input that enables the module output. This pin is referenced to –VI. A logic 0 at this pin disables the module's outputs, and a high impedance enables the outputs. If not used the pin should be left unconnected. EN Out 4 This open-collector output may be used to enable the output of other DC/DC converters in applications where the power-up sequence of the related voltages must be precisely controlled. The output is used principally to control the startup up of a PTB4851xx module when powering ADSL circuits based on the AC7 chipset. The signal is referenced to –VI, and is active low. It is initially off (high impedance), and turns on when the output voltage, VO1, has risen to its nominal set-point voltage. Sync Out 2 The signal generated by this pin is designed to be used exclusively with the PTB48510 in AC7 ADSL applications. When the Sync Out of this converter is connected directly to the Sync In pin of the PTB48510, both modules will operate at the same switch conversion frequency. 8 (POR: Available to PTB48500 and PTB48501 only.) This pin produces an active-low power-on reset signal that may be used to reset logic circuitry. The output is set low during power up just as the output voltage from VO1 starts to rise. It remains low for 10 ms after the voltage at VO1 has reached its nominal set-point voltage. This signal is referenced to the COM node, and has a 3.3-kΩ internal pull-up resistor to VO1. POR (3)/COM (4) (1) (2) (3) (4) 6 DESCRIPTION NAME Shaded functions indicate signals that are referenced to –VI. Denotes positive logic: Open = Normal operation, –VI = Outputs Off Denotes negative logic: High = Normal operation, Low = Reset This pin is COM on the PTB48502. Submit Documentation Feedback PTB48500A and PTB48502A are Not Recommended for New Designs PTB48500 PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (1) (2) (3) CHARACTERISTIC DATA (PTB48500A) EFFICIENCY vs LOAD CURRENT POWER DISSIPATION vs LOAD CURRENT 10 100 (See Note B) 90 PD − Power Dissipation − W (See Note B) VI = 36 V Efficiency − % VI = 48 V 80 VI = 75 V 70 60 50 VI = 36 V 6 VI = 48 V 4 VI = 75 V 2 0 0 2 4 6 8 10 IL − Load Current − A 12 0 2 4 6 8 10 IL − Load Current − A Figure 1. Figure 2. CROSS REGULATION ∆Vox vs Ioy Iox = 1 A and VI = 48 V SAFE OPERATING AREA VI = 48 VDC 6 90 4 TA − Ambient Temperature 5−C Cross Regulation ∆ VO − mV 8 VO 1 vs IO 2 2 0 VO 2 vs IO 1 −2 −4 400LFM 80 Nat Conv 70 100LFM 60 200LFM 50 40 30 VI = 48 VDC −6 0 1 2 3 4 5 IL − Load Current − A 6 7 Figure 3. (1) (2) (3) 12 20 0 5 (See Note B) 10 15 20 25 Total Output Power − W 30 Figure 4. A. Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the converter. B. Load current is increased proportionally from both outputs, up to the indicated maximum value of each respective output. C. SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper. Submit Documentation Feedback 7 PTB48500 PTB48500A and PTB48502A are Not Recommended for New Designs PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (1) (2) (3) PTB48501A CHARACTERISTIC DATA (PTB48501A) EFFICIENCY vs LOAD CURRENT POWER DISSIPATION vs LOAD CURRENT 12 100 (See Note B) PD − Power Dissipation − W 90 (See Note B) VI = 36 V Efficiency − % VI = 48 V 80 70 VI = 75 V 60 VI = 75 V 8 6 4 VI = 48 V 2 50 0 0 3 9 12 6 IL − Load Current − A 15 18 VI = 36 V 0 3 6 9 12 IL − Load Current − A Figure 6. CROSS REGULATION ∆Vox vs Ioy Iox = 1 A and VI = 48 V SAFE OPERATING AREA VI = 48 VDC 6 90 4 80 2 VO 1 vs IO 2 0 VO 2 vs IO 1 −2 −4 Nat Conv 70 100LFM 60 200LFM 50 40 30 8 (See Note C) 20 0 2 4 6 8 10 IL − Load Current − A 12 Figure 7. (1) (2) (3) 18 400LFM VI = 48 VDC −6 15 Figure 5. TA− Ambient Temperature 5−C Cross Regulation ∆ VO − mV 10 0 8 16 24 Total Output Power − W 32 Figure 8. A. Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the converter. B. Load current is increased proportionally from both outputs, up to the indicated maximum value of each respective output. C. SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper. Submit Documentation Feedback PTB48500A and PTB48502A are Not Recommended for New Designs www.ti.com PTB48500 PTB48501 PTB48502 SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (1) (2) (3) CHARACTERISTIC DATA (PTB48502A) [Io1 = 10 A, Io2 = 10 A represents 100% load] EFFICIENCY vs LOAD CURRENT POWER DISSIPATION vs LOAD CURRENT 100 12 (See Note B) 90 PD − Power Dissipation − W (See Note B) VI = 36 V Efficiency − % VI = 48 V 80 VI = 75 V 70 60 8 6 VI = 36 V 4 VI = 48 V 0 0 20 60 40 80 IL − Load Current − A 100 0 20 40 60 80 Figure 9. Figure 10. CROSS REGULATION ∆Vox vs Ioy Iox = 1 A and VI = 48 V SAFE OPERATING AREA VI = 48 V 6 90 4 80 2 100 IL − Load Current − A TA − Ambient Temperature 5−C Cross Regulation ∆ VO − mV VI = 75 V 2 50 VO 1 vs IO 2 0 VO 2 vs IO 1 −2 −4 400LFM Nat Conv 70 100LFM 60 200LFM 50 40 30 VI = 48 VDC −6 (See Note B, C) 20 0 2 4 6 8 IL − Load Current − A 10 Figure 11. (1) (2) (3) 10 0 10 20 30 40 50 60 70 80 90 100 Total Output Power − W Figure 12. A. Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the converter. B. Load current is increased proportionally from both outputs, up to the indicated maximum value of each respective output. C. SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper. Submit Documentation Feedback 9 PTB48500 PTB48500A and PTB48502A are Not Recommended for New Designs PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (1) (2) (3) CHARACTERISTIC DATA (PTB48502A) [Io1 = 8 A, Io2 = 10 A represents 100% load] EFFICIENCY vs LOAD CURRENT POWER DISSIPATION vs LOAD CURRENT 12 100 (See Note B) PD − Power Dissipation − W 90 (See Note B) VI = 36 V Efficiency − % VI = 48 V 80 VI = 75 V 70 60 VI = 75 V 8 6 VI = 36 V 4 VI = 48 V 2 0 50 0 20 60 40 80 IL − Load Current − A 0 100 80 CROSS REGULATION ∆Vox vs Ioy Iox = 1 A and VI = 48 V SAFE OPERATING AREA VI = 48 V 90 4 80 VO 1 vs IO 2 2 0 VO 2 vs IO 1 −2 −4 2 4 6 8 10 IL − Load Current − A 100 400LFM Nat Conv 70 60 100LFM 50 200LFM 40 30 20 12 Figure 15. 10 60 Figure 14. −6 (1) (2) (3) 40 Figure 13. 6 0 20 IL − Load Current − A TA− Ambient Temperature 5−C Cross Regulation ∆ VO − mV 10 VI = 48 VDC 0 10 (See Note B, C) 20 30 40 50 60 70 80 90 100 Total Output Power − W Figure 16. A. Characteristic data has been developed from actual products tested at 25°C. This data is considered typical data for the converter. B. Load current is increased proportionally from both outputs, up to the indicated maximum value of each respective output. C. SOA curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 in. × 4 in. double-sided PCB with 1 oz. copper. Submit Documentation Feedback PTB48500A and PTB48502A are Not Recommended for New Designs www.ti.com PTB48500 PTB48501 PTB48502 SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 APPLICATION INFORMATION ADJUSTING THE LOWER OUTPUT VOLTAGE OF THE PTB4850x CALCULATION OF THE ADJUST RESISTOR The PTB4850x series of DC/DC converters are designed to produce two logic-level supply voltages for use with the AC-7 ADSL chipset. The magnitude of lowest output voltage (Vo2) can be adjusted higher or lower by up to 10% or —20% of the nominal. The adjustment method uses a single external resistor.1 The value of the resistor determines the amount of adjustment, and its placement determines whether the voltage is increased or decreased. The resistor values can be calculated using the appropriate formula (see Equation 1 and Equation 2), or simply selected from the range of values given in Table 2. The placement of each resistor is as follows. Adjust Up: To increase the magnitude of both output voltages, place a resistor R1 between Vo2 Adj (pin 9) and the Vo2 (pin 6) voltage rail; see Figure 17. The value of the adjust resistor is calculated using one of the following equations. Use the equation for R1 to adjust up, or (R2) to adjust down. Va R [Adjust Up] + Rp * R s kW 1 ǒVa * VoǓ (1) Va ǒR2Ǔ [Adjust Down] + Rn ǒVo * VaǓ * R s kW (2) Where: Vo = Magitude of the original output voltage Va = Magnitude of the adjusted voltage Rp = Adjust-up constant from Table 1 Rn = Adjust-down constant from Table 1 Rs = Internal series resistor from Table 1 Table 1. Adjustment Range and Formula Parameters PTB4850x VO2 +VO 6 Part No. R1 Adjust Up VO2Adj COM 9 7 Figure 17. Adjust Up Adjust Down: To decrease the magnitude of both output voltages, add a resistor (R2), between Vo2 Adj (pin 9) and the COM (pin 7) voltage rail; see Figure 18. VO2Adj Vo(nom) 1.2 V 1.2 V Va(min) 0.96 V 0.84 V Va(max) 1.32 V 1.32 V Rp (kΩ) 1.648 1.196 Rn (kΩ) 4.624 3.598 Rs (kΩ) 18.2V 13.0 NOTES: 1. A 0.05 W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100 ppm/°C or better. Place the resistor in either the R1 or (R2) location, as close to the converter as possible. 2. Never connect capacitors to the Vo2 Adj pin. Capacitance added to this pin can affect the stability of the regulated output. +VO 6 Part No. 9 (R2) Adj Down COM PTB48502A Table 2. Adjust Resistor Values PTB4850x VO2 PTB48500(1)A 7 Figure 18. Adjust Down (1) PTB4850xA PTB48502A R1 / (R2) (1) R1 / (R2) (1) 0.848 N/A (0.5) kΩ 0.960 (0.3) kΩ (1.4) kΩ –19 0.972 (1.5) kΩ (2.3) kΩ –18 0.984 (2.9) kΩ (3.4) kΩ –17 0.996 (4.4) kΩ (4.6) kΩ –16 1.008 (6.1) kΩ (5.9) kΩ –15 1.020 (8.0) kΩ (7.4) kΩ –14 1.032 (10.2) kΩ (9.1) kΩ % Adjust Va (V) –21 –20 R1 =Adjust up, (R2) =Adjust down Submit Documentation Feedback 11 PTB48500 PTB48500A and PTB48502A are Not Recommended for New Designs PTB48501 PTB48502 www.ti.com SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 Table 2. Adjust Resistor Values (continued) SWITCHING FREQUENCY SYNCHRONIZATION Part No. Unsynchronized, the difference in switch frequency introduces a beat frequency into the input and output AC ripple components from the converters. The beat frequency can vary considerably with any slight variation in either converter's switch frequency. This results in a variable and undefined frequency spectrum for the ripple waveforms, which would normally require separate filters at the input of each converter. When the switch frequency of the converters are synchronized, the ripple components are constrained to the fundamental and higher. This simplifies the design of the output filters, and allows a common filter to be specified for the treatment of input ripple. PTB4850xA ) (1) R1 / (R2 PTB48502A R1 / (R2) (1) % Adjust Va (V) –13 1.044 (12.7) kΩ (11.1) kΩ –12 1.056 (15.7) kΩ (13.4) kΩ –11 1.068 (19.2) kΩ (16.1) kΩ –10 1.080 (23.4) kΩ (19.4) kΩ –9 1.092 (28.6) kΩ (23.4) kΩ –8 1.104 (35) kΩ (28.4) kΩ –7 1.116 (43.2) kΩ (34.8) kΩ –6 1.128 (54.2) kΩ (43.4) kΩ –5 1.140 (69.7) kΩ (55.4) kΩ –4 1.152 (92.8) kΩ (73.4) kΩ –3 1.164 (131) kΩ 103.0) kΩ –2 1.176 (208) kΩ 163.0) kΩ –1 1.188 (440) kΩ 343.0) kΩ 0 1.200 +1 1.212 148 kΩ 108.0 kΩ +2 1.224 65.8 kΩ 48.0 kΩ +3 1.236 38.4 kΩ 28.1 kΩ +4 1.248 24.6 kΩ 18.1 kΩ +5 1.260 16.4 kΩ 12.1 kΩ +6 1.272 10.9 kΩ 8.1 kΩ +7 1.284 7 kΩ 5.3 kΩ +8 1.296 4.1 kΩ 3.2 kΩ +9 1.308 1.8 kΩ 1.5 kΩ +10 1.320 0 kΩ 0.2 kΩ CONFIGURING THE PTB4850X AND PTB4851X FOR DSL APPLICATIONS When operated as a pair, the PTB4850x and PTB4851x converters are specifically designed to provide all the required supply voltages for powering xDSL chipsets. The PTB4850x produces two logic voltages. They include a 3.3-V source for logic and I/O, and a low-voltage for powering a digital signal processor core. The PTB4851x produces a balanced pair of complementary supply voltages that is required for the xDSL transceiver ICs. When used together in these types of applications, the PTB4850x and PTB4851x may be configured for power-up sequencing, and also synchronized to a common switch conversion frequency. Figure 20 shows the required cross-connects between the two converters to enable these two features. 12 POWER-UP SEQUENCING The desired power-up sequence for the AC7 supply voltages requires that the two logic-level voltages from the PTB4850x converter rise to regulation prior to the two complementary voltages that power the transceiver ICs. This sequence cannot be guaranteed if the PTB4850x and PTB4851x are allowed to power up independently, especially if the 48-V input voltage rises relatively slowly. To ensure the desired power-up sequence, the EN Out pin of the PTB4850x is directly connected to the activelow Enable input of the PTB4851x (see Figure 20). This allows the PTB4850x to momentarily hold off the outputs from the PTB4851x until the logic-level voltages have risen first. Figure 19 shows the power-up waveforms of all four supply voltages from the schematic of Figure 20. VCCIO (1 V/div) VCORE (1 V/div) +VTCVR (5 V/div) −VTCVR (5 V/div) HORIZ SCALE: 10 ms/Div Figure 19. Power-Up Sequencing Waveforms Submit Documentation Feedback PTB48500A and PTB48502A are Not Recommended for New Designs www.ti.com PTB48500 PTB48501 PTB48502 SLTS218C – SEPTEMBER 2003 – REVISED AUGUST 2006 VO2Adj −48 V RTN +VI + Input Filter PTB4850xA VO1 VCCIO VO2 VCORE Enable −48 V − −VI EN Out SyncOut SyncIn COM −VO2Adj +VI +VO PTB4851xA Enable −VI +VTCVR COM −VO −VTCVR Figure 20. Example of PTB4850x and PTB4851x Modules Configured for DSL Applications Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2015 PACKAGING INFORMATION Orderable Device Status (1) PTB48502AAZ NRND Package Type Package Pins Package Drawing Qty Surface Mount Module ERJ 10 9 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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