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PTN78060AAST

PTN78060AAST

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    DIPMODULE7

  • 描述:

    REG SW WIDE-VIN 15W ADJ HORZ SMD

  • 数据手册
  • 价格&库存
PTN78060AAST 数据手册
PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 15-W, WIDE-INPUT ADJUSTABLE POSITIVE-TO-NEGATIVE VOLTAGE REGULATOR MODULE FEATURES APPLICATIONS • • • • • • • • • • Up to 3-A Output Current Wide-Input Voltage (9 V to 29 V) Wide-Output Voltage Adjust (–15 V to –3 V) High Efficiency (Up to 88%) Undervoltage Lockout Output Current Limit Overtemperature Shutdown Operating Temperature: –40°C to 85°C Surface-Mount Package Available General-Purpose, Industrial Controls, HVAC Systems Test and Measurement, Medical Instrumentation AC/DC Adaptors, Vehicles, Marine, and Avionics • • DESCRIPTION The PTN78060A is a series of high-efficiency, buck-boost, integrated switching regulators (ISR), that represent the third generation in the evolution of the (PT)78NR100 series of products. In new designs, the PTN78060A series should also be considered in place of the PT6640 series of single in-line pin (SIP) products. In all cases, the PTN78060A has either similar or improved electrical performance characteristics. The caseless, double-sided package has excellent thermal characteristics, and is compatible with TI's roadmap for RoHS and lead-free compliance. Operating from a wide-input voltage range of 9 V to 29 V, the PTN78060A provides high-efficiency, positive-to-negative voltage conversion for loads of up to 3 A. The output voltage can be set to any value over a wide adjustment range using a single external resistor. The adjust range is –15 V to –3 V. The PTN78060A is suited to a wide variety of general-purpose industrial applications that operate off 12-V, 24-V, or tightly regulated 28-V dc power. C4(3) 4.7 µF Ceramic (Optional) 1 VO 7 1 PTN78060A 2 6 VI 3 + N/C C1(1) GND 100 µF Electrolytic (Required) C2 3 × 4.7 µF Ceramic (Required) 4 5 N/C RSET (2) 1%, 0.05 W (Required) + C3(1) 100 µF (Required) GND L O A D UDG−05094 (1) See the Application Information section for capacitor recommendations (2) RSET is required to adjust the output voltage lower than -3 V. See the Application Information section for values. (3) For reduced VO ripple and noise, a ceramic capacitor is suggested. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range unless otherwise noted all voltages with respect to GND UNIT TA Operating free-air temperature Over VI range Wave solder temperature Surface temperature of module body or pins (5 seconds) –40°C to 85°C Solder reflow temperature Surface temperature of module body or pins Horizontal TH (suffix AH) 260°C Horizontal SMD (suffix AS) 235°C Horizontal SMD (suffix AZ) Tstg Storage temperature PO Output power (1) 260°C –40°C to 125°C |VO| ≥ 5 V 15 W Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VI Input voltage TA Operating free-air temperature MIN MAX 9 32 - |VO| UNIT V –40 85 °C PACKAGE SPECIFICATIONS PTN78060x (Suffix AH, AS, and AZ) Weight Meets UL 94 V-O Mechanical shock Per Mil-STD-883D, Method 2002.3, 1 ms, ½ sine, mounted Mechanical vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz (1) 2 3.9 grams Flammability Qualification limit. Submit Documentation Feedback 500 G (1) Horizontal T/H (suffix AH) 20 G (1) Horizontal SMD (suffix AS & AZ) 20 G (1) PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS operating at 25°C free-air temperature, VI = 20 V, VO = –5 V, IO = IO (max), C1 = 100 µF, C2 = 3 × 4.7 µF, C3 = 100 µF, and C4 = 4.7 µF (unless otherwise noted) PARAMETER IO Output current VI Input voltage range VO TEST CONDITIONS TA = 85°C, natural convection airflow Over IO range η (1) VO = –12 V 0.1 1.25 (1) VO = –5 V 0.1 3 (1) VO = –3.3 V 0.1 3 (1) VO = –15 V 9 17 (2) VO = –12 V 9 20 (2) VO = –5 V 9 27 (2) VO = –3.3 V 9 28.7 (2) –40°C to +85°C Line regulation Over VI range ±10 Load regulation Over IO range ±10 Total output voltage variation Includes set point, line, load –40 < TA < 85°C ∆VO = –50 mV –15 RSET = 100 Ω, IO = 1 A, VO = –15 V 88% 87% RSET = 28.7 kΩ, IO = 3 A, VO = –5 V 82% Recovery time FS Switching frequency Over VI and IO ranges UVLO Undervoltage lockout VI increasing Ceramic 14.1 (4) CI External input capacitance Nonceramic 100 (4) CO External output capacitance 100 (5) 14 (6) VO over/undershoot (5) (6) µs 550 %VO 660 Per Telcordia SR-332, 50% stress, TA = 40°C, ground benign 8.9 kHz V µF 200 Equivalent series resistance (nonceramic) (4) A 200 2 440 Ceramic (1) (2) (3) V(PP) 5.5 5.5 Nonceramic V 77% 2% VO 1-A/µs load step from 50% to 100% IOmax Calculated reliability mV (3) –3 RSET = 2 kΩ, IO = 1.25 A, VO = –12 V Transient response MTBF V mV ±3% RSET = 221 kΩ, IO = 3 A, VO = –3.3 V Current limit threshold A ±0.5% 9 V ≤ VI ≤ (32 - |VO|) V 20-MHz bandwidth UNIT ±2% (3) Temperature variation Output voltage ripple MAX 1 TA = 25°C Efficiency IO (LIM) TYP 0.1 Set-point voltage tolerance Output voltage adjust range VO MIN VO = –15 V 1000 µF mΩ 106 Hr The maximum output current is 3 A or a maximum output power of 15 W, whichever is less. The maximum input voltage is limited and defined to be (32 - |VO|). The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1% with 100 ppm/°C or better temperature stability. A 100-µF electrolytic capacitor and three 4.7-µF ceramic capacitors are required across the input (VI and GND) for proper operation. Locate the ceramic capacitors close to the module. 100 µF of output capacitance is required for proper operation. See the application information for further guidance. This is the typical ESR for all the electrolytic (nonceramic) capacitance. Use 17 mΩ as the minimum when using max-ESR values to calculate. Submit Documentation Feedback 3 PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 PIN ASSIGNMENT 1 7 PTN78060A (Top View) 2 6 3 4 5 TERMINAL FUNCTIONS TERMINAL 4 I/O DESCRIPTION 1, 7 O The negative output voltage power connection. It is also the reference for the VO Adjust control input. For proper operation, pins 1 and 7 must be connected. VI 2 I The positive input voltage power node to the module, which is referenced to common GND. N/C 3 VO Adjust 4 N/C 5 GND 6 NAME NO. VO This pin is active and must be isolated from any electrical connection. I A 1% resistor must be connected between pin 4 and pin 7 to set the output voltage of the module. The adjust range is –15 V to –3 V. If left open-circuit, the output voltage defaults to –3 V. The temperature stability of the resistor should be 100 ppm/°C (or better). The standard resistor value for a number of common output voltages is provided in the application information. This pin is active and must be isolated from any electrical connection. I/O The common ground connection for both VI and VO power connections. Submit Documentation Feedback PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (9-V INPUT) (1) (2) OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT 75 VO = -12 V 70 VO = -15 V 65 VO = -5 V 60 VO = -3 V 55 50 0 0.5 1 1.5 2 2.5 3 300 4.5 250 VO = -15 V 200 150 100 VO = -5 V 50 VO = -3 V 0 0 1.5 1 VO = -5 V 0.5 3 VO = -3 V 0 0.5 1.5 1 2.5 2 3 IO - Output Current - A TEMPERATURE DERATING vs OUTPUT CURRENT TEMPERATURE DERATING vs OUTPUT CURRENT TEMPERATURE DERATING vs OUTPUT CURRENT 90 70 200 LFM 60 100 LFM 50 Nat conv 40 VO = -5 V 90 80 200 LFM 70 100 LFM 60 Nat conv 50 40 VO = -12 V 30 20 20 0 2 1.5 Figure 3. 80 30 2.5 0 2.5 2 VO = -15 V Figure 2. Ambient Temperature - oC Ambient Temperature - oC 1 VO = -12 V 3 Figure 1. 90 0.5 1 1.5 2 IO - Output Current - A Figure 4. (2) 0.5 4 3.5 IO - Output Current - A IO - Output Current - A (1) VO = -12 V Ambient Temperature - oC Efficiency - % 80 POWER DISSIPATION vs OUTPUT CURRENT PD - Power Dissipation - W 90 85 VO - Output Voltage Ripple - mVPP EFFICIENCY vs OUTPUT CURRENT 2.5 3 80 200 LFM 70 100 LFM 60 Nat conv 50 40 VO = -15 V 30 20 0 0.25 0.5 0.75 1 1.25 IO - Output Current - A Figure 5. 0 0.2 0.4 0.6 0.8 1 IO - Output Current - A Figure 6. The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm, double-sided PCB with 2 oz. copper. For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure 4, Figure 5, and Figure 6. Submit Documentation Feedback 5 PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (12-V INPUT) (1) (2) OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT 75 VO = -12 V 70 VO = -5 V VO = -15 V 65 VO = -3 V 60 55 50 0 0.5 1 1.5 2 2.5 3 VO = -15 V 120 80 VO = -5 V 40 VO = -3 V 1.5 2.5 2 2 1.5 1 VO = -5 V 0.5 3 VO = -3 V 0 0.5 1.5 1 2.5 2 3 IO - Output Current - A Figure 9. TEMPERATURE DERATING vs OUTPUT CURRENT TEMPERATURE DERATING vs OUTPUT CURRENT TEMPERATURE DERATING vs OUTPUT CURRENT 90 70 200 LFM 60 100 LFM 50 Nat conv 40 VO = -5 V 90 80 200 LFM 70 100 LFM 60 Nat conv 50 40 30 VO = -12 V 20 0 2.5 Figure 8. 80 30 VO = -15 V Figure 7. Ambient Temperature - oC Ambient Temperature - oC 1 VO = -12 V 3 IO - Output Current - A 20 0.5 1 1.5 2 IO - Output Current - A Figure 10. 6 0.5 3.5 0 0 0 90 (2) VO = -12 V 160 IO - Output Current - A (1) 4 200 Ambient Temperature - oC Efficiency - % 80 POWER DISSIPATION vs OUTPUT CURRENT PD - Power Dissipation - W 90 85 VO - Output Voltage Ripple - mVPP EFFICIENCY vs OUTPUT CURRENT 2.5 3 80 200 LFM 70 100 LFM 60 Nat conv 50 40 VO = -15 V 30 20 0 0.25 0.5 0.75 1 1.25 IO - Output Current - A Figure 11. 0 0.2 0.4 0.6 0.8 1 IO - Output Current - A Figure 12. The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 7, Figure 8, and Figure 9. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm, double-sided PCB with 2 oz. copper. For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure 10, Figure 11, and Figure 12. Submit Documentation Feedback PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 TYPICAL CHARACTERISTICS (24-V INPUT) (1) (2) EFFICIENCY vs OUTPUT CURRENT OUTPUT VOLTAGE RIPPLE vs OUTPUT CURRENT 160 80 75 70 65 VO = -5 V 60 55 VO = -3 V 50 45 40 0 0.5 1 1.5 2 2.5 3 3.5 140 120 PD - Power Dissipation - W VO - Output Voltage Ripple - mVPP 90 85 Efficiency - % POWER DISSIPATION vs OUTPUT CURRENT VO = -5 V 100 80 60 40 VO = -3 V 20 0 IO - Output Current - A 0 0.5 1 1.5 2.5 2 3 2.5 VO = -5 V 2 1.5 1 VO = -3 V 0.5 0 3 0 0.5 Figure 13. Figure 14. TEMPERATURE DERATING vs OUTPUT CURRENT Ambient Temperature - oC Ambient Temperature - oC 2 2.5 3 Figure 15. 90 80 70 200 200 LFM LFM 60 100LFM LFM 100 50 Nat Nat conv conv 40 30 VO = -3.3 -5 V V 20 80 70 200 200 LFM LFM 60 100LFM LFM 100 50 Nat conv Nat conv 40 VO VO == -5-5 VV 30 20 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 0 0.5 1 1.5 2 2.5 3 IO - Output Current - A Figure 16. (2) 1.5 TEMPERATURE DERATING vs OUTPUT CURRENT 90 (1) 1 IO - Output Current - A IO - Output Current - A Figure 17. The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 13, Figure 14, and Figure 15. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm, double-sided PCB with 2 oz. copper. For surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power pins. Please refer to the mechanical specification for more information. Applies to Figure 16, and Figure 17. Submit Documentation Feedback 7 PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 APPLICATION INFORMATION Adjusting the Output Voltage of the PTN78060A Wide-Output Adjust Power Modules General A resistor must be connected directly between the VO Adjust control (pin 4) and the output voltage (pin 7) to set the output voltage lower than –3 V. The adjustment range is from –15 V to –3 V. If pin 4 is left open, the output voltage defaults to the highest value, –3 V. Table 1 gives the standard resistor value for a number of common voltages, and with the actual output voltage that the value produces. For other output voltages, the resistor value can either be calculated using the following formula, or simply selected from the range of values given in Table 2. Figure 18 shows the placement of the required resistor. RSET = 54.9 kW ´ 1.25 V - 5.62 kW |VO| - 3 V (1) Input Voltage Considerations The PTN78060A is a buck-boost switching regulator. In order that the output remains in regulation, the input voltage must not exceed the output by a maximum differential voltage. Another consideration is the pulse width modulation (PWM) range of the regulator's internal control circuit. For stable operation, its operating duty cycle should not be lower than some minimum percentage. This defines the maximum advisable ratio between the regulator's input and output voltage magnitudes. For satisfactory performance, the maximum operating input voltage range must be equal to (32 – |VO|) volts. As an example, Table 1 gives the operating input voltage range for the common output bus voltages. In addition, the Electrical Characteristics define the available output voltage adjust range for various input voltages. Table 1. Standard Values of Rset for Common Output Voltages VO (Required) RSET (Standard Value) VO (Actual) Operating VI Range –15 V 100 Ω –14.997 V 9 V to 17 V –12 V 2 kΩ –12.006 V 9 V to 20 V –5 V 28.7 kΩ –5.000 V 9 V to 27 V –3.3 V 221 kΩ –3.303 V 9 V to 28.7 V VI C1 2 + PTN78060A VI VO GND Adj 6 4 VO 1, 7 C2 RSET 0.05 W 1% C3 + GND GND (1) A 0.05-W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100 ppm/°C (or better). Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 4 and 7 using dedicated PCB traces. (2) Never connect capacitors from VO Adjust to either GND or VO. Any capacitance added to the VO Adjust pin affects the stability of the regulator. Figure 18. VO Adjust Resistor Placement 8 Submit Documentation Feedback PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 Table 2. Output Voltage Set-Point Resistor Values VO Required RSET VO Required RSET VO Required RSET –15.0 V 99 Ω –11.9 V 2.09 kΩ –8.8 V 6.21 kΩ –14.9 V 147 Ω –11.8 V 2.18 kΩ –8.6 V 6.63 kΩ –14.8 V 196 Ω –11.7 V 2.27 kΩ –8.4 V 7.09 kΩ –14.7 V 245 Ω –11.6 V 2.36 kΩ –8.2 V 7.58 kΩ –14.6 V 296 Ω –11.5 V 2.45 kΩ –8.0 V 8.11 kΩ –14.5 V 347 Ω –11.4 V 2.55 kΩ –7.8 V 8.68 kΩ –14.4 V 400 Ω –11.3 V 2.65 kΩ –7.6 V 9.30 kΩ –14.3 V 453 Ω –11.2 V 2.75 kΩ –7.4 V 9.98 kΩ –14.2 V 507 Ω –11.1 V 2.82 kΩ –7.2 V 10.7 kΩ –14.1 V 562 Ω –11.0 V 2.96 kΩ –7.0 V 11.5 kΩ –14.0 V 619 Ω –10.9 V 3.07 kΩ –6.8 V 12.4 kΩ –13.9 V 676 Ω –10.8 V 3.18 kΩ –6.6 V 13.4 kΩ –13.8 V 734 Ω –10.7 V 3.29 kΩ –6.4 V 14.6 kΩ –13.7 V 794 Ω –10.6 V 3.41 kΩ –6.2 V 15.8 kΩ –13.6 V 854 Ω –10.5 V 3.53 kΩ –6.0 V 17.3 kΩ –13.5 V 916 Ω –10.4 V 3.65 kΩ –5.8 V 18.9 kΩ –13.4 V 979 Ω –10.3 V 3.78 kΩ –5.6 V 20.7 kΩ –13.3 V 1.04 kΩ –10.2 V 3.91 kΩ –5.4 V 22.9 kΩ –13.2 V 1.11 kΩ –10.1 V 4.04 kΩ –5.2 V 25.6 kΩ –13.1 V 1.18 kΩ –10.0 V 4.18 kΩ –5.0 V 28.7 kΩ –13.0 V 1.24 kΩ –9.9 V 4.33 kΩ –4.8 V 32.5 kΩ –12.9 V 1.31 kΩ –9.8 V 4.47 kΩ –4.6 V 37.2 kΩ –12.8 V 1.38 kΩ –9.7 V 4.62 kΩ –4.4 V 43.4 kΩ –12.7 V 1.46 kΩ –9.6 V 4.78 kΩ –4.2 V 51.6 kΩ –12.6 V 1.52 kΩ –9.5 V 4.94 kΩ –4.0 V 63.0 kΩ –12.5 V 1.60 kΩ –9.4 V 5.10 kΩ –3.8 V 80.1 kΩ –12.4 V 1.68 kΩ –9.3 V 5.27 kΩ –3.6 V 109 kΩ –12.3 V 1.76 kΩ –9.2 V 5.45 kΩ –3.4 V 166 kΩ –12.2 V 1.84 kΩ –9.1 V 5.63 kΩ –3.2 V 338 kΩ –12.1 V 1.92 kΩ –9.0 V 5.82 kΩ –3.0 V OPEN –12.0 V 2.01 kΩ –8.9 V 6.01 kΩ Submit Documentation Feedback 9 PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 CAPACITOR RECOMMENDATIONS FOR THE PTN78060 WIDE-OUTPUT ADJUST POWER MODULES Input Capacitor The minimum requirement for the input bus is 100 µF of nonceramic capacitance and 14.1 µF (3× 4.7 µF) of ceramic capacitance, in either an X5R or X7R temperature characteristic. Ceramic capacitors should be located within 0.5 inch (1,27 cm) of the regulator's input pins. Electrolytic capacitors can be used at the input, but only in addition to the required ceramic capacitance. The minimum ripple current rating for any nonceramic capacitance must be 350 mA rms. The ripple current rating of electrolytic capacitors is a major consideration when they are used at the input. This ripple current requirement can be reduced by placing more ceramic capacitors at the input, in addition to the minimum required 14.1 µF. Tantalum capacitors are not recommended for use at the input bus, as none were found to meet the minimum voltage rating of 2 × (maximum dc voltage + ac ripple). The 2× rating is standard practice for regular tantalum capacitors to ensure reliability. Polymer-tantalum capacitors are more reliable, and are available with a maximum rating of typically 20 V. These can be used with input voltages up to 16 V. Output Capacitor The minimum capacitance required to ensure stability is a 100-µF capacitor. Either ceramic or electrolytic-type capacitors can be used. The minimum ripple current rating for the nonceramic capacitance must be at least 200 mA rms. The stability of the module and voltage tolerances is compromised if the capacitor is not placed near the output bus pins. A high-quality, computer-grade electrolytic capacitor should be adequate. A ceramic capacitor can be also be located within 0.5 inch (1,27 cm) of the output pin. For applications with load transients (sudden changes in load current), the regulator response improves with additional capacitance. Additional electrolytic capacitors should be located close to the load circuit. These capacitors provide decoupling over the frequency range, 2 kHz to 150 kHz. Aluminum electrolytic capacitors are suitable for ambient temperatures above 0°C. For operation below 0°C, tantalum or Os-Con-type capacitors are recommended. When using one or more nonceramic capacitors, the calculated equivalent ESR should be no lower than 10 mΩ (17 mΩ using the manufacturer's maximum ESR for a single capacitor). A list of recommended capacitors and vendors are identified in Table 3. Ceramic Capacitors Above 150 kHz, the performance of aluminum electrolytic capacitors becomes less effective. To further reduce the reflected input ripple current, or improve the output transient response, multilayer ceramic capacitors must be added. Ceramic capacitors have low ESR, and their resonant frequency is higher than the bandwidth of the regulator. When placed at the output, their combined ESR is not critical as long as the total value of ceramic capacitance does not exceed 200 µF. Tantalum Capacitors Tantalum-type capacitors may be used at the output and are recommended for applications where the ambient operating temperature can be less than 0°C. The AVX TPS, Sprague 593D/594/595, and Kemet T495/T510/T520 capacitors series are suggested over many other tantalum types due to their rated surge, power dissipation, and ripple current capability. As a caution, many general-purpose tantalum capacitors have considerably higher ESR, reduced power dissipation, and lower ripple current capability. These capacitors are also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do not have a stated ESR or surge current rating are not recommended for power applications. When specifying Os-Con and polymer-tantalum capacitors for the output, the minimum ESR limit is encountered well before the maximum capacitance value is reached. Capacitor Table The capacitor table, Table 3, identifies the characteristics of capacitors from vendors with acceptable ESR and ripple current (rms) ratings. The recommended number of capacitors required at both the input and output buses is identified for each capacitor type. This is not an extensive capacitor list. Capacitors from other vendors are available with comparable specifications. Those listed are for guidance. The rms rating and ESR (at 100 kHz) are critical parameters necessary to ensure both optimum regulator performance and long capacitor life. 10 Submit Documentation Feedback PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 Designing for Load Transients The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of 1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the required value of output capacitance. As the di/dt of a transient is increased, the response of a converter's regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation of any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target application specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional output capacitor decoupling. In these cases, special attention must be paid to the type, value, and ESR of the capacitors selected. If the transient performance requirements exceed those specified in the data sheet, the selection of output capacitors becomes more important. Review the minimum ESR in the characteristic data sheet for details on the capacitance maximum. Table 3. Recommended Input/Output Capacitors CAPACITOR CHARACTERISTICS QUANTITY WORKING VOLTAGE (V) VALUE (µF) EQUIVALENT SERIES RESISTANCE (ESR) (Ω) 85°C MAXIMUM RIPPLE CURRENT (IRMS) (mA) FC( Radial) 35 100 0.117 555 8 x 11,5 ≥1 1 EEUFC1V01 FC (SMD) 35 100 0.015 670 10 x10,2 ≥1 1 EEVFC1V101P United Chemi-Con PXA (SMD) 16 180 0.016 4360 8 x 12 ≥1 (1) ≤1 PXA16VC180MF60 (VI, |VO| < 14 V) PS 25 100 0.020 4300 10 x 12,5 ≥1 (1) ≤1 10PS100MJ12 (VI < 22V) LXZ 50 100 0.22 485 8 x 12,5 ≥1 (1) 1 LXZ50VB101M8X12LL MVY(SMD) 50 100 0.300 500 10 x 10 ≥1 1 MVY50VC101M10X10TP Nichicon UWG (SMD) 50 100 0.300 500 10 x 10 ≥1 1 UWG1H101MNR1GS F550 (Tantalum) 10 100 0.055 2000 7,7 x 4,3 HD 50 120 0.072 979 10 x12,5 Sanyo Os-Con SVP (SMD) 20 100 0.024 2500 8 x 12 ≥1 (1) ≤1 20SVP100M (VI ≤ 16 V) SP 16 100 0.032 2890 10 x 5 ≥1 (1) ≤1 16SP100M (VI, |VO| ≤ 14 V) 20 100 0.085 1543 7,3 L x 4,3 W x 4,1 H N/R (3) ≤3 TPSV107M020R0085 (|VO| ≤ 10 V) 20 100 0.200 > 817 N/R (3) ≤3 TPSE107M020R0200 (|VO| ≤ 10 V) Murata X5R Ceramic 16 47 0.002 >1000 3225 ≥3 ≤3 GRM32ER61C476M (VI, |VO| ≤ 13.5 V) Murata X5R Ceramic 6.3 47 0.002 >1000 3225 N/R (1) ≤3 GRM42-2X5R476M6.3 (|VO| ≤ 5.5 V) TDK X7R Ceramic 25 2.2 0.002 >1000 3225 ≥6 (4) 1 C3225X7R1E225KT/MT (VI ≤ 20 V) Murata X7R Ceramic 25 2.2 0.002 >1000 3225 ≥6 (4) 1 GRM32RR71E225K (VI ≤ 20 V) Kemet X7R Ceramic 25 2.2 0.002 >1000 3225 ≥6 (4) 1 C1210C225K3RAC (VI ≤ 20 V) AVX X7R Ceramic 25 2.2 0.002 >1000 3225 ≥6 (4) 1 C12103C225KAT2A (VI ≤ 20 V) Murata X7R Ceramic 50 4.7 0.002 >1000 3225 ≥3 1 GRM32ER71H475KA88L TDK X7R Ceramic 50 2.2 0.002 >1000 3225 ≥6 1 C3225X7R1H225KT Murata Radial Through-hole 50 2.2 0.004 >1000 10 H x 10 W x4D ≥6 1 RPER71H2R2KK6F03 CAPACITOR VENDOR/ COMPONENT SERIES AVX Tantalum TPS (SMD) (1) (2) (3) (4) PHYSICAL SIZE (mm) INPUT OUTPUT BUS BUS (1) N/R ≥1 ≤ 3 (2) 1 (1) VENDOR NUMBER F551A107MN (|VO| ≤ 5 V) UHD1H151MHR The voltage rating of the input capacitor must be selected for the desired operating input voltage range of the regulator. To operate the regulator at a higher input voltage, select a capacitor with the next higher voltage rating. The maximum voltage rating of the capacitor must be selected for the desired set-point voltage (VO ). To operate at a higher output voltage, select a capacitor with a higher voltage rating. Not recommended (N/R). The voltage rating does not meet the minimum operating limits in most applications. The maximum rating of the ceramic capacitor limits the regulator's operating input voltage to 20 V. Select an alternative ceramic component to operate at a higher input voltage. Submit Documentation Feedback 11 PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 Power-Up Characteristics When configured per the standard application, the PTN78060A power module produces a regulated output voltage following the application of a valid input source voltage. During power up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. The soft-start circuitry introduces a short time delay (typically 5 ms – 10 ms) into the power-up characteristic. This is from the point that a valid input source is recognized. Figure 19 shows the power-up waveforms when operating from a 12-V input and with the output voltage adjusted to –5-V. The waveforms were measured with a 2.8-A resistive load. VI (5 V/div) VO (2 V/div) II (2 A/div) t - Time = 5 ms/div Figure 19. Power-Up Waveforms Undervoltage Lockout The undervoltage lockout (UVLO) circuit prevents the module from attempting to power up until the input voltage is above the UVLO threshold. This is to prevent the module from drawing excessive current from the input source at power up. Below the UVLO threshold, the module is held off. Current Limit Protection The module is protected against load faults with a continuous current limit characteristic. Under a load-fault condition, the output current increases to the current limit threshold. Attempting to draw current that exceeds the current limit threshold causes the module to progressively reduce its output voltage. Current is continuously supplied to the fault until the fault is removed. Once it is removed, the output voltage promptly recovers. When limiting output current, the regulator experiences higher power dissipation, which increases its temperature. If the temperature increase is excessive, the module's overtemperature protection begins to periodically turn the output voltage off. Overtemperature Protection A thermal shutdown mechanism protects the module's internal circuitry against excessively high temperatures. A rise in temperature may be the result of a drop in airflow, a high ambient temperature, or a sustained current limit condition. If the internal temperature rises excessively, the module turns itself off, reducing the output voltage to zero. The module exercises a soft-start power up when the sensed temperature has decreased by about 10°C below the trip point. NOTE: Overtemperature protection is a last-resort mechanism to prevent damage to the module. It should not be relied on as permanent protection against thermal stress. Always operate the module within its temperature derated limits, for the worst-case operating conditions of output current, ambient temperature, and airflow. Operating the module above these limits, albeit below the thermal shutdown temperature, reduces the long-term reliability of the module. 12 Submit Documentation Feedback PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 Optional Input/Output Filters Power modules include internal input and output ceramic capacitors in all of their designs. However, some applications require much lower levels of either input reflected or output ripple/noise. This application describes various filters and design techniques found to be successful in reducing both input and output ripple/noise. Input/Output Capacitors The easiest way to reduce output ripple and noise is to add one or more 1-µF ceramic capacitors, such as C5 shown in Figure 20. Ceramic capacitors should be placed close to the output power terminals. A single 4.7-µF capacitor reduces the output ripple/noise by 10% to 30% for modules with a rated output current of less than 3 A. (Note: C4 is required to improve the regulators transient response, and does not reduce output ripple and noise.) Switching regulators draw current from the input line in pulses at their operating frequency. The amount of reflected (input) ripple/noise generated is directly proportional to the equivalent source impedance of the power source including the impedance of any input lines. The addition of C1,≥4.7-µF (2 ×2.2 µF) ceramic capacitor, near the input power pins, reduces reflected conducted ripple/noise by up to 20%. C6 4.7 µF Ceramic 2 VI VI PTN78060A GND + C1 4.7 mF Ceramic C2 100 µF Electrolytic (Required) C3(1) 3 y 4.7 mF Ceramic (Required) Vo 1,7 Vo Adjust 6 4 RSET GND C4 (2) + 100 µF (Required) C5 4.7 µF Ceramic GND UDG−05092 (1) See the specifications for required value and type. (2) See the Application Information section for suggested value and type. Figure 20. Adding High-Frequency Bypass Capacitors to the Input and Output π Filters If a further reduction in ripple/noise level is required for an application, higher order filters must be used. A π (pi) filter, employing a ferrite bead (Fair-Rite Pt. No. 2673000701 or equivalent) in series with the input or output terminals of the regulator reduces the ripple/noise by at least 20 db (see Figure 21 and Figure 22). In order for the inductor to be effective ceramic capacitors are also required. (See the Capacitor Recommendations for additional information on vendors and component suggestions.) These inductors plus ceramic capacitors form an excellent filter because of the rejection at the switching frequency (650 kHz - 1 MHz). The placement of this filter is critical. It must be located as close as possible to the input or output pins to be effective. The ferrite bead is small (12,5 mm × 3 mm), easy to use, low cost, and has low dc resistance. Fair-Rite also manufactures a surface-mount bead (part number 2773021447). It is rated to 5 A, and can be used on the output bus. As an alternative, suitably rated 1-µH to 5-µH wound inductors can be used in place of the ferrite inductor bead. Submit Documentation Feedback 13 PTN78060A www.ti.com SLTS245B – APRIL 2005 – REVISED AUGUST 2006 C7 4.7 µF Ceramic VI L1 1 µH − 5 µH 2 1,7 VI GND GND Adjust 6 C2 100 µF Electrolytic (Required) VO Vo PTN78060A + C1 4.7 µF Ceramic L2 1 µH − 5 µH 4 C3 3 × 4.7 µF 50 V Ceramic (Required) + RSET (2) + C4 (2) 100 µF (Required) C5 4.7 µF Ceramic C6 (3) GND UDG−05093 (1) See the specifications for required value and type. (2) See the Application Information section for suggested value and type. (3) Recommended when IO > 2 A.. Figure 21. Adding π Filters (IO≤ 3 A) 45 40 Attenuation − dB 35 1 MHz 30 25 20 600 kHz 15 10 0 0.5 1 1.5 2 Load Current − A 2.5 3 Figure 22. π-Filter Attenuation vs. Load Current 14 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) PTN78060AAH ACTIVE ThroughHole Module EUW 7 36 RoHS Exempt & Green SN N / A for Pkg Type -40 to 85 PTN78060AAS ACTIVE Surface Mount Module EUY 7 36 Non-RoHS & Green SNPB Level-1-235C-UNLIM/ Level-3-260C-168HRS -40 to 85 PTN78060AAST ACTIVE Surface Mount Module EUY 7 250 Non-RoHS & Green SNPB Level-1-235C-UNLIM/ Level-3-260C-168HRS -40 to 85 PTN78060AAZ ACTIVE Surface Mount Module EUY 7 36 RoHS (In Work) & Green SNAGCU Level-3-260C-168 HR -40 to 85 PTN78060AAZT ACTIVE Surface Mount Module EUY 7 250 RoHS (In Work) & Green SNAGCU Level-3-260C-168 HR -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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