PTRF1212IRGZR

TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 Dual VCO/PLL Synthesizer With IF Down-Conversion • • • • • • • • • S-Band LO Frequency Range: – TRF1112: 1700 to 2400 MHz – TRF1212: 2400 MHz to 3550 MHz UHF LO Frequency Range: 325 MHz to 460 MHz Phase Noise is 0.5 RMS Typ 100 Hz to 1 MHz Rx Noise Figure of 5 dB, Typ UHF LO Tuning Step Size of 125 kHz With 18 MHz Reference Typical Gain of 90 dB, Including 15-dB Loss IF2 SAW Filter Input Third Order Intercept Point > 0 dBm Input 1-dB Compression Point > –10 dBm Gain Control Range of 90 dB Typ DESCRIPTION The TRF1112 / TRF1212 are UHF-VHF down converters with integrated UHF and S-band frequency synthesizers for radio applications in the 2GHz to 4GHz range. The device integrates an image reject mixer, IF gain blocks, automatic gain control (AGC), and two complete phase locked loop (PLL) circuits including: VCOs, resonator circuit, varactors, dividers, and phase detectors. TRF1112 / TRF1212 PIN OUT LPCC−48 PACKAGE (TOP VIEW) EXTLO1N EXTLO1P VCCLO1 LO1OP LO1ON LO1BPA LO1TUN LO1BPB IF2BIN IF2BIP IF2AIN IF2AIP KEY SPECIFICATIONS 48 47 46 45 44 43 42 41 40 39 38 37 • • • The TRF1112 / TRF1212 are designed to function as part of Texas Instruments 2.5-GHz and 3.5-GHz complete radio chipsets, respectively. In the chipset, two chips function together to double-down convert RF frequencies to an IF frequency that is suitable for most baseband modem ADCs. The TRF1112 / TRF1212 performs the second down conversion from the first IF frequency (480 MHz typical) to a final IF frequency (20-50 MHz). The radio chipset features sufficient linearity, phase noise and dynamic range to work in single carrier or multi-carrier, line-of-sight or non-line-of-sight, IEEE standard 802.16, BWIF, or proprietary systems. Due to the modular nature of the chipset, it is ideal for use in systems that employ transmit or receive diversity. CP2O LD1 LF1 EN FRBP VCCD1 FR VCCD2 CLK DATA LF2 LD2 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 AGCO IFBPB IF1IP IF1IN VCCA VCCB VERR VREF VFB VCCC IF2AOP IF2AON 13 14 15 16 17 18 19 20 21 22 23 24 • • Low Phase Noise High Dynamic Range Image-Reject Downconverter Selectable IF Filters Internal or External AGC Control With Peak Detector and Voltage Reference Analog Gain Control Range Direct Interface to A/D Dual VCO/PLL With On-Chip Resonator For Double Down-Conversion Architecture CP2O LO2TUN LO2BPB VDET AGCI LO2BPA VCCLO2 BBON BBOP VBGR IF2BON IF2BOP FEATURES • • BLOCK DIAGRAM The detailed block diagram and the pin-out of the ASIC are shown in Figure 1 and the Terminal Functions table. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 VCCC VCCD1 VCCB VCCA Power Supply IF2 LPF IF2AOP 90 º BPF IF2AON IF1 IF2AIP IF VGA IF2AIN IFBPB BBOP BBON IF1IP LPF IF1IN IF2BOP BPF IF2BON IF2BIP IF2BIN Down−converter DETECTOR 90 º VDET VFB LO1OP N N LO1ON VERR Chrg Pump Chrg Pump VCO1 VCCD2 Synthesizer #1 DATA CLK VBGR R Synthesizer #2 Synthesizer Data Decoder & Controller EN VREF VCO2 Automatic Gain Controller AGCI AGCO LD2 LF2 LO2BPA LO2BPB CP20 VCCLO2 LO2TUN FRBP FR LO1BPA LO1BPB LD1 LFI CP1O VCCLO1 LO1TUN EXTLOIP EXTLOIN Figure 1. Detailed Block Diagram of TRF1112 / TRF1212 TERMINAL FUNCTIONS TERMINAL NO. I/O TYPE DESCRIPTION 1 CP1O O Analog Analog Synthesizer 1 Charge Pump Output 2 LD1 O Digital Synthesizer 1 Lock Detect Output, High is locked 3 LF1 O Analog Lock Detector Filter Capacitor for LO1, 0.01 µF Typ. 100 kΩ pull-up (1) 4 EN I Digital 3-wire bus Enable; Active High 5 FRBP O Analog Reference Frequency Bypass, Internally biased to 2.5 V. 6 VCCD1 I Power Digital Power Supply Voltage 7 FR I Analog Reference Frequency Source Input, HCMOS input. (DC level = 2.5 V) 8 VCCD2 I Power Digital Power Supply Voltage 9 CLK I Digital 3-wire bus Clock 10 DATA I Digital 3-wire bus Data 11 LF2 O Analog Lock Detector Filter Capacitor for LO2, 0.01 µF typ 100 kΩ pull-up (1) 12 LD2 O Analog Synthesizer 2 Lock Detect Output, High is locked 13 CP2O O Analog Synthesizer 2 Charge Pump Output 14 LO2TUN I Analog Synthesizer 2 VCO Input tune port 15 LO2BPB O Analog Bypass cap for LO2, 0.1 µF (min) DCV = 1 V 16 VDET O Analog Peak Detector Output (1) 2 NAME Current leakage on the order of 10 µA through the capacitor or by any other means from either LF pin can cause false loss of lock signals. The two pull up resistors (R23 and R24) in Figure 20 reduce this sensitivity. IF2 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 TERMINAL FUNCTIONS (continued) TERMINAL NO. NAME I/O 17 AGCI I 18 LO2BPA O 19 VCCLO2 20 BBON 21 BBOP 22 VBGR 23 TYPE DESCRIPTION Analog AGC Voltage Input, 0-3 V Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. I Power VCC for LO2, Low Noise Supply O Analog IF output (differential) negative, DC coupled, internally biased to 3 V typical O Analog IF output (differential) positive, DC coupled, internally biased to 3 V typical O Analog Band-Gap Reference Voltage, 1.17 V IF2BON O Analog IF2B output (differential) negative, DC coupled, internally biased to 4 V typical 24 IF2BOP O Analog IF2B output (differential) positive , DC coupled, internally biased to 4 V typical 25 IF2AON O Analog IF2A output (differential) negative, DC coupled, internally biased to 4 V typical 26 IF2AOP O Analog IF2A output (differential) positive, DC coupled, internally biased to 4 V typical 27 VCCC I Power Analog Power Supply Voltage 28 VFB I Analog Error Amplifier Feedback Input 29 VREF I Analog Reference Frequency Input 30 VERR O Analog Error Amplifier Output, internal op amp output 31 VCCB I Power Analog Power Supply Voltage 32 VCCA I Power Analog Power Supply Voltage 33 IF1IN I Analog IF1 input (differential) negative, DC coupled, Internally biased to 1.4 V typical 34 IF1IP I Analog IF1 input (differential) positive, DC coupled, Internally biased to 1.4 V typical 35 IFBPB O Analog Bypass cap for IF amp, 0.1 µF (min), DCV = 1 V 36 AGCO O Analog AGC Voltage Output Used to control Front end gain for extended dynamic range 37 IF2AIP I Analog IF2A input (differential) positive, DC coupled, Internally biased to 3.0 V typical 38 IF2AIN I Analog IF2A input (differential) negative, DC coupled, Internally biased to 3.0 V typical 39 IF2BIP I Analog IF2B input (differential) positive, DC coupled, Internally biased to 3.0 V typical 40 IF2BIN I Analog IF2B input (differential) negative, DC coupled, Internally biased to 3.0 V typical 41 LO1BPB O Analog Bypass cap for LO1 0.1 µF (min), DCV = 1 V 42 LO1TUN I Analog Synthesizer1 VCO Tune port Input 43 LO1BPA O Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to any other pin. 44 LO1ON O Analog LO1 output (differential) neg. Negative and positive VCC bias (+5 V) for LO buffer amp. 45 LO1OP O Analog LO1 output (differential) pos. Negative and positive VCC bias (+5 V) for LO buffer amp. 46 VCCLO1 I Power VCC for LO1, Low Noise Supply 47 EXTLO1P I Analog External VCO input (differential) positive and logic level for VCO select. 48 EXTLO1N I Analog External VCO input (differential) negative and logic level for VCO select. – BACK – – Back side of package has metal base that must be grounded for thermal and RF performance. 3 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 ABSOLUTE MAXIMUM RATINGS UNIT VCC DC Supply Voltage 0.0 V to 5.5 V ICC DC Supply Current 270 mA Pin RF Input Power 20 dBm TJ Junction Temperature Pd Power Dissipation 1.5 W Digital Input Pins –0.3 to 5.5 V 150°C Analog Input Pins TBD θJC Thermal Resistance Junction-to-Ambient (1) Tstg Storage Temperature Top Operating Temperature 25°C/W – 40°C to 105°C –40°C to 85°C Lead Temperature, 40 Sec Max. (1) 260°C Thermal resistance is junction to ambient assuming thermal pad with 16 thermal vias under package metal base see recommended PCB layout (see Figure 20.) DC ELECTRICAL CHARACTERISTICS VCC = 5 V, T = 25°C (unless otherwise noted) PARAMETER VCC DC supply voltage ICC DC supply current TEST CONDITIONS MIN TYP MAX 4.8 5.2 200 UNIT V mA DOWNCONVERTER ELECTRICAL CHARACTERISTICS VCC = 5 V, TA = 25°C, FIF = 480 MHz, IF2 SAW 43.75 MHz unless otherwise stated OVERALL DOWNCONVERTER SIGNAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 400 480 500 MHz IF1IP/N to BBOP/N at VAGCI = 3 V 90 95 100 dB IF1IP/N to BBOP/N at VAGCI = 0 through 3 V 78 90 dB ±0.3 dB 35 dBc High Gain ( VAGCI = 2 V) IF1IP/N to BBOP/N at 100 Ω diff 4.7 dB High Gain ( VAGCI = 2 V) IF1IP/N to BBOP/N at 100 Ω diff –75 Low Gain ( VAGCI = 0 V) IF1IP/N to BBOP/N at 100 Ω diff –10 fIF1 IF1 input frequency Gmax Maximum gain DRG Gain control range ∆Gmax Gain flatness IF1IP/N to IF2A/BOP/N or BBOP/N for any gain setting. Measured in 6 MHz BW, excluding BPF gain variations IR Image rejection IF1IP/N to IF2A/BOP/N Measured into 1 kΩ differential load IF2 = 35–60 MHz NF Noise figure IP-1dB Input power at 1dB gain compression IIP3 Input 3rd order intercept ZIF1 IF1 input impedance Differential mode RLIF1 IF1 input return loss Measured into 100 Ω differential load at IF1P/N input fIF2 IF2 frequency ZIF2O IF2A/BO output impedance Measured in differential mode At IF2A/BOP/N ISOPP Port-to-port isolation Measured between IF2AOP/N to IF2BOP/N and IF2AIP/N to IF2BIP/N with the Filter Select set high or low. 30 dB ISOOI Output-to-input port isolation Measured between IF2A/BOP/N and IF2A/BIP/N with the Filter Select set high or low. 60 dB ZF2I IF2A/BI input impedance VBB,OUT Output signal level Measured into a 1000 Ω differential load at BBOP/N at any gain with functional AGC 1.2 IMD Closed-loop AGC, VBB,OUT = 1.2 V Any input power up to –20 dBm. 4 In-band intermodulation 30 High Gain ( VAGCI = 2 V) IF1IP/N to BBOP/N at 100 Ω diff Low Gain ( VAGCI = 0 V) IF1IP/N to BBOP/N at 100 Ω diff dBm –65 –5 –11 dBm 0 100 Ω –16 dB 25 70 Ω 50 1 MHz 2 kΩ Vppd –35 –30 dBc TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 DOWNCONVERTER ELECTRICAL CHARACTERISTICS (continued) VCC = 5 V, TA = 25°C, FIF = 480 MHz, IF2 SAW 43.75 MHz unless otherwise stated OVERALL DOWNCONVERTER SIGNAL CHARACTERISTICS PARAMETER ZBB TEST CONDITIONS Baseband section output impedance MIN Measured in differential mode at BBOP/N TYP MAX UNIT Ω 50 SYNTHESIZER #1 (S-BAND PLL) ELECTRICAL CHARACTERISTICS SYNTHESIZER #1 SIGNAL CHARACTERISTICS PARAMETER TEST CONDITIONS fRef Reference frequency fLO1 Output frequency range MSLO1 Tuning sensitivity ∆fLO1 Step size, nominal For 18-MHz reference input PLO1 Power level Measured into a 100-Ω differential load at the LO1OP/N port, over temperature and frequency range φFR Free running VCO1 SSB phase noise at 100 kHz Measured into 100-Ω differential load at the LO1OP/N port VOC1 φLD LO1 Locked synthesizer 1 SSB phase noise at 10 kHz Locked Synthesizer 1 SSB phase noise at 100 kHz MIN Reference frequency can vary. 18 MHz is used for reference design Also see 1 Note that for source peak-to-peak voltages of less than 4 V and dc component other than 2.5-V degradation of the close-in phase noise may occur. For oscillators with no dc component, a dc voltage may be applied using a voltage divider (see the schematic and the Input Reference Requirements table). TYP MAX 18 MHz TRF1112 1700 2400 TRF1212 2400 3550 TRF1112, For VLO1TUN≥ 2 V 200 400 TRF1212, For VLO1TUN≥ 2 V 300 600 1 -6 Locked Synthesizer 1 Integrated RMS phase noise 100 Hz to 1 MHz RRS LO1 Reference Spur Rejection RFS Fractional Spur Rejection LO1 MHz MHz/V MHz 0 –100 dBm dBc/Hz –105 Measured into 100-Ω differential load at the LO1OP/N port Locked with loop bandwidth set to 400 kHz nominal φLD LO1 -3 UNIT dBc/Hz –100 0.5 1 deg Measured into a 100-Ω differential load at the LO1OP/N port –50 dBc Measured into a 100-Ω differential load at the LO1OP/N port –45 dBc R N x LO1, N: Harmonic Rejection 2,3,4… Measured into a 100-Ω differential load at the LO1OP/N port RLO Output Return Loss Measured into a 100-Ω differential load at the LO1OP/N port over all input power levels. ZO Output Impedance Differential mode at LO1OP/N port 100 Ω PextVCO Ext VCO input Differential mode –13 dBm RLextVCO Ext VCO Port Input Return Loss Differential mode –13 dB ZI Ext VCO port input impedance 100 Ω extVCO –11 Differential mode –20 dBc –16 dB SYNTHESIZER #2 (UHF-BAND PLL) ELECTRICAL CHARACTERISTICS SYNTHESIZER #2 SIGNAL CHARACTERISTICS PARAMETER fRef Reference Frequency fLO2 Frequency φFR TEST CONDITIONS MIN See Table 4 TYP MAX 18 325 UNIT MHz 460 MHz Free running VCO2 SSB Phase Noise at 100 kHz –115 dBc/Hz φLD LO2 Locked Synthesizer 2 SSB Phase Noise at 10 kHz –115 dBc/Hz φLD LO2 Locked Synthesizer 2 SSB Phase Noise at100 kHz –115 dBc/Hz VCO2 5 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 SYNTHESIZER #2 (UHF-BAND PLL) ELECTRICAL CHARACTERISTICS (continued) SYNTHESIZER #2 SIGNAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP φLD LO2 Locked Synthesizer 2 Integrated RMS Phase noise 100 Hz to 1MHz MSLO2 Tuning Sensitivity For VLO2TUN≥ 2 V ∆fLO2 Step Size For 18-MHz reference input RRS LO1 Reference Sideband Rejection –65 LO1 Fractional Spurs Rejection –65 RFS 40 MAX UNIT 0.2 deg 80 MHz/V 125 kHz -60 dBc –60 dBc MAX UNIT INPUT REFERENCE REQUIREMENTS PARAMETER fRef TEST CONDITIONS Customer Requirement Reference Source Input Level (1) HCMOS Output Reference Input Symmetry Waveform Duty Cycle τFR Waveform Pulse Rise Time 10% to 90% of max voltage transition φFR SSB Phase Noise at 10 kHz VFR TYP 18 Temperature Stability (1) MIN Reference Frequency 4 4.5 40% MHz 5 Vpp 60% 1 4 –153 –150 nsec dBc/Hz Note that for source peak-to-peak voltage of less than 4 V and dc component other than 2.5-V degradation of the close-in phase noise may occur. For oscillators with no dc component, a dc voltage may be applied using a voltage divider (see the schematic). AC TIMING, SERIAL BUS INTERFACE SERIAL INTERFACE TIMING CHARACTERISTICS (see Figure 9) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CDI Clock to Data Invalid 10 ns DVC Data Valid to Clock 10 ns CPWH Clock Pulse Width High 50 ns CPWL Clock Pulse Width Low 50 ns CEL Clock to Enable Low 10 ns ELC Enable Low to Clock 10 ns EPWH Enable Pulse Width 10 ns DIGITAL INTERFACE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input High Voltage 2.1 5.0 V VIL Input Low Voltage 0 0.8 V IIH Input High Current 0 50 µA IIL Input Low Current 0 –50 µA CI Input Capacitance VOH Output Logic 1 Voltage ROH Output Logic 1 Impedance VOL Output Low Voltage 6 3 0 to 100-µA load 2.4 pF 3.6 18 0 to -100-µA load 0 V kΩ 0.4 V TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 AUXILIARY, AGC, AND CONTROL FUNCTIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVCOenbl External VCO Enable Voltage CMOS compatible Input. See the Synthesizer #1 (S-Band PLL) Characteristics table. V VLD1 Lock Detect Voltage (PLL1) CMOS compatible Output (active high). See the Synthesizer #1 (S-Band PLL) Characteristics table. V VLD2 Lock Detect Voltage (PLL2) CMOS compatible Output (active high). See the Synthesizer #1 (S-Band PLL) Characteristics table. V VAGCI Gain Control Input VAGCO Gain Control Output When loaded with 10-kΩ load. Output impedance of AGCO is 3.75 kΩ. Texas Instruments RF ASICs present a 10-kΩ load impedance. AAGC2 VAGCO Accuracy VAGCO vs VAGCI characteristic ±100 mV VDET Detector Output Voltage TBD mV AVDET Detector Accuracy TBD mV VBGR Band-Gap Reference Voltage 1.17 V tRBB AGC Time Constant EXTLOIP EXTLOIN Set by external loop filter 3 V 0 1.5 V µs TBD On-chip VCO1 selection Logic level applied to EXTLOIP and EXTLOIN pins to select the on-chip VCO High Logic Level applied to EXTLOIP and EXTLOIN pins to select the off-chip (external) VCO. Low Off-chip VCO1 selection EXTLOIP EXTLOIN 0 High Low The VAGCO vs VAGCI is the voltage-transfer-function as defined by Table 1 when the AGCO is loaded with 10 kΩ. Note: The RFAGC pin on Texas Instruments RF downconverters (such as: TRF1111, TRF1115, or TRF1216) have an internal load of 10 kΩ and consequently the user should not add a separate 10-kΩ load resistor. Table 1. AGCO Voltage vs AGCI Voltage VAGCI V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 >0.6 VAGCO V 1.5 1.2 0.85 0.55 0.2 0.0 0.0 0.0 FREQUENCY PLAN The TRF1112 / TRF1212 allow a variety of frequency plans. Figure 2 illustrates the allowable combinations of first and second IFs. However, due to the fact that the chips feature image-reject mixers, significant changes in the frequency plan can result in degradation of image rejection. This phenomenon is captured in Figure 3. In order to maintain maximum image rejection and LO suppression, a recommended frequency plan is: RxIF1 = 480 MHz, RxIF2 = 43.75 MHz. 7 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 100 90 80 IF2 (MHz) 70 60 50 480 / 44 40 426 / 36 30 20 10 0 300 350 400 450 500 550 600 IF1 (MHz) Figure 2. Potential Receive IF Combinations 0 T=25oC, LO2=436.25 MHz IF1 to IF2 Image Rejection −5 −10 Image Rejection (dBc) −15 −20 −25 −30 −35 −40 −45 −50 10 20 30 40 50 60 70 80 90 IF2 Frequency (MHz) Figure 3. Image Rejection vs IF2 RECEIVE GAIN CONTROL The TRF1112 / TRF1212 offers two methods for gain control. Gain can be adjusted via an external analog signal (0-3 V) or by using the on-chip detector, voltage reference and operational amplifier. The gain-response curve is shown in Figure 4 and is designed to be monotonic for a 0-V to 3-V input analog voltage. This voltage control (AGCI) can be used to keep a constant peak-to-peak differential voltage output from 8 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 the TRF1112 / TRF1212 to the baseband processor’s ADC over a large input signal dynamic range. The recommended TRF1112 / TRF1212 differential output level is 1.2 Vpp. The ASIC AGC output pin (AGCO) can be used to control the gain of a front-end downconverter for improved system dynamic range. In order to minimize the receiver’s noise figure, the gain is changed in a stepped fashion. This means as the input signal level decreases, the gain shifts from the front-end stages to the back-end stages of the chip. This approach allows the noise figure to remain low until large input signals are present. Closed-Loop AGC In order to achieve very fast signal acquisition in applications such as burst-mode transmission, Texas Instruments offers a receive gain control loop that requires no interaction from the demodulator. The internal loop operates by comparing the output of an internal peak detector to an internal voltage reference and adjusting the gain of the receive chain such that a constant voltage is achieved over a large input signal dynamic range. The internal AGC speed is set by an external AGC loop filter, the speed of which should be set low enough so that the AGC loop will not remove any carrier AM modulation. Careful attention to the ASIC architecture enables excellent 3rd order intermodulation distortion (IMD) performance over the entire AGC range as shown in Figure 4 and Figure 5. In these figures, VREF refers to the reference voltage setting on the VREF pin which is used to set the output voltage swing when configured for internal AGC. Vout is the output voltage swing at IF2 given in Vpp differential or rms. 0 T=25 oC Vout=2.0 Vppdiff, 680mV rms, VREF=0.621 V Vout=1.2 Vppdiff, 400mV rms, VREF=0.411 V Vout=0.6 Vppdiff, 190mV rms, VREF=0.254 V −10 IMD level (dBc) −20 −30 −40 −50 −60 −70 −60 −50 −40 −30 −20 −10 Input Power per Tone (dBm) Figure 4. IMD Level vs Input Power and AGC Output Setting (IF2 BPF Loss of 15 dB Included in Plot) 9 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 0 IMD level (dBc) −10 −20 −30 −40 −50 −40 ºC +25 ºC +85 ºC −60 −70 −60 −50 −40 −30 −20 −10 Input Power per Tone (dBm) Figure 5. IMD Level vs Temperature at Output AGC Setting of 1.2-Vpp Differential (IF2 Filter Loss of 15 dB Included) External Analog Control Receive signal gain control can also be accomplished through direct interaction with the modem. For example, the modem can look at several metrics on the incoming signal including voltage swing, SNR, and AGC error, then feedback an analog (0 V to 3 V) gain control signal to the Texas Instruments ASIC. Note that for applications requiring large channel bandwidths (e.g., 6 MHz) the maximum usable VAGCI should be limited to approximately 2 V to 2.5 V, otherwise the resulting gain produces excessive amounts of noise at the output. 10 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 100 50 90 80 40 70 35 60 30 50 25 40 20 30 15 Noise Figure 20 10 −40 ºC +25 ºC +85 ºC 10 0 Noise Figure (dB) GAIN (dB) Gain 5 0 0 0.5 1 1.5 2 2.5 AGC (V) Figure 6. TRF1112 / TRF1212 Gain vs AGCI Voltage (IF2 BPF Loss of 15 dB Included) Figure 7 shows the input third-order intercept point (IIP3) vs VAGCI for open loop AGC operation. As expected, the IIP3 decreases with increasing gain (increasing VAGCI). The input P-1dB behaves in a similar way. Figure 8 shows that the output P-1dB (OP-1dB) and output (OIP3) of the TRF1112 / TRF1212 is approximately constant vs the VAGCI voltage. 0.0 −10.0 −20.0 IIP3 (dBm) −30.0 −40.0 −50.0 −60.0 −70.0 −80.0 0.0 −40 ºC +25 ºC +85 ºC 0.5 1.0 1.5 2.0 2.5 AGCI (V) Figure 7. IIP3 vs AGCI Voltage and Temperature (IF2 BPF Loss of 15 dB Included) 11 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 30.0 25.0 OIP3 or OP−1dB (dBm) 20.0 15.0 OIP3 10.0 OP1dB 5.0 0.0 −5.0 −40 ºC +25 ºC +85 ºC −10.0 0.0 0.5 1.0 1.5 2.0 2.5 AGCI (V) Figure 8. OP-1dB and OIP3 vs AGCI Voltage and Temperature (IF2 BPF Loss of 15 dB Included) INTEGRATED SYNTHESIZERS PLL Programming A UHF and S-band PLL are integrated in the TRF1112 / TRF1212. These two PLLs can be programmed via a 3-wire serial bus (CLK, DATA, and EN) from the baseband processor. The timing specs are given in the AC Timing table and detailed in Figure 9. Figure 10details the addresses and register values required to fully program the synthesizers. CDI Data A[7]=MSB DVC A[6] A[5] CEL A[4] D[1] D[0] LSB Clock EN ELC CPWH CPWL EPWH NOTE: If left unconnected, the DATA, CLK and EN pins rest on logic High. Figure 9. Serial Interface Timing Diagram Data is written to the PLLs according to the following format: 12 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 MSB Byte 1 LSB MSB Byte 2 LSB Address MSB Byte 3 LSB Data A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[15] D[14] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 D[13] D[12] D[11] D[10] D[9] D[8] Synth #1 N divider Synth #2 N divider 0 0 0 0 D[7] D[6] D[5] D[4] Synth #1 S counter PS 0 0 0 D[2] D[1] D[0] Synth #1 F divider Synth #2 S counter FS D[3] Synth #2 F divider 0 0 0 0 0 all other addresses reserved for future expansion Figure 10. Serial Interface Data Format The first eight bits are the appropriate address for the instruction set and the remaining 16 bits are the instructions. The data is 24 bits long (3 bytes). Byte 1 is the address with A[7] being the MSB and A[0] being the LSB. Byte 2 and 3 program the IC with synthesizer information and PS (polarity select bit) information. D[15] is the MSB and D[8] the LSB. The PS bit selects which edge of the reference is used for frequency comparison. Improved spurious and phase noise is achieved by selected the edge with the fastest rise or fall time. If PS = 1, the rising edge is used as the reference. If PS = 0, the falling edge is used. The filter select (FS) bit selects which receive filter path is enabled. If FS = 1, the A filter path is selected, if FS = 0 the B filter path is selected. This feature allows the user to control the receive signal bandwidth. Each of the three lines in Figure 10 needs to be sent to the TRF1112 /TRF1212 to fully program the synthesizers, the FS bit, and the PS bit. Once the synthesizers and the FS/PS bits are fully programmed, the clock signal should be turned off to eliminate any clock-associated spurious signals The UHF oscillator (LO2) frequency of oscillation is set by the following equation:   Fout  REFIN
8
(N  3)  S  F 8 18 (1) The S-band oscillator (LO1) frequency of oscillation is set by the following equation:   Fout  REFIN
8
(N  3)  S  F 18 (2) where F has a range of 0 to 17. Both N and S have ranges that are limited more by the LO range than by their digital count. Both synthesizers use a fractional architecture, which allows a high comparison frequency relative to the step size. The S-band PLL operates at a reference frequency of 18 MHz with a minimum phase accumulator frequency of 1 MHz. The UHF PLL operates at a 9-MHz reference with a minimum phase accumulator frequency of 0.5 MHz. The S-band PLL has a step size of 1 MHz and the UHF PLL has a step size of 125 kHz, when using an 18-MHz reference frequency. Different reference frequencies yield different step sizes, many of which are non-integer. If a different reference frequency is chosen, the step size is linearly related to the step size for 18 MHz. Step size = step size18MHz x [REF FREQ/18 MHz] In addition to normal reference spurious signals, fractional synthesizers have fractional spurs. The fractional spurs occur at an offset from the LO signal that is dependent on the difference between the LO frequency and integer multiples of the reference frequency. The spur locations can be found by the following process: divide the LO frequency by the reference frequency, take the remainder (fraction to the right of the whole number) and multiply by the reference frequency. This frequency is the difference between the actual LO frequency and an integer multiple of reference frequency. Fractional spurs will occur at this frequency and the reference frequency minus this frequency. An example will best explain the process: if LO1 is set to 2206 MHz and an 18-MHz reference frequency is used, then 2206/18 is 122.55556. The difference between the LO1 and 122 × 18 MHz is: 0.55556 x 18 MHz = 10 MHz The fractional spurs will occur at this frequency offset (10 MHz) from LO1 and: 18 MHz–10 MHz or 8 MHz from LO1. 13 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 The fractional spurious level varies with the offset from the LO since these spurious signals are attenuated by the loop filter response. The larger the offset from the LO, the lower the spur level. In general, spurs at offsets greater than 3 or 4 MHz are below –75 dBc and are not a concern. The worst fractional spurs levels occur when they are located at 1 MHz offset from the LO1 frequency. (Note: the fractional spur is offset from the LO1 frequency by 1 MHz when the difference between the LO1 and an integer multiple of the reference frequency is 1 or 17 MHz.) Although both synthesizers have fractional spurs, for most applications the spurious signals from the UHF (LO2) synthesizer can be ignored because these spurs are attenuated by frequency dividers that are placed after the LO2 generation. In some frequency plans it is possible to offset LO1 and LO2, in a complementary manner, to avoid worst-case fractional spurs (i.e., 1-MHz offsets) on LO1 synthesizer. VCO Tuning Characteristics The TRF1121 / TRF1221 internal VCOs have the following frequency vs tune voltage characteristics. 2500 700 2250 600 Frequency 500 1750 400 1500 300 Mod Sense 1250 200 −40 ºC +25 ºC +85 ºC 1000 100 1 1.5 2 2.5 3 3.5 4 4.5 Tuning Voltage (V) Figure 11. TRF1112 LO1 Frequency vs LO1TUN Voltage 14 5 Mod Sense (MHz/V) Frequency (MHz) 2000 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 500.0 140 450.0 120 Frequency 80 300.0 60 Mod Sense 250.0 40 Mod Sense (MHz/V) 100 350.0 −40 ºC +25 ºC +85 ºC 200.0 20 1 1.5 2 2.5 3 3.5 4 4.5 5 Tuning Voltage (V) Figure 12. TRF1112 LO2 Frequency vs LO2TUN Voltage 3750 900 3500 800 3250 700 3000 600 2750 500 2500 400 Mod Sense 2250 300 2000 Mod Sense (MHz/V) Frequency Frequency (MHz) Frequency (MHz) 400.0 200 −40 ºC +25 ºC +85 ºC 1750 100 1 1.5 2 2.5 3 3.5 4 4.5 5 Tuning Voltage (V) Figure 13. TRF1212 LO1 Frequency vs LO1TUN Voltage 15 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 500.0 140 450.0 120 Frequency 100 350.0 80 300.0 60 Mod Sense 250.0 Mod Sense (MHz/V) Frequency (MHz) 400.0 40 −40 ºC +25 ºC +85 ºC 200.0 20 1 1.5 2 2.5 3 3.5 4 4.5 5 Tuning Voltage (V) Figure 14. TRF1212 LO2 Frequency vs LO2TUN Voltage Phase Noise The TRF1112 / TRF1212 achieve superior phase noise performance with on-chip resonators and varactors. They are designed to meet the phase noise requirements of both single carrier and multi-carrier systems. Due to chip architecture, the phase noise and spurious performance of the LO2 (UHF) PLL is about 15 dB better than the LO1 (S-band) PLL. The typical phase noise of the TRF1112 and TRF1212 S-Band PLL (LO1) with the PLL locked is shown in Figure 15 and Figure 16, respectively. The phase noise of the TRF1212 S-Band PLL at the min and max range are shown in Figure 17 and Figure 18 respectively. These plots were taken at room temperature and typical voltage conditions. 16 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 Figure 15. Phase Noise of TRF1112 Synthesizer #1 – Typical Performance is 0.4 RMS (100 Hz to 1 MHz) Figure 16. Phase Noise of the TRF1212 Synthesizer #1 – Typical Performance is 0.6 RMS (100 Hz to 1 MHz) 17 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 Figure 17. TRF1212 S-Band Synthesizer Phase Noise - 2818 MHz 18 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 Figure 18. TRF1212 S-Band Synthesizer Phase Noise - 3418 MHz For applications demanding tighter phase noise performance than that offered by Texas Instruments internal VCOs, a provision exists for connection of an external VCO. Texas Instruments integrated PLL locks the external VCO to the reference frequency and the chip provides an external tuning voltage that drives the VCO. OUTPUT A/D INTERFACE The output of the baseband amplifier is designed to directly drive typical A/D inputs. The output IF2 buffer amplifiers are low impedance emitter followers as shown in Figure 19. 19 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 +Vcc differential 500
ll 10pF at 44MHz BBOUT N 3mA 3mA TRF1112 or TRF1212 Optional load resistors can be used to increase peak current drive. Cp Cp Figure 19. Output Interface for TRF1112 / TRF1212 The peak current drive of the output transistors is 3 mA. Assuming a 1.2-Vpp differential (0.6 V single ended) voltage swing, the minimum impedance the TRF1112 / TRF1212 drives without clipping is 0.6 V/3 mA = 200 Ω, single-ended. In practice the impedance must be higher to prevent distortion products from degrading BER of the receiver. This impedance must include the A/D input capacitance and any parasitic board capacitance. At 44 MHz, the TRF1112 / TRF1212 drives a differential impedance of 1000 Ω (single ended impedance of 500 Ω) with up to a 10-pF capacitive load (293-Ω single-ended impedance) and maintain 38-dBc imtermodulation products with 64 QAM modulation. Proper attention to layout and reduction of parasitic capacitance at this interface is critical to avoid linearity degradation. At higher IF frequencies parasitic capacitance is even more critical. If parasitic capacitance is loading the output and degrading intermodulation performance there are two approaches to solve the problem. First a shunt inductor can be added to resonate the capacitance. The inductor value would be determined by: L = 1/ω2Cp, where Cp is the parasitic capacitance and ω is 2π times the baseband receive IF frequency. Frequently this inductor can be part of the bias network for the ADC. Second, the peak output current drive can be increased by adding a shunt resistor across the output of each baseband output. This resistor will essentially increase the quiescent current through the output transistor thus allowing a higher peak output current. The maximum increase in quiescent current is 3 mA resulting in a maximum allowable peak current of 6 mA. If load resistors are added, their resistance must be included to calculate total load impedance for the TRF1112 / TRF1212. 20 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 APPLICATION INFORMATION TRF1112/TRF1212 A typical application schematic is shown in Figure 20 and a mechanical drawing of the package outline (LPCC Quad 7 mm × 7 mm, 48-pin) is shown in Figure 21. Figure 20. Recommended TRF1112/TRF1212 Application Schematic 21 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 APPLICATION INFORMATION (continued) Figure 21. Package Drawing The recommended PCB Layout mask is shown in Figure 22, along with recommendations on the board material (see Table 2) and construction (see Figure 23). Table 2. PCB Recommendations Board Material Board Material Core Thickness Copper Thickness (starting) 1 oz Prepreg Thickness 8 mil Recommended Number of Layers Via Plating Thickness Final Plate Final Board Thickness 22 FR4 10 mil 4 ½ oz White immersion tin 33–37 mil TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 5.50 0.50 TYP 0.60 TYP 0.45 TYP PIN 1 1.27 TYP 5.50 1.27 TYP 5.30 DIA 0.38 TYP 0.25 TYP 5.30 SOLDER MASK: NO SOLDERMASK UNDER CHIP, ON LEAD PADS OR ON GROUND CONNECTIONS. 16 VIA HOLES, EACH 0.38 mm. DIMENSIONS in mm Figure 22. Recommended Pad Layout 23 TRF1112 TRF1212 www.ti.com SLWS175A – APRIL 2005 – REVISED DECEMBER 2005 Figure 23. PCB Via Cross Section 24 PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) PTRF1212IRGZR NRND VQFN RGZ 48 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1212 TRF1112IRGZR NRND VQFN RGZ 48 TBD Call TI Call TI -40 to 85 TRF 1112 TRF1112IRGZRG3 NRND VQFN RGZ 48 TBD Call TI Call TI -40 to 85 TRF 1112 TRF1112IRGZT NRND VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1112 TRF1112IRGZTG3 NRND VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1112 TRF1212IRGZR NRND VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1212 TRF1212IRGZRG3 NRND VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1212 TRF1212IRGZT NRND VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1212 TRF1212IRGZTG3 NRND VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 TRF 1212 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TRF1112IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TRF1212IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TRF1212IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRF1112IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 TRF1212IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 TRF1212IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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