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REF1925, REF1930, REF1933, REF1941
SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
REF19xx Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References
1 Features
3 Description
•
Applications with only a positive supply voltage often
require an additional stable voltage in the middle of
the analog-to-digital converter (ADC) input range to
bias input bipolar signals. The REF19xx provides a
reference voltage (VREF) for the ADC and a second
highly-accurate voltage (VBIAS) that can be used to
bias the input bipolar signals.
1
•
•
•
•
•
•
•
•
•
Two Outputs, VREF and VREF / 2, for Convenient
Use in Single-Supply Systems
Excellent Temperature Drift Performance:
– 25 ppm/°C (max) from –40°C to 125°C
High Initial Accuracy: ±0.1% (max)
VREF and VBIAS Tracking over Temperature:
– 6 ppm/°C (max) from –40°C to 85°C
– 7 ppm/°C (max) from –40°C to 125°C
Microsize Package: SOT23-5
Low Dropout Voltage: 10 mV
High Output Current: ±20 mA
Low Quiescent Current: 360 μA
Line Regulation: 3 ppm/V
Load Regulation: 8 ppm/mA
2 Applications
•
•
•
•
•
•
Digital Signal Processing:
– Power Inverters
– Motor Controls
Current Sensing
Industrial Process Controls
Medical Equipment
Data Acquisition Systems
Single-Supply Systems
The REF19xx offers excellent temperature drift
(25 ppm/°C, max) and initial accuracy (0.1%) on both
the VREF and VBIAS outputs while operating at a
quiescent current less than 430 µA. In addition, the
VREF and VBIAS outputs track each other with a
precision of 6 ppm/°C (max) across the temperature
range of –40°C to 85°C. All these features increase
the precision of the signal chain and decrease board
space, while reducing the cost of the system as
compared to a discrete solution. Extremely low
dropout voltage of only 10 mV allows operation from
very low input voltages, which can be very useful in
battery-operated systems.
Both the VREF and VBIAS voltages have the same
excellent specifications and can sink and source
current equally well. Very good long-term stability and
low noise levels make these devices ideally-suited for
high-precision industrial applications.
Device Information(1)
PART NAME
REF19xx
PACKAGE
BODY SIZE (NOM)
SOT (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
Application Example
Power
Supply
INA213
ISENSE
VOUT
ADC
REF
VIN-
VREF
3.0 V
VBIAS
0.02
0.01
0
-0.01
-0.02
VREF
-0.03
-0.05
±75
±50
±25
0
25
50
75
Temperature (ƒC)
REF1930
EN
0.03
-0.04
VBIAS
1.5 V
GND
Output Voltage Accuracy (%)
LOAD
0.04
VIN+
RSHUNT
VREF and VBIAS vs Temperature
0.05
100
125
150
C001
VIN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF1925, REF1930, REF1933, REF1941
SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 12
8.1 Solder Heat Shift..................................................... 12
8.2 Thermal Hysteresis ................................................. 13
8.3 Noise Performance ................................................. 14
9
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 16
10 Applications and Implementation...................... 17
10.1 Application Information.......................................... 17
10.2 Typical Application ................................................ 17
11 Power-Supply Recommendations ..................... 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 23
13 Device and Documentation Support ................. 24
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
24
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2014) to Revision A
Page
•
Changed Input to Output in I/O column of pin 1 row in Pin Functions table ......................................................................... 3
•
Added Storage temperature parameter to Absolute Maximum Ratings table (moved from ESD Ratings table)................... 4
•
Changed ESD Ratings table: changed title and updated table format .................................................................................. 4
2
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SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
5 Device Comparison Table
PRODUCT
VREF
VBIAS
REF1925
2.5 V
1.25 V
REF1930
3.0 V
1.5 V
REF1933
3.3 V
1.65 V
REF1941
4.096 V
2.048 V
6 Pin Configuration and Functions
DDC Package
SOT23-5
(Top View)
VBIAS
1
GND
2
EN
3
5
VREF
4
VIN
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
VBIAS
2
GND
—
3
EN
Input
Enable (EN ≥ VIN – 0.7 V, device enabled)
4
VIN
Input
Input supply voltage
5
VREF
Output
Output
Copyright © 2014–2017, Texas Instruments Incorporated
Bias voltage output (VREF / 2)
Ground
Reference voltage output (VREF)
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Temperature
MIN
MAX
VIN
–0.3
6
EN
–0.3
VIN + 0.3
Operating
–55
150
Junction, TJ
V
150
Storage, Tstg
(1)
UNIT
–65
°C
170
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
(1)
Supply input voltage range (IL = 0 mA, TA = 25°C)
NOM
MAX
VREF + 0.02 (1)
5.5
UNIT
V
See Figure 24 in the Typical Characteristics section for the minimum input voltage at different load currents and temperature.
7.4 Thermal Information
REF19xx
THERMAL METRIC (1)
DDC (SOT23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
193.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.2
°C/W
RθJB
Junction-to-board thermal resistance
34.5
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
34.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5
SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
Electrical Characteristics
At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy
–0.1%
Output voltage temperature coefficient (1)
0.1%
–40°C ≤ TA ≤ 125°C
±10
±25
–40°C ≤ TA ≤ 85°C
±1.5
±6
±2
±7
VREF + 0.02 V ≤ VIN ≤ 5.5 V
3
35
Sourcing
0 mA ≤ IL ≤ 20 mA ,
VREF + 0.6 V ≤ VIN ≤ 5.5 V
8
20
Sinking
0 mA ≤ IL ≤ –20 mA,
VREF + 0.02 V ≤ VIN ≤ 5.5 V
8
20
360
430
VREF and VBIAS tracking over temperature (2)
–40°C ≤ TA ≤ 125°C
ppm/°C
ppm/°C
LINE AND LOAD REGULATION
ΔVO(ΔVI)
ΔVO(ΔIL)
Line regulation
Load regulation
ppm/V
ppm/mA
POWER SUPPLY
Active mode
ICC
Supply current
Shutdown mode
–40°C ≤ TA ≤ 125°C
460
3.3
–40°C ≤ TA ≤ 125°C
9
Device in shutdown mode (EN = 0)
Enable voltage
Device in active mode (EN = 1)
0
0.7
VIN – 0.7
VIN
10
Dropout voltage
IL = 20 mA
ISC
Short-circuit current
ton
Turn-on time
0.1% settling, CL = 1 µF
Low-frequency noise (3)
0.1 Hz ≤ f ≤ 10 Hz
Output voltage noise density
f = 100 Hz
µA
5
V
20
mV
600
50
mA
500
µs
NOISE
12
ppmPP
0.25
ppm/√Hz
CAPACITIVE LOAD
Stable output capacitor range
0
10
µF
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
0 to 1000 hours
Output voltage hysteresis (4)
(1)
(2)
(3)
(4)
25°C, –40°C, 125°C, 25°C
60
Cycle 1
60
Cycle 2
35
ppm
ppm
Temperature drift is specified according to the box method. See the Feature Description section for more details.
The VREF and VBIAS tracking over temperature specification is explained in more detail in the Feature Description section.
The peak-to-peak noise measurement procedure is explained in more detail in the Noise Performance section.
The thermal hysteresis measurement procedure is explained in more detail in the Thermal Hysteresis section.
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7.6 Typical Characteristics
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
60
40
50
Population (%)
Population (%)
30
20
40
30
20
10
0
80
60
40
20
0
±20
±40
±60
±80
0
±100
10
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/ƒC)
VREF and VBIAS Matching (ppm)
C016
C004
–40°C ≤ TA ≤ 85°C
Figure 2. Distribution of VREF – 2 × VBIAS Drift Tracking
Over Temperature
Figure 1. VREF – 2 × VBIAS Distribution
50
60
40
40
Population (%)
Population (%)
50
30
20
20
10
10
0
30
0
1
2
3
4
5
6
0
7
-0.0125 -0.01 -0.0075 -0.005 -0.0025
VREF and VBIAS Tracking Over Temperature (ppm/ƒC)
0
0.0025
Solder Heat Shift Histogram - VREF (%)
C041
C017
–40°C ≤ TA ≤ 125°C
Refer to the Solder Heat Shift section for more information.
Figure 3. Distribution of VREF – 2 × VBIAS Drift Tracking
Over Temperature
Figure 4. Solder Heat Shift Distribution (VREF)
60
0.05
0.04
Output Voltage Accuracy (%)
Population (%)
50
40
30
20
10
0.03
VBIAS
0.02
0.01
0
-0.01
-0.02
VREF
-0.03
-0.04
0
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
-0.05
±75
±50
±25
0
Solder Heat Shift Histogram - VBIAS (%)
25
50
75
Temperature (ƒC)
100
125
150
C001
C040
Refer to the Solder Heat Shift section for more information.
Figure 5. Solder Heat Shift Distribution (VBIAS)
6
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Figure 6. Output Voltage Accuracy (VREF) vs Temperature
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SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
1000
2.5005
-40°C
2.5000
500
250
VREF (V)
VREF - 2 x VBIAS (ppm)
750
0
±250
2.4995
25°C
2.4990
125°C
±500
2.4985
±750
±1000
2.4980
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±20
±15
±10
±5
C003
0
5
10
Load Current (mA)
15
20
C038
VREF output
1.2503
-40°C
VBIAS (V)
1.2501
1.2499
1.2497
25°C
125°C
1.2495
1.2493
±20
±15
±10
0
±5
5
10
15
Load Current (mA)
20
Figure 8. Output Voltage Change vs Load Current (VREF)
VREF - Load Regulation Sourcing (ppm/mA)
Figure 7. VREF – 2 × VBIAS Tracking vs Temperature
11
10
9
8
7
6
5
4
0
25
50
75
Temperature (ƒC)
VBIAS output
9
8
7
6
5
4
±75
±50
±25
100
125
150
Figure 11. Load Regulation Sourcing vs Temperature (VBIAS)
25
50
75
100
125
150
C025
IL = 20 mA
Figure 10. Load Regulation Sourcing vs Temperature (VREF)
12
11
10
9
8
7
6
5
4
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C020
IL = 20 mA
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0
Temperature (ƒC)
VREF - Load Regulation Sinking (ppm/mA)
VBIAS - Load Regulation Sourcing (ppm/mA)
12
±25
10
VREF output
Figure 9. Output Voltage Change vs Load Current (VBIAS)
±50
11
C039
VBIAS output
±75
12
VREF output
150
C021
IL = –20 mA
Figure 12. Load Regulation Sinking vs Temperature (VREF)
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Typical Characteristics (continued)
5
12
11
VREF Line Regulation (ppm/V)
VBIAS - Load Regulation Sinking (ppm/mA)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
10
9
8
7
6
5
4
3.5
3
2.5
2
4
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
VBIAS output
±75
150
±50
±25
0
25
50
75
100
Temperature (ƒC)
C022
IL = –20 mA
125
150
C019
VREF output
Figure 13. Load Regulation Sinking vs Temperature (VBIAS)
Figure 14. Line Regulation vs Temperature (VREF)
5
100
4.5
VBIAS
80
4
PSRR (dB)
VBIAS Line Regulation (ppm/V)
4.5
3.5
VREF
60
3
40
2.5
2
20
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
1
10
100
1k
10k
Frequency (Hz)
C018
VBIAS output
100k
C026
CL = 0 µF
Figure 15. Line Regulation vs Temperature (VBIAS)
Figure 16. Power-Supply Rejection Ratio vs Frequency
100
VIN + 0.25 V
VBIAS
500 mV/div
PSRR (dB)
80
VIN + 0.25 V
VIN - 0.25 V
VREF
VREF
40 mV/div
60
40
20
1
10
100
1k
Frequency (Hz)
10k
C027
CL = 10 µF
Figure 17. Power-Supply Rejection Ratio vs Frequency
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Time (500 µs/div)
100k
C006
CL = 1 µF
Figure 18. Line Transient Response
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SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
VIN + 0.25 V
500 mV/div
VIN + 0.25V
+1 mA
VIN - 0.25V
+1 mA
2 mA/div
- 1 mA
VREF
40 mV/div
VREF
20 mV/div
Time (500 µs/div)
Time (500 µs/div)
C006
CL = 10 µF
C032
CL = 1 µF
Figure 19. Line Transient Response
Figure 20. Load Transient Response
+20 mA
+20 mA
+1 mA
+1 mA
IL = ±1-mA step
40 mA/div
2 mA/div
-20 mA
- 1 mA
VREF
VREF
20 mV/div
40 mV/div
Time (500 µs/div)
Time (500 µs/div)
C037
CL = 10 µF
C031
IL = ±1-mA step
CL = 1 µF
Figure 21. Load Transient Response
IL = ±20-mA step
Figure 22. Load Transient Response
400
125°C
Dropout Voltage (mV)
+20 mA
+20 mA
40 mA/div
-20 mA
VREF
40 mV/div
25°C
±40°C
200
100
0
Time (500 µs/div)
±30
C036
CL = 10 µF
300
±20
±10
0
10
20
Load Current (mA)
30
C005
IL = ±20-mA step
Figure 23. Load Transient Response
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Figure 24. Minimum Dropout Voltage vs Load Current
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Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
VIN
VIN
2 V/div
2 V/div
VREF
VREF
Time (100 µs/div)
Time (100 µs/div)
C033
C034
CL = 1 µF
CL = 10 µF
Figure 26. Turn-On Settling Time
500
500
450
450
Quiescent Current ( A)
Quiescent Current ( A)
Figure 25. Turn-On Settling Time
400
350
300
400
350
300
250
250
200
200
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
2
3
4
5
Input Voltage (V)
C006
Voltage (5 V/div)
Figure 28. Quiescent Current vs Input Voltage
Voltage (5 V/div)
Figure 27. Quiescent Current vs Temperature
Time (1 s/div)
Time (1 s/div)
C028
VREF output
Figure 29. 0.1-Hz to 10-Hz Noise (VREF)
10
6
C007
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C029
VBIAS output
Figure 30. 0.1-Hz to 10-Hz Noise (VBIAS)
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SBOS697A – SEPTEMBER 2014 – REVISED JANUARY 2017
Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
100
CL = 0 F
Output Impedance ( )
2XWSXW 1RLVH 6SHFWUDO 'HQVLW\ SSP ¥+]
1
CL = 0 µF
0.1
CL = 4.7 F
10
CL = 1µF
1
CL = 10 F
0.1
CL = 10 µF
0.01
1
10
100
1k
0.01
0.01
10k
Frequency (Hz)
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
C030
C024
VREF output
Figure 31. Output Voltage Noise Spectrum
Figure 32. Output Impedance vs Frequency (VREF)
100
40
35
30
10
Population (%)
Output Impedance ( )
CL = 0 F
CL = 1µF
1
CL = 10 F
25
20
15
10
0.1
100
1k
10k
80
60
100k
Frequency (Hz)
120
10
100
1
40
0
0.1
20
0.01
0.01
0
5
Thermal Hysterisis - VREF (ppm)
C023
C013
VBIAS output
Figure 33. Output Impedance vs Frequency (VBIAS)
Figure 34. Thermal Hysteresis Distribution (VREF)
40
35
Population (%)
30
25
20
15
10
120
100
80
60
40
20
0
0
5
Thermal Hysteresis - VBIAS (ppm)
C014
Figure 35. Thermal Hysteresis Distribution (VBIAS)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF19xx have differing coefficients of thermal expansion, resulting
in stress on the device die when the device is heated. Mechanical and thermal stress on the device die can
cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is
a common cause of this error.
In order to illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on
each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow
profile. The reflow profile is as shown in Figure 36. The PCB is comprised of FR4 material. The board thickness
is 1.57 mm and the area is 171.54 mm × 165.1 mm.
300
Temperature (ƒC)
250
200
150
100
50
0
0
50
100
150
200
250
300
Time (seconds)
350
400
C01
Figure 36. Reflow Profile
The reference and bias output voltages are measured before and after the reflow process; the typical shift is
displayed in Figure 37 and Figure 38. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are
also possible depending on the size, thickness, and material of the PCB. An important note is that the histograms
display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on
PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the
PCB is exposed to multiple reflows, solder the device in the second pass to minimize device exposure to thermal
stress.
60
50
50
Population (%)
Population (%)
40
30
20
10
0
40
30
20
10
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
Solder Heat Shift Histogram - VREF (%)
0
-0.0125 -0.01 -0.0075 -0.005 -0.0025
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0.0025
C040
C041
Figure 37. Solder Heat Shift Distribution, VREF (%)
12
0
Solder Heat Shift Histogram - VBIAS (%)
Figure 38. Solder Heat Shift Distribution, VBIAS (%)
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8.2 Thermal Hysteresis
Thermal hysteresis is measured with the REF19xx soldered to a PCB, similar to a real-world application. Thermal
hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling the
device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed by
Equation 1:
§ VPRE VPOST ·
6
VHYST
¨¨
¸¸ x 10 (ppm)
V
NOM
©
¹
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm),
VNOM = the specified output voltage,
VPRE = output voltage measured at 25°C pre-temperature cycling, and
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to 125°C and returns to 25°C.
(1)
40
35
35
30
30
120
100
120
0
100
0
80
5
60
5
40
10
20
10
80
15
60
15
20
40
20
25
20
25
0
Population (%)
40
0
Population (%)
Typical thermal hysteresis distribution is as shown in Figure 39 and Figure 40.
Thermal Hysteresis - VBIAS (ppm)
Thermal Hysterisis - VREF (ppm)
C013
Figure 39. Thermal Hysteresis Distribution (VREF)
Copyright © 2014–2017, Texas Instruments Incorporated
C014
Figure 40. Thermal Hysteresis Distribution (VBIAS)
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8.3 Noise Performance
Voltage (5 V/div)
Voltage (5 V/div)
Typical 0.1-Hz to 10-Hz voltage noise is shown in Figure 41 and Figure 42. Device noise increases with output
voltage and operating temperature. Additional filtering can be used to improve output noise levels, although care
must be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise
measurement setup is shown in Figure 43.
Time (1 s/div)
Time (1 s/div)
C028
C029
Figure 41. 0.1-Hz to 10-Hz Noise (VREF)
Figure 42. 0.1-Hz to 10-Hz Noise (VBIAS)
10 k
100
40 mF
VIN
To scope
VREF
REF19xx
0.1 F
GND
+
10 F
EN
1k
2-Pole High-pass
4-Pole Low-pass
0.1 Hz to 10 Hz Filter
VBIAS
Figure 43. 0.1-Hz to 10-Hz Noise Measurement Setup
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9 Detailed Description
9.1 Overview
The REF19xx is a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The Functional
Block Diagram section provides a block diagram of the basic band-gap topology and the two buffers used to
derive the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater
than that of Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature
coefficient and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2,
which has a negative temperature coefficient. The resulting band-gap output voltage is almost independent of
temperature. Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The
resistors R1, R2 and R3, R4 are sized such that VBIAS = VREF / 2.
e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS,
implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the
influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is
implemented in the REF19xx to minimize the temperature drift and maximize the initial accuracy of both the VREF
and VBIAS outputs.
9.2 Functional Block Diagram
R2
R6
R1
R7
+
VREF
+
e-Trim
R5
+
VBE1
-
+
R4
VBE2
-
R3
Q2
Q1
VBIAS
+
e-Trim
9.3 Feature Description
9.3.1 VREF and VBIAS Tracking
Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter
(ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF19xx are generated from
the same band-gap voltage as shown in the Functional Block Diagram section. Hence, both outputs track each
other over the full temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (max). The tracking
accuracy increases to 6 ppm/°C (max) when the temperature range is limited to –40°C to 85°C. The tracking
error is calculated using the box method, as described by Equation 2:
VDIFF(MAX) VDIFF (MIN)
§
·
6
Tracking Error
¨
¸ x 10 (ppm)
© VREF x Temperature Range ¹
where
•
VDIFF
VREF
2 ‡ VBIAS
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Feature Description (continued)
The tracking accuracy is as shown in Figure 44.
0.05
Output Voltage Accuracy (%)
0.04
0.03
VBIAS
0.02
0.01
0
-0.01
-0.02
VREF
-0.03
-0.04
-0.05
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C001
Figure 44. VREF and VBIAS Tracking vs Temperature
9.3.2 Low Temperature Drift
The REF19xx is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 3:
V REF(MAX) V REF(MIN)
§
·
6
Drift ¨
¸ x 10 (ppm)
x
V
Temperature
Range
© REF
¹
(3)
9.3.3 Load Current
The REF19xx family is specified to deliver a current load of ±20 mA per output. Both the VREF and VBIAS outputs
of the device are protected from short circuits by limiting the output short-circuit current to 50 mA. The device
temperature increases according to Equation 4:
TJ TA PD ‡ R -$
where
•
•
•
•
TJ = junction temperature (°C),
TA = ambient temperature (°C),
PD = power dissipated (W), and
RθJA = junction-to-ambient thermal resistance (°C/W).
(4)
The REF19xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
When the EN pin of the REF19xx is pulled high, the device is in active mode. The device must be in active mode
for normal operation. The REF19xx can be placed in a low-power mode by pulling the ENABLE pin low. When in
shutdown mode, the output of the device becomes high impedance and the quiescent current of the device
reduces to 5 µA in shutdown mode. See the Electrical Characteristics for logic high and logic low voltage levels.
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The low-drift, bidirectional, single-supply, low-side, current-sensing solution described in this section can
accurately detect load currents from –2.5 A to 2.5 A. The linear range of the output is from 250 mV to 2.75 V.
Positive current is represented by output voltages from 1.5 V to 2.75 V, whereas negative current is represented
by output voltages from 250 mV to 1.5 V. The difference amplifier is the INA213 current-shunt monitor, whose
supply and reference voltages are supplied by the low-drift REF1930.
10.2 Typical Application
REF19xx
VREF
+
VIN
Bandgap
EN
+
VCC
VBIAS
+
±
GND
REF
±ILOAD
VBUS
+
±
IN+
V+
VREF
+
RSHUNT
OUT
ADC
VOUT
INGND
INA213B
Figure 45. Low-Side, Current-Sensing Application
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Typical Application (continued)
10.2.1 Design Requirements
The design requirements are as follows:
1. Supply voltage: 5.0 V
2. Load current: ±2.5 A
3. Output: 250 mV to 2.75 V
4. Maximum shunt voltage: ±25 mV
10.2.2 Detailed Design Procedure
Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore, the currentsensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, use a differential
amplifier with a reference pin. This procedure allows for the differentiation between positive and negative
currents by biasing the output stage such that it can respond to negative input voltages. There are a variety of
methods for supplying power (V+) and the reference voltage (VREF, or VBIAS) to the differential amplifier. For a
low-drift solution, use a monolithic reference that supplies both power and the reference voltage. Figure 46
shows the general circuit topology for a low-drift, low-side, bidirectional, current-sensing solution. This topology is
particularly useful when interfacing with an ADC; see Figure 45. Not only do VREF and VBIAS track over
temperature, but their matching is much better than alternate topologies. For a more detailed version of the
design procedure, refer to TIDU357.
REF19xx
VREF
+
VIN
Bandgap
EN
+
VCC
VBIAS
+
±
GND
REF
±ILOAD
VBUS
+
±
IN+
± VSHUNT
V+
+
RSHUNT
OUT
VOUT
INGND
INA213B
Figure 46. Low-Drift, Low-side, Bidirectional, Current-Sensing Circuit Topology
The transfer function for the circuit given in Figure 46 is as shown in Equation 5:
VOUT G ‡ r VSHUNT
VBIAS
G ‡ rILOAD ‡ RSHUNT
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VBIAS
(5)
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Typical Application (continued)
10.2.2.1 Shunt Resistor
As illustrated in Figure 46, the value of VSHUNT is the ground potential for the system load. If the value of VSHUNT
is too large, issues may arise when interfacing with systems whose ground potential is actually 0 V. Also, a value
of VSHUNT that is too negative may violate the input common-mode voltage of the differential amplifier in addition
to potential interfacing issues. Therefore, limiting the voltage across the shunt resistor is important. Equation 6
can be used to calculate the maximum value of RSHUNT.
VSHUNT(max)
R SHUNT(max)
I LOAD(max)
(6)
Given that the maximum shunt voltage is ±25 mV and the load current range is ±2.5 A, the maximum shunt
resistance is calculated as shown in Equation 7.
VSHUNT (max) 25mV
R SHUNT (max)
10m:
I LOAD (max)
2.5A
(7)
To minimize errors over temperature, select a low-drift shunt resistor. To minimize offset error, select a shunt
resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.
10.2.2.2 Differential Amplifier
The differential amplifier used for this design must have the following features:
1. Single supply (3 V),
2. Reference voltage input,
3. Low initial input offset voltage (VOS),
4. Low-drift,
5. Fixed gain, and
6. Low-side sensing (input common-mode range below ground).
For this design, a current-shunt monitor (INA213) is used. The INA21x family topology is shown in Figure 47. The
INA213B specifications can be found in the INA213 product data sheet.
V+
IN-
OUT
IN+
+
REF
GND
Figure 47. INA21x Current-Shunt Monitor Topology
The INA213B is an excellent choice for this application because all the required features are included. In general,
instrumentation amplifiers (INAs) do not have the input common-mode swing to ground that is essential for this
application. In addition, INAs require external resistors to set their gain, which is not desirable for low-drift
applications. Difference amplifiers typically have larger input bias currents, which reduce solution accuracy at
small load currents. Difference amplifiers typically have a gain of 1 V/V. When the gain is adjustable, these
amplifiers use external resistors that are not conducive to low-drift applications.
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Typical Application (continued)
10.2.2.3 Voltage Reference
The voltage reference for this application must have the following features:
1. Dual output (3.0 V and 1.5 V),
2. Low drift, and
3. Low tracking errors between the two outputs.
For this design, the REF1930 is used. The REF19xx topology is as shown in the Functional Block Diagram
section.
The REF1930 is an excellent choice for this application because of its dual output. The temperature drift of
25 ppm/°C and initial accuracy of 0.1% make the errors resulting from the voltage reference minimal in this
application. In addition, there is minimal mismatch between the two outputs and both outputs track very well
across temperature, as shown in Figure 48 and Figure 49.
60
40
50
Population (%)
Population (%)
30
20
40
30
20
10
0
80
60
40
20
0
±20
±40
±60
±80
0
±100
10
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/ƒC)
VREF and VBIAS Matching (ppm)
C016
C004
Figure 48. VREF – 2 × VBIAS Distribution (At TA = 25°C)
Figure 49. Distribution of VREF – 2 × VBIAS Drift Tracking
Over Temperature
10.2.2.4 Results
Table 1 summarizes the measured results.
Table 1. Measured Results
UNCALIBRATED (%)
CALIBRATED (%)
Error across the full load current range (25°C)
ERROR
±0.0355
±0.004
Error across the full load current range (–40°C to 125°C)
±0.0522
±0.0606
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10.2.3 Application Curves
Performing a two-point calibration at 25°C removes the errors associated with offset voltage, gain error, and so
forth. Figure 50 to Figure 52 show the measured error at different conditions. For a more detailed description on
measurement procedure, calibration, and calculations, please refer to TIDU357.
3
800
Uncalibrated error (ppm)
Output Voltage (Vout)
-40°C
600
2.5
2
1.5
1
0.5
400
0°C
200
0
25°C
85°C
±200
±400
±600
0
125°C
±800
-3
-2
-1
0
1
2
Load current (mA)
3
±3
±2
±1
0
1
2
Load current (mA)
C00
Figure 50. Measured Transfer Function
3
C00
Figure 51. Uncalibrated Error vs Load Current
800
-40°C
Calibrated error (ppm)
600
400
0°C
200
0
25°C
85°C
±200
±400
±600
125°C
±800
±3
±2
±1
0
1
2
Load current (mA)
3
C00
Figure 52. Calibrated Error vs Load Current
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11 Power-Supply Recommendations
The REF19xx family of references feature an extremely low-dropout voltage. These references can be operated
with a supply of only 20 mV above the output voltage. For loaded reference conditions, a typical dropout voltage
versus load is shown in Figure 53. A supply bypass capacitor ranging between 0.1 µF to 10 µF is recommended.
400
Dropout Voltage (mV)
125°C
300
25°C
±40°C
200
100
0
±30
±20
±10
0
10
20
Load Current (mA)
30
C005
Figure 53. Dropout Voltage vs Load Current
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12 Layout
12.1 Layout Guidelines
Figure 54 shows an example of a PCB layout for a data acquisition system using the REF1930. Some key
considerations are:
• Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF1930.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise
pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible and only make perpendicular crossings when absolutely necessary.
INOUT
Analog Input
Via
to GND
Plane
V+
Via to
Input Power
C
GND
C
REF
VBIAS
C
GND
EN
REF19xx
IN+
INA213
12.2 Layout Example
REF
VREF
C
Microcontroller
A/D Input
C
VIN
DIG1
AIN
Figure 54. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt
Monitors (SBOS437)
• Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design (TIDU357)
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
REF1925
Click here
Click here
Click here
Click here
Click here
REF1930
Click here
Click here
Click here
Click here
Click here
REF1933
Click here
Click here
Click here
Click here
Click here
REF1941
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
e-Trim is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
REF1925AIDDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAGM
REF1925AIDDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAGM
REF1930AIDDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAHM
REF1930AIDDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAHM
REF1933AIDDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAIM
REF1933AIDDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAIM
REF1941AIDDCR
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAJM
REF1941AIDDCT
ACTIVE
SOT-23-THIN
DDC
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAJM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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