S4MF06607BSPZQQ1

TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com TMS470MF06607 16/32-Bit RISC Flash Microcontroller Check for Samples: TMS470MF06607 1 Features 1 • High-Performance Automotive Grade Microcontroller with Safety Features – Full Automotive Temperature Range – ECC on Flash and SRAM – CPU and Memory BIST (Built-In Self Test) • ARM Cortex™-M3 32-Bit RISC CPU – Efficient 1.2 DMIPS/MHz – Optimized Thumb2 Instruction Set – Memory Protection Unit (MPU) – Open Architecture With Third-Party Support – Built-In Debug Module • Operating Features – Up to 80MHz System Clock – Single 3.3V Supply Voltage • Integrated Memory – 640KB Total Program Flash with ECC – Support for Flash EEPROM Emulation – 64K-Byte Static RAM (SRAM) with ECC • Key Peripherals – High-End Timer, MibADC, CAN, MibSPI • Common TMS470M/570 Platform Architecture – Consistent Memory Map across the family – Real-Time Interrupt Timer (RTI) – Digital Watchdog – Vectored Interrupt Module (VIM) – Cyclic Redundancy Checker (CRC) • Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module – Oscillator and PLL clock monitor • Up to 51 Peripheral IO pins – 4 Dedicated GIO - w/ External Interrupts – Programmable External Clock (ECLK) • Communication Interfaces – Two CAN Controllers • One with 32 mailboxes, one with 16 • Parity on mailbox RAM – Two Multi-buffered Serial Peripheral Interface (MibSPI) • 12 total chip selects • 64 buffers with parity on each – Two UART (SCI) interfaces • H/W Support for Local Interconnect Network (LIN 2.1 master mode) • High-End Timer (HET) – Up to 18 Programmable I/O Channels – 64 Word Instruction RAM with parity • 10-Bit Multi-Buffered ADCs (MibADC) – Up to 16 ADC Input channels – 64 Result FIFO Buffer with parity – 1.55uS total conversion time – Calibration and Self Test features • On-Chip Scan-Base Emulation Logic – IEEE Standard 1149.1 (JTAG) Test-Access Port and Boundary Scan • Packages supported – 100-Pin Plastic Quad Flatpack (PZ Suffix) – Green/Lead-Free • Development Tools Available – Development Boards – Code Composer Studio™ Integrated Development Environment (IDE) – HET Assembler and Simulator – nowFlash™ Flash Programming Tool • Community Resources – TI E2E Community 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 HET[5] HET[4] VCCIOR VSS 54 53 52 51 HET[7] HET[6] 56 55 HET[9] HET[8] 58 57 HET[11] HET[10] 60 59 HET[13] HET[12] 62 61 HET[15] VCCIOR 65 HET[14] VSS 66 63 VCC 67 64 ADIN[0] ADEVT 69 68 ADIN[2] ADIN[1] 71 70 ADIN[4] ADIN[3] 72 ADIN[5] 74 73 ADIN[6] 75 PZ Package View ADIN[7] 76 50 HET[3] ADIN[8] 77 49 HET[2] ADIN[9] 78 48 TRST ADIN[10] 79 47 TMS ADIN[11] 80 46 TDI/HET[25] ADIN[12] 81 45 TDO/HET[24] ADREFHI 82 44 TCK ADREFLO 43 VSSAD 83 84 42 VCCIOR VSS VCCAD 85 41 VCC ADIN[13] 86 40 HET[1] ADIN[14] 87 39 HET[0] ADIN[15] 88 38 CAN2SRX PORRST 89 37 CAN2STX MIBSPIP2ENA 90 36 MIBSPI1SOMI ENZ 91 35 MIBSPI1SIMO VCC 92 34 MIBSPI1CLK VSS 93 33 MIBSPI1SCS[0] VCCIOR 94 32 MIBSPI1SCS[1] 24 25 LIN/SCI2TX LIN/SCI2RX 22 23 VSS LIN/SCI1TX 20 21 VCCIOR LIN/SCI1RX 18 19 MIBSPIP2SIMO MIBSPIP2CLK MIBSPIP2SOMI 16 17 GIOA[7]/INT[7] 14 15 13 VSS VCCIOR 12 VCC GIOA[6]/INT[6] 11 OSCOUT 9 10 VSS OSCIN MIBSPI1SCS[7] 7 26 8 MIBSPI1SCS[6] 100 VSS CAN1STX 27 CAN1SRX 99 5 MIBSPI1SCS[5] FLTP1 6 28 GIOA[4]/INT[4] 98 GIOA[5]/INT[5] MIBSPI1SCS[4] RST 4 29 MIBSPIP2SCS[3] 97 3 MIBSPI1SCS[3] TEST MIBSPIP2SCS[2] MIBSPI1SCS[2] 30 2 31 96 1 95 MIBSPIP2SCS[1] VCCP ECLK MIBSPIP2SCS[0] 1.1 www.ti.com Figure 1-1. TMS470MF06607 100-Pin PZ Package (Top View) 2 Features Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1.2 Description The TMS470MF06607 device is a member of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency ARM Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption. The TMS470MF06607 device contains the following: • • • • • • • • • • • • • • • • 16/32-Bit RISC CPU Core 640K-Byte Total Flash with SECDED ECC – 512K-Byte Program Flash – 128K- Byte Flash for additional program space or EEPROM Emulation 64K-Byte Static RAM (SRAM) with SECDED ECC Real-Time Interrupt Timer (RTI) Vectored Interrupt Module (VIM) Hardware built-in self-test (BIST) checkers for SRAM (MBIST) and CPU (LBIST) 64-bit Cyclic Redundancy Checker (CRC) Frequency-Modulated Zero-Pin Phase-Locked Loop (FMzPLL)-Based Clock Module With Prescaler Two Multi-buffered Serial Peripheral Interfaces (MibSPI) Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN) Two CAN Controller (DCAN) High-End Timer (HET) External Clock Prescale (ECP) Module One 16-Channel 10-Bit Multi-Buffered ADC (MibADC) Error Signaling Module (ESM) Four Dedicated General-Purpose I/O (GIO) Pins and 47 (2 of them are muxed with JTAG pins) Additional Peripheral I/Os (100-Pin Package) The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory. It is implemented with a 144-bit wide data word (128-bit without ECC) and a 64-bit wide flash module interface. The flash operates with a system clock frequency of up to 28 MHz. Pipeline mode, which allows linear prefetching of flash data, enables a system clock of up to 80 MHz. The enhanced real-time interrupt (RTI) module on the TMS470M devices has the option to be driven by the oscillator clock. The digital watchdog (DWD) is a 25-bit resetable decrementing counter that provides a system reset when the watchdog counter expires. The TMS470M devices have six communication interfaces: two LIN/SCIs, two DCANs and two MibSPIs. The LIN is the Local Interconnect Network standard and also supports an SCI mode. SCI can be used in a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The DCAN uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication Features Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 3 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or multiplexed wiring. The MibSPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The MibSPI provides the standard SOMI, SIMO, and SPI clock interface as well as up to eight chip select lines. The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The TMS470M HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. The TMS470M devices have one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be grouped by software for sequential conversion sequences. There are three separate groupings, all three of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. The frequency-modulated zero-pin phase-locked loop (FMzPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMzPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMzPLL provides the input to the global clock module (GCM). The GCM module subsequently provides system clock (HCLK), real-time interrupt clock (RTICLK), CPU clock (GCLK), HET clock (VCLK2), DCAN clock (AVCLK1), and peripheral interface clock (VCLK) to all other TMS470M device modules. The TMS470M devices also have an external clock prescaler (ECP) module that when enabled, outputs a continuous external clock (ECLK). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. An error signaling module (ESM) provides a common location within the device for error reporting allowing efficient error checking and identification. 4 Features Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1.3 Functional Block Diagram Figure 1-2 shows the functional block diagram of the TMS470M devices. TMS470MF0660x JTAG-DP ICEPICK Cortex™ M3 with MPU nVIC LBIST Boundary Scan M3VIM I TMS TCK TRST TDI TDO D SYS HET 64 Words w/Parity HET[15:0] ESM SYS BMM BMM LIN/SCI1 VCCP FLTP1 FLTP2 LIN/SCI2 Flash 512kB w/ECC RAM 64kB w/ECC PSA A2V MibSPI1 64 Words/ 16TGs w/Parity MBIST Flash 128kB w/ECC MibSPIP2 64 Words/ 8TGs w/Parity ADC 64 Words w/Parity PCR OSCIN1 OSCOUT1 VCCIOR ENZ OSC PLL CLK Monitor Flash RAM Wrapper Wrapper RTI/ DWD 1.5-V P-Ch VREG VCC Passgate1 VCC Passgate2 VCC Passgate3 VCC Passgate4 DCAN1 16 Mailboxes w/Parity CANS1RX CANS1TX DCAN2 32 Mailboxes w/Parity CANS2RX CANS2TX GIO VCCOUT RST PORRST TEST ECLK LIN/SCI1TX LIN/SCI1RX LIN/SCI2TX LIN/SCI2RX MIBSPI1SIMO MIBSPI1SOMI MIBSPI1CLK MIBSPI1SCS[7:0] MIBSPIP2SIMO MIBSPIP2SOMI MIBSPIP2CLK MIBSPIP2SCS[3:0] MIBSPIP2ENA ADIN[15:0] ADEVT VCCAD VSSAD ADREFHI ADREFLO GIOA[7:4]/INTA[7:4] Figure 1-2. TMS470M Functional Block Diagram Features Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 5 TMS470MF06607 SPNS157C – JANUARY 2012 1.4 www.ti.com Terms and Acronyms Table 1-1. Terms and Acronyms 6 Terms and Acronyms Description Comments A2V AHB to VBUSP Bridge The A2V bridge provides the memory interface between the proprietary TI VBUSP and the ARM AHB bus in the TMS470 platform devices. ADC Analog To Digital Converter AHB Advanced High-performance Bus Part of the M3 core BMM Bus Matrix Master The BMM provides connectivity between different bus slave modules to different bus master modules. Accesses from different master modules are executed in parallel if no resource conflict occurs or if the master modules are kept in series through arbitration CRC Cyclic Redundancy Check Controller DAP Debug Access Port DCAN Controller Area Network DWD Digital Watchdog ECC Error Correction Code DAP is an implementation of an ARM Debug Interface. ESM Error Signaling Module GIO General-Purpose Input/Output HET High-End Timer ICEPICK In Circuit Emulation TAP (Test Access Port) Selection Module ICEPick can connect or isolate a module level TAP to or from a higher level chip TAP. ICEPick was designed with both emulation and test requirements in mind. JTAG Joint Test Access Group IEEE Committee responsible for Test Access Ports JTAG-DP JTAG Debug Port JTAG-DP contains a debug port state machine (JTAG) that controls the JTAG-DP operation, including controlling the scan chain interface that provides the external physical interface to the JTAG-DP. It is based closely on the JTAG TAP State Machine, see IEEE Std 1149.1-2001. LBIST Logic Built-In Self Test Test the integrity of M3 CPU LIN Local Interconnect Network M3VIM Cortex-M3 Vectored Interrupt Manager MBIST Memory Built-In Self Test MibSPI Multi-Buffered Serial Peripheral Interface MPU Protection Unit NVIC Nested Vectored Interrupt Controller OSC Oscillator PCR Peripheral Central Resource PLL Phase-Locked Loop PSA Parallel Signature Analysis RTI Real-Time Interrupt Test the integrity of SRAM Part of the M3 core SCI Serial Communication Interface SECDED Single Error Correction and Double Error Detection STC Self Test Controller SYS System Module VBUS Virtual Bus One of the protocols that comprises CBA (Common Bus Architecture) VBUSP Virtual Bus-Pipelined One of the protocols that comprises CBA (Common Bus Architecture) VREG Voltage Regulator Features Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1 2 3 ................................................... 1 1.1 PZ Package View .................................... 2 1.2 Description ........................................... 3 1.3 Functional Block Diagram ............................ 5 1.4 Terms and Acronyms ................................ 6 Device Overview ........................................ 8 2.1 Memory Map Summary .............................. 9 2.2 Terminal Functions ................................. 12 2.3 Device Support ..................................... 16 Device Configuration ................................. 18 3.1 Reset/Abort Sources ............................... 18 3.2 Lockup Reset Module .............................. 19 3.3 ESM Assignments .................................. 19 3.4 Interrupt Priority (M3VIM) ........................... 20 3.5 MibADC ............................................. 21 3.6 MibSPI .............................................. 22 3.7 JTAG ID ............................................ 23 3.8 Scan Chains ........................................ 23 3.9 Low-Power Modes .................................. 23 3.10 Adaptive Impedance 4 mA IO Buffer ............... 23 3.11 Built-In Self Test (BIST) Features .................. 28 Features 4 5 ................ ............................... Device Operating Conditions ....................... 3.12 Device Identification Code Register 3.13 Device Part Numbers 31 32 4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range, Q Version ........... 32 4.2 4.3 Device Recommended Operating Conditions ...... 32 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, Q Version ...................................................... 33 Peripheral Information and Electrical Specifications .......................................... 35 ........................ 5.2 PLL and Clock Specifications ...................... 5.3 SPIn Master Mode Timing Parameters ............. 5.4 SPIn Slave Mode Timing Parameters .............. 5.5 CAN Controller (DCANn) Mode Timings ........... 5.6 High-End Timer (HET) Timings ..................... 5.7 Multi-Buffered A-to-D Converter (MibADC) ......... Revision History ....................................... Mechanical Data ....................................... 7.1 Thermal Data ....................................... 7.2 Packaging Information .............................. 5.1 6 7 30 RST and PORRST Timings Contents Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 35 40 47 51 55 55 56 60 61 61 61 7 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 2 Device Overview The TMS470MF06607 device is a TMS470M Platform Architecture implemented in F035 130-nm TI technology. Table 2-1 identifies all the characteristics of the TMS470MF06607 device except the SYSTEM and CPU, which are generic. Table 2-1. Device Characteristics CHARACTERISTICS DEVICE DESCRIPTION TMS470MF06607 COMMENTS FOR TMS470MF06607 MEMORY INTERNAL MEMORY Pipeline/Non-Pipeline 2 Bank 640K-Byte Flash with ECC 64K-Byte SRAM with ECC CRC, 1-channel Flash is pipeline-capable PERIPHERALS For the device-specific interrupt priority configurations, see Table 3-4. For the peripheral address ranges and their peripheral selects, see Table 2-6. CLOCK GENERAL-PURPOSE I/Os LIN/SCI FMzPLL 4 I/O Frequency-modulated zero-pin PLL has no external loop filter pins. The GIOA port has up to four (4) external pins with external interrupt capability. 2 LIN/SCI DCAN 2 DCAN Each with 16/32 mailboxes, respectively. MibSPI 2 MibSPI One MibSPI with eight chip select pins, 16 transfer groups, and a 64 word buffer with parity. A second MibSPI with four chip select pins, 1 enable pin, 8 transfer groups, and a 64 word buffer with parity. 18 I/O The high-resolution (HR) SHARE feature allows even-numbered HR pins to share the next higher odd-numbered HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. HET RAM with parity checking capability. HET with XOR Share HET RAM MibADC 64-Instruction Capacity 10-bit, 16-channel 64-word FIFO CORE VOLTAGE 1.5 V I/O VOLTAGE 3.3 V PINS 100 PACKAGE 8 PZ (100 pin) MibADC RAM includes parity support. Available in 100-pin package. The 100-pin package designator is PZ. Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 2.1 Memory Map Summary 2.1.1 Memory Map Figure 2-1 shows the TMS470MF06607 memory map. 0xFFFFFFFF 0xFFF80000 0xFFF7FFFF 0xFF000000 0xFEFFFFFF 0xFE000000 SYSTEM Module Peripherals PSA 0x0840FFFF 0x08400000 RAM - ECC 0x0810FFFF 0x08100000 RAM - CLR Space 0x0808FFFF 0x08080000 0x0800FFFF 0x08000000 0x0044FFFF 0x0043FFFF 0x00400000 0x0009FFFF (A) (A) RAM - SET Space (64KB) (64KB) RAM (64KB) FLASH - ECC (Bank 1) FLASH - ECC (Bank 0) FLASH (128KB - Bank 1) 0x0007FFFF FLASH (512KB - Bank 0) 0x00000000 A. The RAM supports bit access operation which allows set/clear to dedicated bits without disturbing the other bits; for detailed description see the Architecture Specification. Figure 2-1. TMS470MF06607 Memory Map 2.1.2 Memory Selects Memories in the TMS470M devices are located at fixed addresses. Table 2-2 through Table 2-6 detail the mapping of the memory regions. Table 2-2. TMS470MF06607-Specific Memory Frame Assignment (1) MEMORY FRAME NAME START ADDRESS ENDING ADDRESS MEMORY TYPE ACTUAL MEMORY nCS0 (1) 0x0000 0000 0x0009 FFFF Flash 640K Bytes RAM-CLR 0x0810 0000 0x0810 FFFF Internal RAM 64K Bytes RAM-SET 0x0808 0000 0x0808 FFFF Internal RAM 64K Bytes CSRAM0 (1) 0x0800 0000 0x0800 FFFF Internal RAM 64K Bytes CSRAM0 (1) 0x0840 0000 0x0840 FFFF Internal RAM-ECC 64K Bytes Additional address mirroring could be present resulting in invalid but addressable locations beyond those listed above. The device may generate an abort when accessing the unimplemented memory regions of peripheral memories. TI recommends the use of the MPU for protecting access to addresses outside the intended range of use. Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 9 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 2-3. Memory Initialization and MBIST CONNECTING MODULE (1) ADDRESS RANGE BASE ADDRESS ENDING ADDRESS MEMORY INITIALIZATION CHANNEL MBIST CONTROLLER ENABLE CHANNEL System RAM 0x08000000 0x0800FFFF 0 0 MibSPI1 RAM 0xFF0E0000 0xFF0FFFFF 1 1 or 2 (1) MibSPIP2 RAM 0xFF0C0000 0xFF0DFFFF 2 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 3 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 4 ADC RAM 0xFF3E0000 0xFF3FFFFF 5 5 HET RAM 0xFF460000 0xFF47FFFF Not Available 6 STC ROM Not Applicable Not Applicable Not Applicable 7 3 or 4 (1) There are single MBIST controllers for both MibSPI RAMs and both DCAN RAMs. The MBIST controller for both MibSPI RAMs is mapped to channels 1 and 2 and the MBIST controller for both DCAN RAMs is mapped to channels 3 and 4. MBIST on these modules can be initiated by selecting one of the 2 channels or both. Table 2-4. Peripheral Memory Chip Select Assignment ADDRESS RANGE CONNECTING MODULE BASE ADDRESS ENDING ADDRESS PERIPHERAL SELECTS MibSPI1 RAM 0xFF0E0000 0xFF0FFFFF PCS[7] MibSPIP2 RAM 0xFF0C0000 0xFF0DFFFF PCS[6] DCAN1 RAM 0xFF1E0000 0xFF1FFFFF PCS[14] DCAN2 RAM 0xFF1C0000 0xFF1DFFFF PCS[15] ADC RAM 0xFF3E0000 0xFF3FFFFF PCS[31] HET RAM 0xFF460000 0xFF47FFFF PCS[35] NOTE All used peripheral memory chip selects should decode down to the smallest possible address for this particular peripheral configuration, starting from 4kB upwards. Unused addresses should generate an illegal address error when accessed. Table 2-5. System Peripheral Registers ADDRESS RANGE FRAME NAME 10 FRAME START ADDRESS FRAME ENDING ADDRESS 0xFEFF_FFFF PSA 0xFE00_0000 Flash Wrapper Registers 0xFFF8_7000 0xFFF8_7FFF PCR Register 0xFFFF_E000 0xFFFF_E0FF System Frame 2 Registers 0xFFFF_E100 0xFFFF_E1FF CPU STC (LBIST) 0xFFFF_E400 0xFFFF_E4FF ESM Register 0xFFFF_F500 0xFFFF_F5FF RAM ECC Register 0xFFFF_F900 0xFFFF_F9FF RTI Register 0xFFFF_FC00 0xFFFF_FCFF VIM Register 0xFFFF_FE00 0xFFFF_FEFF System Registers 0xFFFF_FF00 0xFFFF_FFFF Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 2-6. Peripheral Select Map with Address Range 2.1.3 CONNECTING MODULE BASE ADDRESS END ADDRESS PERIPHERAL SELECTS MibSPIP2 0xFFF7_F600 0xFFF7_F7FF PS[2] MibSPI1 0xFFF7_F400 0xFFF7_F5FF LIN/SCI1 0xFFF7_E500 0xFFF7_E5FF LIN/SCI2 0xFFF7_E400 0xFFF7_E4FF DCAN2 0xFFF7_DE00 0xFFF7_DFFF DCAN1 0xFFF7_DC00 0xFFF7_DDFF ADC 0xFFF7_C000 0xFFF7_C1FF PS[15] GIO 0xFFF7_BC00 0xFFF7_BCFF PS[16] HET 0xFFF7_B800 0xFFF7_B8FF PS[17] PS[6] PS[8] Flash Memory When in pipeline mode, the Flash operates with a system clock frequency of up to 80 MHz (versus a system clock in non-pipeline mode of up to 28 MHz). Flash in pipeline mode is capable of accessing 128-bit words and provides four 32-bit pipelined words to the CPU. NOTE 1. After a system reset, pipeline mode is disabled [FRDCNTL[2:0] is 000b, see the Flash chapter in the TMS470M Series Technical Reference Manual (SPNU495). In other words, the device powers up and comes out of reset in non-pipeline mode. 2. The flash external pump voltage (VCCP) is required for all operations (program, erase, and read). 2.1.4 Flash Program and Erase The TMS470MF06607 device flash contains one 512K-byte memory array (or bank) and one 128K-byte bank for a total of 15 sectors. These 15 sectors are sized as shown in Table 2-7. The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit word. Table 2-7. Flash Memory Banks and Sectors SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS 0 16k 0x0000_0000 0x0000_3FFF 1 16k 0x0000_4000 0x0000_7FFF 2 32k 0x0000_8000 0x0000_FFFF 3 64k 0x0001_0000 0x0001_FFFF 4 64k 0x0002_0000 0x0002_FFFF 5 64k 0x0003_0000 0x0003_FFFF 6 64k 0x0004_0000 0x0004_FFFF 7 64k 0x0005_0000 0x0005_FFFF 8 64k 0x0006_0000 0x0006_FFFF 9 64k 0x0007_0000 0x0007_FFFF MEMORY ARRAYS (OR BANKS) BANK 0 (512K Bytes) Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 11 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 2-7. Flash Memory Banks and Sectors (continued) SECTOR NO. SEGMENT LOW ADDRESS HIGH ADDRESS MEMORY ARRAYS (OR BANKS) 0 16k 0x0008_0000 0x0008_3FFF 1 16k 0x0008_4000 0x0008_7FFF BANK 1 (1) (128K Bytes) 2 16k 0x0008_8000 0x0008_BFFF 3 16k 0x0008_C000 0x0008_FFFF 4 64k 0x0009_0000 0x0009_FFFF (1) Bank 1 can be used as either EEPROM emulation space or as program space. 2.2 Terminal Functions The terminal functions table (Table 2-8) identifies the pin names, the associated pin numbers, input voltage, output voltage, whether the pin has any internal pullup/pulldown resistors and a functional pin description. Table 2-8. Terminal Functions TERMINAL NAME 100 PIN INPUT VOLTAGE (1) (2) OUTPUT CURRENT (3) IPU/IPD (4) DESCRIPTION HIGH-END TIMER (HET) HET[0] 39 HET[1] 40 HET[2] 49 HET[3] 50 HET[4] 53 HET[5] 54 HET[6] 55 HET[7] 56 HET[8] 57 HET[9] 58 HET[10] 59 HET[11] 60 HET[12] 61 HET[13] 62 HET[14] 63 HET[15] 64 HET[24] 45 HET[25] 46 Timer input capture or output compare. The HET[15:0] applicable pins can be programmed as general-purpose input/output (GIO) pins. All are high-resolution pins. 3.3-V I/O Adaptive impedance 4 mA Programmable IPD (100 µA) The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. NOTE: HET[24] and HET[25] channels are muxed with TDO/TDI pins. During debug, their respective input buffers will reflect the state of TDI and TDO. CAN CONTROLLER 1 (DCAN1) CAN1STX 7 CAN1SRX 8 3.3-V I/O Adaptive impedance 4 mA Programmable IPU (100 µA) DCAN1 transmit pin or GIO pin. DCAN1 receive pin or GIO pin. CAN CONTROLLER 2 (DCAN2) CAN2STX 37 CAN2SRX 38 (1) (2) (3) (4) 12 3.3-V I/O Adaptive impedance 4 mA Programmable IPU (100 µA) DCAN2 transmit pin or GIO pin DCAN2 receive pin or GIO pin PWR = power, GND = ground, REF = reference voltage, NC = no connect All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. The TMS470M device utilizes adaptive impedance 4 mA buffers that default to the adaptive impedance mode of operation. As a fail-safe, the adaptive impedance features of the buffer may be disabled and revert the buffer to a standard buffer mode. IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are inactive on input pins when PORRST is asserted) Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 2-8. Terminal Functions (continued) TERMINAL NAME 100 PIN INPUT VOLTAGE (1) (2) OUTPUT CURRENT (3) IPU/IPD (4) DESCRIPTION GENERAL-PURPOSE I/O (GIO) GIOA[4]/INT[4] 5 General-purpose input/output pins. Adaptive impedance 4 mA GIOA[5]/INT[5] 6 GIOA[6]/INT[6] 15 GIOA[7]/INT[7] 16 MIBSPI1CLK 34 MIBSPI1SCS[0] 33 MIBSPI1sCS[1] 32 MIBSPI1SCS[2] 31 MIBSPI1SCS[3] 30 MIBSPI1SCS[4] 29 MIBSPI1SCS[5] 28 MIBSPI1SCS[6] 27 MIBSPI1SCS[7] 26 MIBSPI1SIMO 35 MIBSPI1 data stream. Slave in/master out. MIBSPI1SIMO can be programmed as a GIO pin. MIBSPI1SOMI 36 MIBSPI1 data stream. Slave out/master in. MIBSPI1SOMI can be programmed as a GIO pin. MIBSPIP2CLK 17 MIBSPIP2SCS[0] 1 MIBSPIP2SCS[1] 2 MIBSPIP2SCS[2] 3 3.3-V I/O Programmable IPD (100 µA) 100 pin - GIOA[7:4]/INT[7:4] are interrupt-capable pins. MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE 1 (MIBSPI1) MIBSPI1 clock. MIBSPI1CLK can be programmed as a GIO pin. 3.3-V I/O Adaptive impedance 4 mA Programmable IPU (100 µA) MIBSPI1 slave chip select. MIBSPI1SCS[7:0] can be programmed as a GIO pins. MULTI-BUFFERED SERIAL PERIPHERAL INTERFACE 2 (MIBSPIP2) MIBSPIP2 clock. MIBSPIP2CLK can be programmed as a GIO pin. MIBSPIP2 slave chip select MIBSPIP2SCS[3:0] can be programmed as GIO pins. MIBSPIP2SCS[3] 4 MIBSPIP2ENA 90 MIBSPIP2SIMO 18 MIBSPIP2 data stream. Slave in/master out. MIBSPIP2SIMO pins can be programmed as a GIO pins. MIBSPIP2SOMI 19 MIBSPIP2 data stream. Slave out/master in. MIBSPIP2SOMI pins can be programmed as GIO pins. 3.3-V I/O Adaptive impedance 4 mA Programmable IPU (100 µA) MIBSPIP2 enable pin. MIBSPIP2ENA can be programmed as a GIO pin. LOCAL INTERCONNECT NETWORK 1/SERIAL COMMUNICATIONS INTERFACE 1 (LIN1/SCI1) LIN1/SCI1RX LIN1/SCI1TX 23 22 3.3-V I/O Adaptive impedance 4 mA Programmable IPU (100 µA) LIN/SCI1 data receive. Can be programmed as a GIO pin. LIN/SCI1 data transmit. Can be programmed as a GIO pin. LOCAL INTERCONNECT NETWORK 2/SERIAL COMMUNICATIONS INTERFACE 2 (LIN2/SCI2) LIN2/SCI2RX 25 LIN2/SCI2TX 24 ADEVT 68 3.3-V I/O Adaptive impedance 4 mA Programmable IPU (100 µA) LIN/SCI2 data receive. Can be programmed as a GIO pin. LIN/SCI2 data transmit. Can be programmed as a GIO pin. MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MIBADC) 3.3-V I/O Adaptive impedance 4 mA Programmable IPD (100 µA) MibADC event input. Can be programmed as a GIO pin. Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 13 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 2-8. Terminal Functions (continued) TERMINAL NAME 100 PIN INPUT VOLTAGE (1) (2) OUTPUT CURRENT (3) IPU/IPD (4) DESCRIPTION ADIN[0] 69 ADIN[1] 70 ADIN[2] 71 ADIN[3] 72 ADIN[4] 73 ADIN[5] 74 ADIN[6] 75 ADIN[7] 76 ADIN[8] 77 ADIN[9] 78 ADIN[10] 79 ADIN[11] 80 ADIN[12] 81 ADIN[13] 86 ADIN[14] 87 ADIN[15] 88 ADREFHI 82 3.3-V REF MibADC module high-voltage reference input. ADREFLO 83 GND REF MibADC module low-voltage reference input. VCCAD 85 3.3-V PWR MibADC analog supply voltage. VSSAD 84 GND 3.3 V MibADC analog input pins. MibADC analog ground reference. OSCILLATOR (OSC) OSCIN 10 1.5-V I OSCOUT 11 1.5-V O Crystal connection pin or external clock input. External crystal connection pin. SYSTEM MODULE (SYS) PORRST 89 RST 98 IPD (100 µA) 3.3-V I 3.3-V I/O ECLK 96 3.3-V I/O TCK 44 3.3-V I TDI 46 Adaptive impedance 4 mA Adaptive impedance 4 mA Input master chip power-up reset. External VCC monitor circuitry must assert a power-on reset. IPU (100 µA) Bidirectional reset. The internal circuitry can assert a reset, and an external system reset can assert a device reset. On this pin, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor be connected to this pin. Programmable IPD (100 µA) Bidirectional pin. ECLK can be programmed as a GIO pin. TEST/DEBUG (T/D) TDO 45 3.3-V I/O TMS 47 TRST 48 14 3.3-V I Adaptive impedance 4 mA IPD (100 µA) Test clock. TCK controls the test hardware (JTAG). IPU (100 µA) Test data in pin. TDI inputs serial data to the test instruction register, test data register, and programmable test address (JTAG). Note: This pin is muxed with the HET channel 25. IPD (100 µA) Test data out pin. TDO outputs serial data from the test instruction register, test data register, identification register, and programmable test address (JTAG). Note: This pin is muxed with the HET channel 24. IPU (100 µA) Serial input pin for controlling the state of the CPU test access port (TAP) controller (JTAG). IPD (100 µA) Test hardware reset to TAP. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic. Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 2-8. Terminal Functions (continued) TERMINAL NAME TEST ENZ 100 PIN INPUT VOLTAGE (1) (2) OUTPUT CURRENT (3) IPU/IPD (4) 97 3.3-V I IPD (100 µA) 3.3-V I IPD (100 µA) 91 DESCRIPTION Test enable. Reserved for internal use only. TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. Enables/disables the internal voltage regulator. 0V - Enables internal voltage regulator. 3.3V-Disables internal voltage regulator. FLASH FLTP1 99 VCCP1 95 VCCP2 95 VCC 12 Flash Test Pad 1 pin. For proper operation, this pin must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event. Flash external pump voltage (3.3 V). This pin is required for both Flash read and Flash program and erase operations. VCCP1 and VCCP2 are double bonded to the same pin. 3.3-V PWR SUPPLY VOLTAGE CORE (1.5 V) 41 67 Vreg output voltage when Vreg is enabled. VCC input when Vreg is disabled. 1.5-V PWR 92 SUPPLY VOLTAGE DIGITAL I/O AND REGULATOR (3.3 V) VCCIOR 14 20 43 52 3.3-V PWR Digital I/O and internal regulator supply voltage. 65 94 SUPPLY GROUND VSS 9 13 21 42 51 GND Digital I/O and core supply ground reference. 66 93 100 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 15 TMS470MF06607 SPNS157C – JANUARY 2012 2.3 2.3.1 www.ti.com Device Support Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,TMS470MF06607). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZ), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz. Figure 2-2 illustrates the numbering and symbol nomenclature for the TMS470M family. 16 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Full Part Number TMS 470 MF 06 6 07 B S PZ Q Q1 R Orderable Part Number S 4 MF 06 6 07 B S PZ Q Q1 R Prefix: TM S = TMS Qualified P = TMP Prototype X = TMX Samples Core Technology: 4 = 470 Cortex M3 Architecture: MF = M3 Flash Flash Memory Size: 06 = 640 KBytes RAM Memory Size: 6 = 64 KBytes Package Option: 07 = 100-pin package Die Revision: Blank = Initial Die A = First Die Revision B = Second Die Revision Technology/Core Voltage: S = F035 (130 nm), 1.5-V Nominal Core Voltage Package Type: PZ = 100-Pin QFP Package (Green) Temperature Range: I = -40°C to +85°C T = -40°C to +105°C Q = -40°C to +125°C Quality Designator: Q1 = Automotive Shipping Options: R = Tape and Reel NOTE: The part number given above is for illustrative purposes only and does not represent the specific part number or silicon revision to which this document applies. Figure 2-2. TMS470M Device Numbering Conventions Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 17 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3 Device Configuration 3.1 Reset/Abort Sources Resets/aborts are handled as shown in Table 3-1. Table 3-1. Reset/Abort Sources SYSTEM MODE ERROR RESPONSE ESM HOOKUP, GROUP.CHANNEL Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a External imprecise error (Illegal transaction with ok response) User/Privilege ESM 2.17 Illegal instruction User/Privilege Undefined Instruction Trap (CPU) (1) n/a M3 Lockup User/Privilege ESM => NMI 2.16 MPU access violation User/Privilege Abort (CPU) n/a ECC single error (correctable) User/Privilege ESM 1.26 ECC double error (uncorrectable) User/Privilege ESM => NMI 2.6 ECC single error (correctable) User/Privilege ESM 1.6 ECC double error (uncorrectable) User/Privilege ESM => NMI 2.4 User/Privilege ESM 1.7 MibSPI1 memory parity error User/Privilege ESM 1.17 MibSPI2 memory parity error User/Privilege ESM 1.18 User/Privilege ESM 1.19 DCAN1 memory parity error User/Privilege ESM 1.21 DCAN2 memory parity error User/Privilege ESM 1.23 User/Privilege ESM 1.10 User/Privilege ESM 1.11 n/a Reset n/a User/Privilege ESM 1.27 n/a Reset n/a ERROR SOURCE 1) CPU TRANSACTIONS 2) SRAM 3) FLASH WITH ECC 8) HET HET Memory parity error 9) MIBSPI 10) MIBADC Memory parity error 11) DCAN/CAN 13) PLL PLL slip error 14) CLOCK MONITOR Clock monitor interrupt 19) VOLTAGE REGULATOR Vcc out of range 20) CPU SELFTEST (LBIST) CPU Selftest (LogicBIST) error 21) ERRORS REFLECTED IN THE SYSESR REGISTER Power-Up Reset/Vreg out of voltage (2) (1) (2) 18 The undefined instruction trap is NOT detected outside of the CPU. The trap is taken only if the code reaches the execute stage of the CPU. Both a power-on reset and Vreg out-of-range reset are indicated by the PORST bit in the SYSESR register. Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-1. Reset/Abort Sources (continued) SYSTEM MODE ERROR RESPONSE ESM HOOKUP, GROUP.CHANNEL Oscillator fail / PLL slip (3) n/a Reset n/a M3 Lockup/LRM n/a Reset n/a Watchdog time limit exceeded n/a Reset n/a CPU Reset n/a Reset n/a Software Reset n/a Reset n/a External Reset n/a Reset n/a ERROR SOURCE (3) 3.2 Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset. Lockup Reset Module The lockup reset module (LRM) is implemented to communicate a lockup condition by the core. The LRM provides a small watchdog timer which can generate a system reset in case a lockup condition that is identified by the core cannot be cleared by software. 3.3 ESM Assignments The ESM module is intended for the communication critical system failures in a central location. The error indication is by an error interrupt when the failure is recognized from any detection unit. The ESM module consist of three error groups with 32 inputs each. The generation of the interrupts is shown in Table 3-2. ESM assignments are listed in Table 3-3. Table 3-2. ESM Groups ERROR GROUP INTERRUPT, LEVEL Group1 maskable, low/high Group2 non-maskable, high Group3 Not Used Table 3-3. ESM Assignments ERROR SOURCES CHANNEL GROUP 1 Reserved 0-5 Flash - ECC Single Bit 6 HET memory parity error 7 Reserved 8-9 PLL Slip Error 10 Clock Monitor interrupt 11 Reserved 12-16 MibSPI1 memory parity error 17 MibSPIP2 memory parity error 18 MibADC memory parity error 19 Reserved 20 DCAN1 memory parity error 21 Reserved 22 DCAN2 memory parity error 23 Reserved 24-25 SRAM - single bit 26 CPU LBIST - selftest error 27 Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 19 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-3. ESM Assignments (continued) ERROR SOURCES CHANNEL Reserved 28-31 GROUP 2 3.4 Reserved 0-3 Flash - Double-Bit Error (uncorrectable) 4 Reserved 5 SRAM - Double-Bit Error (uncorrectable) 6 Reserved 7-15 M3 Lockup 16 M3 External Imprecise Abort 17 Reserved 18-31 Interrupt Priority (M3VIM) The TMS470M platform interrupt architecture includes a vectored interrupt manager (M3VIM) that provides hardware assistance for prioritizing and controlling the many interrupt sources present on a device. Table 3-4 communicates the default interrupt request assignments. Table 3-4. Interrupt Request Assignments 20 MODULES INTERRUPT SOURCES DEFAULT VIM INTERRUPT REQUEST ESM ESM High level interrupt (NMI) 0 Reserved (NMI) 1 ESM ESM Low level interrupt 2 SYSTEM Software interrupt (SSI) 3 RTI RTI compare interrupt 0 4 RTI RTI compare interrupt 1 5 RTI RTI compare interrupt 2 6 RTI RTI compare interrupt 3 7 RTI RTI overflow interrupt 0 8 RTI RTI overflow interrupt 1 9 Reserved Reserved 10 GIO GIO Interrupt A 11 GIO GIO Interrupt B 12 HET HET level 0 interrupt 13 HET HET level 1 interrupt 14 MibSPI1 MibSPI1 level 0 interrupt 15 MibSPI1 MibSPI1 level 1 interrupt 16 Reserved Reserved 17 LIN2/SCI2 LIN2/SCI2 level 0 interrupt 18 LIN2/SCI2 LIN2/SCI2 level 1 Interrupt 19 LIN1/SCI1 LIN1/SCI1 level 0 interrupt 20 LIN1/SCI1 LIN1/SCI1 level 1 Interrupt 21 DCAN1 DCAN1 level 0 Interrupt 22 DCAN1 DCAN1 level 1 Interrupt 23 ADC ADC event group interrupt 24 ADC ADC sw group 1 interrupt 25 ADC ADC sw group 2 interrupt 26 Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-4. Interrupt Request Assignments (continued) 3.5 MODULES INTERRUPT SOURCES DEFAULT VIM INTERRUPT REQUEST MibSPIP2 MibSPIP2 level 0 interrupt 27 MibSPIP2 MibSPIP2 level 1 interrupt 28 DCAN2 DCAN2 level 0 interrupt 29 DCAN2 DCAN2 level 1 interrupt 30 ADC ADC magnitude threshold interrupt 31 Reserved Reserved 32 Reserved Reserved 33 DCAN1 DCAN1 IF3 interrupt 34 DCAN2 DCAN2 IF3 interrupt 35 Reserved Reserved 36-47 MibADC The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a 10-bit digital value. The TMS470M MibADC module stores its digital results in one of three FIFO buffers. There is one FIFO buffer for each conversion group [event, group1 (G1), and group2 (G2)], and the total MibADC FIFO on the device is divided amongst these three regions. The size of the individual group buffers are software programmable. MibADC buffers can be serviced by interrupts. 3.5.1 MIBADC Event Triggers All three conversion groups can be configured for event-triggered operation, providing up to three event-triggered groups. The trigger source and polarity can be selected individually for group 1, group 2 and the event group from the options identified in Table 3-5. Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 21 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-5. MibADC Event Hookup Configuration (1) (2) 3.6 EVENT NO. SOURCE SELECT BITS for G1 or EVENT (G1SRC[2:0] or EVSRC[2:0]) SIGNAL PIN NAME 1 000 ADEVT 2 001 HET[1] 3 010 HET[3] 4 011 HET[16] (1) 5 100 HET[18] (1) 6 101 HET[24] (2) 7 110 HET[26] (1) 8 111 HET[28] (1) These channels are available as internal signals even if they are not included as pins (Figure 1-1). During debug modes, the state of TDO will affect the state of the HET[24] input buffer. MibSPI The multi-buffered serial peripheral interface module allows CPU independent SPI communications with system peripherals. The MibSPI1 module can support up to 16 transfer groups and 8 chip selects. In addition, up to 4 data formats can be supported allowing assignment of various formats to each transfer group. The MiBSPIP2 module can support up to 8 transfer groups, 4 chip selects, and up to 4 data formats. 3.6.1 MIBSPI Event Trigger The MibSPI module has the ability to automatically trigger SPI events based on internal and external event triggers. The trigger sources can be selected individually for each transfer group from the options identified in Table 3-6. Table 3-6. MibSPI1 and MibSPIP2 Event Hookup Configuration (1) 22 EVENT NO. SOURCE SELECT BITS FOR MIBSPI EVENTS TGXCTRL TRIGSRC[3:0] SIGNAL PIN NAME Disabled 0000 No trigger source EVENT0 0001 GIOA[0] (1) EVENT1 0010 GIOA[1] (1) EVENT2 0011 GIOA[2] (1) EVENT3 0100 GIOA[3] (1) EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 HET[20] (1) EVENT7 1000 HET[21] (1) EVENT8 1001 HET[22] (1) EVENT9 1010 HET[23] (1) EVENT10 1011 HET[28] (1) EVENT11 1100 HET[29] (1) EVENT12 1101 HET[30] (1) EVENT13 1110 HET[31] (1) EVENT14 1111 Internal Tick Counter These channels are available as internal signals even if they are not included as pins (Figure 1-1). Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3.7 JTAG ID The 32-bit JTAG ID code for this device is 0x0B7E202F. 3.8 Scan Chains The device contains an ICEPICK module to access the debug scan chains; see Figure 3-1. Debug scan chain #0 handles the access to the CPU. The ICEPICK scan ID is 0x00246D15, which is the same as the device ID. TDI DAP CPU ICEPICK TDO Boundary Scan Chain #0 Boundary Scan Boundary Scan Interface Figure 3-1. Debug Scan Chains 3.9 Low-Power Modes TMS470M devices support multiple low-power modes. These different modes allow the user to trade-off the amount of current consumption during low power mode versus functionality and wake-up time. Supported low-power modes on the TMS470MF06607 are Doze and Sleep; for a detailed description see the TMS470M Series Technical Reference Manual (SPNU495). 3.10 Adaptive Impedance 4 mA IO Buffer The adaptive impedance 4 mA buffer is a buffer that has been explicitly designed to address the issue of decoupling EMI sources from the pins which they drive. This is accomplished by adaptively controlling the impedance of the output buffer and should be particularly effective with capacitive loads. The adaptive impedance 4 mA buffer features two modes of operation: Impedance Control Mode, and Low-Power Mode/Standard Buffer Mode as defined below: • Impedance Control Mode is enabled in the design by default. This mode adaptively controls the impedance of the output buffer. • Low-Power Mode is functionally identical to Standard Buffer Mode and is used to configure the buffer back into a generic configuration. This buffer mode is used during low-power device modes, when it is necessary to drive the output at very high speeds, or when EMI reduction is not a concern. Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 23 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-7. Adaptive Impedance 4 mA Buffer Mode Availability MODULE OR PIN NAME (1) 24 ADAPTIVE IMPEDANCE 4 mA BUFFER SIGNAL REGISTER HOOKUP LOW-POWER MODE (LPM) STANDARD BUFFER ENABLE (SBEN) (1) SYS.ECLK SYS.VRCTL.VLPMENA GPREG1.0 SYS.nRST SYS.VRCTL.VLPMENA GPREG1.1 SYS.TDI/TDO SYS.VRCTL.VLPMENA Standard Buffer Enabled SYS.TMSC SYS.VRCTL.VLPMENA Standard Buffer Enabled HET SYS.VRCTL.VLPMENA GPREG1.2 SCI1 SYS.VRCTL.VLPMENA GPREG1.3 LIN/SCI2 SYS.VRCTL.VLPMENA GPREG1.4 MIBSPI1 SYS.VRCTL.VLPMENA GPREG1.5 MIBSPIP2 SYS.VRCTL.VLPMENA GPREG1.6 Reserved SYS.VRCTL.VLPMENA GPREG1.7 MIBADC.ADEVT SYS.VRCTL.VLPMENA GPREG1.8 DCAN1 SYS.VRCTL.VLPMENA GPREG1.9 DCAN2 SYS.VRCTL.VLPMENA GPREG1.10 GIOA SYS.VRCTL.VLPMENA GPREG1.11 SBEN configuration can be achieved using the GPREG register within the system frame (0xFFFFFFA0). Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3.10.1 Standard Buffer Enable Register (GPREG1) A general purpose register with the system frame has been utilized to control the enabling of standard buffer mode. This register is shown in Figure 3-2 and described in Table 3-8 31 16 Reserved R-0 15 12 11 10 9 8 Reserved GIOA_SBEN DCAN2_SBEN DCAN1_SBEN ADC.ADEVT_ SBEN R-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 0 Reserved MIBSPIP2_ SBEN MIBSPI1_ SBEN LIN2SCI2_ SBEN LIN1SCI1_ SBEN HET_SBEN RST_SBEN ECLK_SBEN RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 3-2. General-Purpose Register 1 (GPREG1) Table 3-8. General-Purpose Register 1 (GPREG1) Field Descriptions Bit 31-12 11 10 9 8 7 6 5 4 Field Value Description Reserved These bits are reserved. Reads return 0 and writes have no effect. GIOA_SBEN GIOA port standard buffer enable bit. This bit enables/disables standard buffer mode for all GIOA pins 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. DCAN2_SBEN DCAN2 standard buffer enable bit. This bit enables/disables standard buffer mode for all DCAN2 pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. DCAN1_SBEN DCAN1 standard buffer enable bit. This bit enables/disables standard buffer mode for all DCAN1 pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. ADC.ADEVT_SBEN ADC.ADEVT standard buffer enable bit. This bit enables/disables standard buffer mode for the ADC.ADEVT pin. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for the ADEVT pin. Reserved Reserved 0 Reserved 1 Reserved MIBSPIP2_SBEN MIBSPIP2 standard buffer enable bit. This bit enables/disables standard buffer mode for all MIBSPIP2 pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. MIBSPI1 MIBSPI1 standard buffer enable bit. This bit enables/disables standard buffer mode for all MIBSPI1 pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. LIN2SCI2_SBEN LINSCI2 standard buffer enable bit. This bit enables/disables standard buffer mode for all LINSCI2 pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 25 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-8. General-Purpose Register 1 (GPREG1) Field Descriptions (continued) Bit 3 2 1 0 Field Value Description LIN1SCI1_SBEN SCI1 standard buffer enable bit. This bit enables/disables standard buffer mode for all SCI1 pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. HET_SBEN HET standard buffer enable bit. This bit enables/disables standard buffer mode for all HET pins. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for all associated module pins. RST_SBEN RST standard buffer enable bit. This bit enables/disables standard buffer mode for the RST pin. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for the RST pin. ECLK_SBEN ECLK standard buffer enable bit. This bit enables/disables standard buffer mode for the ECLK pin. 0 Standard buffer mode is not enabled. 1 Standard buffer mode is enabled for the ECLK pin. 3.10.2 Coresight Components/Debug ROM Coresight registers are memory-mapped and accessible via the CPU and JTAG. Table 3-9. Debug Component Memory Map COMPONENT FRAME START ADDRESS FRAME END ADDRESS FRAME SIZE MEMORY TYPE M3 INTEGRATION FRAME ITM(1) 0xE000_0000 0xE000_0FFF 4K DWT 0xE000_1000 0xE000_1FFF 4K FPB 0xE000_2000 0xE000_2FFF 4K NVIC 0xE000_E000 0xE000_EFFF 4K Debug ROM 1 0xE00F_F000 0xE00F_FFFF 4K Control Registers for debug and trace modules PLATFORM DEBUG FRAME (1) Debug ROM 2 0xFFA0_0000 0xFFA0_0FFF 4K ETM-M3 (1) 0xFFA0_1000 0xFFA0_1FFF 4K HTM (1) 0xFFA0_2000 0xFFA0_2FFF 4K Trace Funnel 0xFFA0_3000 0xFFA0_3FFF 4K TPIU 0xFFA0_4000 0xFFA0_4FFF 4K Control Registers for debug and trace modules Availability of trace components, although present in the design, are not externally available in the PZ packaged devices. A suitable emulation capable package is available from TI if a need for trace capability exists. Table 3-10. Debug ROM contents for Debug ROM 1 (M3 ROM) 26 ADDRESS OFFSET (see Table 3-9 ) DESCRIPTION VALUE 0x000 NVIC 0xFFF0_F003 0x004 DWT 0xFFF0_2003 0x008 FPB 0xFFF0_3003 0x00C ITM 0xFFF0_1003 Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 3-10. Debug ROM contents for Debug ROM 1 (M3 ROM) (continued) (1) ADDRESS OFFSET (see Table 3-9 ) DESCRIPTION VALUE 0x010 TPIU (1) 0xFFF4_1002 0x014 ETM (1) 0xFFF4_2002 0x018 Debug ROM 2 (CoreSight ROM) 0x1F90_1003 0x01C End of Table 0x0000_0000 0x020 - 0xEFC Unused 0x0000_0000 0xF00 - 0xFC8 Reserved 0x0000_0000 0xFCC MEMTYPE 0x0000_0001 0xFD0 PID4 0x0000_0000 0xFD4 PID5 0x0000_0000 0xFD8 PID6 0x0000_0000 0xFDC PID7 0x0000_0000 0xFE0 PID0 0x0000_0000 0xFE4 PID1 0x0000_0000 0x0000_0000 0xFE8 PID2 0xFEC PID3 0x0000_0000 0xFF0 CID0 0x0000_000D 0xFF4 CID1 0x0000_0010 0xFF8 CID2 0x0000_0005 0xFFC CID3 0x0000_00B1 Cortex™-M3 debug ROM always will have entries for optional components TPIU and ETM. Whether or not these components are present is determined by bit number 0 of the entry value. Table 3-11. Debug ROM contents for Debug ROM 2 (CoreSight ROM) ADDRESS OFFSET (see Table 3-9 ) DESCRIPTION VALUE 0x000 ETM-M3 0x0000_1003 0x004 HTM 0x0000_2003 0x008 Trace Funnel 0x0000_3003 0x00C TPIU 0x0000_4003 0x010 End of Table 0x0000_0000 0x014 - 0xEFC Unused 0x0000_0000 0xF00 - 0xFCC Reserved 0x0000_0000 0xFD0 PID4 0x0000_0000 0xFD4 PID5 0x0000_0000 0xFD8 PID6 0x0000_0000 0xFDC PID7 0x0000_0000 0xFE0 PID0 0x0000_0000 0xFE4 PID1 0x0000_0007 0x0000_0009 0xFE8 PID2 0xFEC PID3 0x0000_0000 0xFF0 CID0 0x0000_000D 0xFF4 CID1 0x0000_0010 0xFF8 CID2 0x0000_0005 0xFFC CID3 0x0000_00B1 Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 27 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3.11 Built-In Self Test (BIST) Features 3.11.1 STC/LBIST The TMS470M family supports a logic built-in self test (LBIST or CPUBIST) of the M3 CPU. LBIST testing can be performed in two modes of operation: • Full Execution. In this mode, the full suite of test patterns is run without interruption. This test is started via CPU control and is well suited for use at device start up. • Cyclic Execution. During cyclic execution, a small percentage of time will be dedicated to running a subset of the self-test (STC Intervals). This mode is well suited for executing on a periodic basis to minimize the bandwidth use. After all STC intervals are executed, all test patterns will have been run. NOTE 1. The application will need to disable peripherals and or interrupts to avoid missing interrupts. 2. No debugger interaction is possible with the CPU during self test. This includes access to memory and registers since access is through the CPU. The default value of the LBIST clock prescaler (STCDIV) is divide-by-1; however, the maximum STC CLK is limited by the current consumption and supply capability of the Vreg. For specified maximum STC clock rates for specified operating frequencies, see Table 3-12. Table 3-12. Maximum STC Clock Frequencies vs HCLK (1) (1) HCLK FREQUENCY (MHz) STC DIVIDER (STC_DIV+1) STC CLOCK FREQUENCY (MHz) 80 2 40 72 2 36 56 2 28 28 1 28 The maximum LBIST STC clock frequency is limited to 40MHz. 100 2500.00 90 80 2000.00 60 1500.00 50 40 1000.00 Test Time (µs) % Coverage 70 30 500.00 20 10 0 0 50 100 150 200 250 300 350 No. of Intervals 400 450 500 0.00 550 Test Coverage Test Time (µs) A. B. A single LBIST interval is 158 STC CLK cycles in duration, excluding clock transition timing of 20 cycles. This device has 550 total intervals. Figure 3-3. CPU BIST Intervals vs Coverage 28 Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3.11.2 MBIST The TMS470M family supports memory built-in self test (MBIST) of the system and peripheral SRAM. The MBIST is accessible via the application in order to facilitate memory self test by the application by enabling the MBIST controllers associated with the specific RAMs to be tested. (For device-specific MBIST controller assignments, see Table 2-3.) The MBIST controller: • Supports testing of all system and peripheral RAM. • Captures the MBIST results in the MBIST status register (MSTFAIL). • Supports execution of each Memory BIST controller in parallel (MSINENA). For MSIENA bit assignments, see Table 2-3 • Supports execution of each Memory BIST controller individually (MSINENA). For MSIENA bit assignments, see Table 2-3 The MBIST controller selection is mapped to the MBIST controller/memory initialization enable register (MSIENA) within the SYS register frame. Each MBIST controller is enabled by setting the corresponding bit within this register and then enabling memory self-test via the memory self-test global enable within the global control register (MSTGCR.MSTGENA[3:0]). The MBIST controllers support execution of the following tests: • March13N, background 0 • March11N, background A • Checkerboard and Inverse Checkerboard • March13N, background 3, 0F, and 69 • PMOS Address decoder Algorithm • ROM2 algorithm for STC NOTE The algorithm to be applied is selectable via the memory self-test global control register algo selection field (MSTGCR.MBIST_ALGSEL[7:0]). Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 29 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3.12 Device Identification Code Register The device identification code register identifies the coprocessor status, an assigned device-specific part number, the technology family (TF), the I/O voltage, whether or not parity is supported, the levels of flash and RAM error detection, and the device version. The TMS470M device identification code base register value is 0X00246D15 and is subject to change based on the silicon version. 31 30 17 16 CP15 PART NUMBER TF R-0 R-00000000010010 R-0 15 12 11 TF 13 I/O VOLT PP FLASHECC RAMECC R-011 R-0 R-1 R-10 R-1 7 3 10 9 8 2 1 VERSION 1 0 0 1 R-0010 R-1 R-0 R-1 LEGEND: R = Read only; -n = value after reset Figure 3-4. TMS470M Device ID Bit Allocation Register Table 3-13. TMS470M Device ID Bit Allocation Register Field Descriptions Bit Field 31 CP15 Value Description This bit indicates the presence of coprocessor (CP15). 0 No coprocessor present in the device. 1 Coprocessor present in the device. 30-17 PART NUMBER These bits indicate the assigned device-specific part number. The assigned device-specific part number for the TMS470M device is 00000000010010. 16-13 TF Technology family bit. These bits indicate the technology family (C05, F05, F035, C035). 0011 12 11 10 8 30 I/O VOLT F035 I/O voltage bit. This bit identifies the I/O power supply. 0 3.3 V 1 5V PP Peripheral parity bit. This bit indicates whether parity is supported. 0 No parity on peripheral. 1 Parity on peripheral. FLASHECC Flash ECC bits. These bits indicate the level of error detection and correction on the flash memory. 00 No error detection/correction. 01 Program memory with parity. 10 Program memory with ECC. 11 Reserved RAMECC RAM ECC bits. This bit indicates the presence of error detection and correction on the CPU RAM. 0 RAM ECC not present. 1 RAM ECC present. 7-3 VERSION These bits identify the silicon version of the device. 2-0 101 Bits 2:0 are set to 101 by default to indicate a platform device. Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 3.13 Device Part Numbers Table 3-14 lists all the available TMS470MF06607 device configurations. Table 3-14. Device Part Numbers DEVICE PART NUMBER TMS470MF06607BPZQ (1) SAP PART NUMBER S4MF06607BSPZQQ1 PROGRAM MEMORY PACKAGE TYPE TEMPERATURE RANGE FLASH EEPROM 100-PIN LQFP -40°C to 125°C X X X PbFREE/ GREEN (1) X RoHS compliant products are compatible with the current RoHS requirements for all six substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials, unless exempt. Pb-Free products are RoHS Compliant, plus suitable for use in higher temperature lead-free solder processes (typically 245 to 260°C). Green products are RoHS and Pb-Free, plus also free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Device Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 31 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 4 Device Operating Conditions Absolute Maximum Ratings Over Operating Free-Air Temperature Range, Q Version (1) 4.1 VCC (2) Supply voltage range: -0.5 V to 2.1 V VCCIOR, VCCAD, VCC (Flash pump) Input voltage range: (2) -0.5 V to 4.1 V All input pins Input clamp current: -0.5 V to 4.1 V IIK (VI < 0 or VI > VCCIOR) All pins, except ADIN[0:15] ±20 mA IIK (VI < 0 or VI > VCCIOR) ADIN[0:15] ±10 mA Operating free-air temperature range, TA: Q version -40°C to 125°C Operating junction temperature range, TJ: Standard -40°C to 150°C Storage temperature range, Tstg (1) (2) -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated grounds. Device Recommended Operating Conditions (1) 4.2 MIN NOM MAX UNIT 3 3.3 3.6 V 1.40 1.55 1.70 V MibADC supply voltage 3 3.3 3.6 V VCCP Flash pump supply voltage 3 3.3 3.6 V VSS Digital logic supply ground VSSAD MibADC supply ground TA Operating free-air temperature TJ Operating junction temperature VCCIOR Digital I/O and internal regulator supply voltage VCC Voltage regulator output voltage VCCAD (1) 32 0 Q version V -0.1 0.1 V -40 125 °C -40 150 °C All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD. Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 4.3 Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, Q Version (1) (2) PARAMETER Vhys VIL VIH TEST CONDITIONS MIN Input hysteresis Low-level input voltage High-level input voltage All inputs (3) -0.3 OSCIN All inputs (3) 2 OSCIN IOL = IOL MAX VOH High-level output voltage 0.8 VCCIOR VCCIOR -0.2 IOH = 50 µA Impedance Control mode 0.8 VCCIOR VI < VSSIO - 0.3 or VI > VCCIOR + 0.3 Input clamp current (I/O pins) (4) IIH Pulldown VI = VCCIOR IIL Pullup VI = VSS All other pins No pullup or pulldown Adaptive Impedance 4 mA VOL = VOL MAX Buffer IOH High-level output current Adaptive Impedance 4 mA VOH = VOH MIN Buffer (4) (5) V V VCCIOR + 0.3 V 0.2 VCCIOR IOH = 50 µA Standard mode Low-level output tcurrent (1) (2) (3) 0.8 0.2 VCC V IOH = IOH MAX IOL ICC mV 0.2 IOL = 50 µA Impedance Control mode Input current (I/O pins) UNIT 0.2 VCCIOR IOL = 50 µA Standard mode Low-level output voltage II MAX 0.8 VCC VOL IIC TYP 150 VCC digital supply current (operating mode, internal regulator disabled) HCLK = 80 MHz, VCLK = 80 MHz, VCC = 1.70 V (5) V -2 2 45 190 -190 -45 -1 1 4 -4 mA µA mA mA 115 mA Source currents (out of the device) are negative while sink currents (into the device) are positive. "All frequencies" will include all specified device configuration frequencies. The VIL here does not apply to the OSCIN, and PORRST pins; the VIH here does not apply to the OSCIN, and RST pins; For RST and PORRST exceptions, see Section 5.1. Parameter does not apply to input-only or output-only pins. Maximum currents are measured using a system-level test case. This test case exercises all of the device peripherals concurrently (excluding MBIST and STC LBIST). Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 33 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, Q Version(1)(2) (continued) PARAMETER TEST CONDITIONS ICCIOR ICCAD TYP MAX VCCIOR IO and digital supply current (operating mode, internal regulator enabled) 120 VCCIOR IO and digital supply current (LBIST execution, internal regulator enabled) (7) HCLK = 80 MHz, VCLK = 80 MHz, STCCLK = 40 MHz, No DC load, VCCIOR = 3.6 V (6) 170 VCCIOR IO and digital supply current (MBIST execution, internal regulator enabled) (8) HCLK = 80 MHz, VCLK = 80 MHz, No DC load, VCCIOR = 3.6 V (6) 180 VCCIOR IO and digital supply current (doze mode, internal regulator enabled) No DC load, VCCIOR = 3.6 V (6) (9) 2 (10) VCCIOR IO and digital supply current (sleep mode, internal regulator enabled) No DC load, VCCIOR = 3.6 V (6) (9) 200 (10) VCCAD supply current (operating mode) All frequencies, VCCAD = 3.6 V (11) 8 VCCP = 3.6 V read operation(5) 10 VCCP = 3.6 V program (11) 75 VCCP = 3.6 V erase 75 VCCIOR + VCCAD + VCCP total digital supply current (operating mode, internal regulator enabled) HCLK = 80 MHz, VCLK = 80 MHz, No DC load, VCCIOR = 3.6 V(5)(6) 135 VCCIOR + VCCAD + VCCP total digital supply current (doze mode, internal regulator enabled) No DC load, VCCIOR = 3.6 V(6)(9) ICCP VCCP pump supply current ICCTOTAL MIN HCLK = 80 MHz, VCLK = 80 MHz, No DC load, VCCIOR = 3.6 V (5) (6) (12) VCCIOR + VCCAD + VCCP total digital supply No DC load, VCCIOR current (sleep mode, internal regulator enabled) = 3.6 V(6)(9) UNIT mA µA mA mA mA 2(10) 200(10) µA CI Input capacitance 6 pF CO Output capacitance 7 pF I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO - 0.2 V. ECLK output ≤ 2 MHz. (7) LBIST current specified is peak current for the maximum supported operating clock (HCLK = 80 MHz) and STC CLK = HCLK/2. Lower current consumption can be achieved by configuring a slower STC Clock frequency. The current peak duration can last for the duration of 1 LBIST test interval. (8) MBIST currents specified are for execution of MBIST on all RAMs in parallel. Lower current consumption can be achieved by sequenced execution of MBIST on each of the RAM spaces available. (9) For Flash banks/pumps in sleep mode. (10) Typical doze and sleep currents represent measurements under nominal conditions (baseline/nominal material, 30°C, 3.3 V). (11) Assumes reading from one bank while programming the same bank. (12) Total device operating current is derived from the total ICCIOR, ICCAD, and ICCP in normal operating mode excluding MBIST and LBIST execution. It is expected that the total will be less than the sums of the values of the individual components due to statistical calculations involved in producing the specification values. (6) 34 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5 Peripheral Information and Electrical Specifications RST and PORRST Timings (13) 5.1 (13) When the VCC timing requirements for PORRST are satisfied, there are no timing requirements for VCCP. Table 5-1. Timing Requirements for PORRST (see Figure 5-1) NO. MIN MAX UNIT VCCPORL VCC low supply level when RST becomes active VCCPORH VCC high supply level when RST becomes active 1.80 V VCCIOPORL VCCIO low supply level when PORRST must be active during power up 1.1 V VCCIOPORH VCCIO high supply level when PORRST must remain active during power up and become active during power down VIL (1) VOH 1.30 V 3.0 V Low-level input voltage after VCCIOR > VCCIOPORH (2) 0.2 VCCIOR High-level output voltage after VCCIOR > VCCIOPORH 0.8 VCCIOR V V VIL(PORRST) Low-level input voltage of PORRST before VCCIOR > VCCIOPORL 3 tsu(PORRST)r Setup time, PORRST active before VCCIOR > VCCIOPORL during power up 0 ms 5 tsu(VCCIOR)r Setup time, VCCIOR > VCCIOPORL before VCC > VCCPORL 0 ms 6 th(PORRST)r Hold time, PORRST active after VCC > VCCPORH 1 ms 7 tsu(PORRST)f Setup time, PORRST active before VCC ≤ VCCPORH during power down 8 8 th(PORRST)rio Hold time, PORRST active after VCCIOR > VCCIOPORH 1 ms 9 th(PORRST)d Hold time, PORRST active after VCCIOR < VCCIORPORL 0 ms 10 tsu(PORRST)fio Setup time, PORRST active before VCC ≤ VCCIOPORH during power down 0 ns 11 tsu(VCCIO)f Setup time, VCC < VCCPORE before VCCIO < VCCIOPORL 0 ns tf(PORRST) Filter time PORRST, pulses less than MIN get filtered out; pulses greater than MAX generate a reset. 30 150 ns tf(RST) Filter time RST, pulses less than MIN get filtered out; pulses greater than MAX generate a reset. 40 150 ns (1) (2) 0.5 V µs Corresponds to PORRST. Corresponds to RST. VCCIOR VCCIOPORH VCCIOPORH VCCIOR 8 11 VCC VCCPORH 6 VCC 7 6 VCCPORH 7 10 VCCIOPORL VCCIOPORL VCCPORL VCCPORL 5 9 3 PORRST VIL(PORRST) VIL VIL VIL VIL VIL(PORRST) VCC (1.55 V) VCCP/VCCIOR (3.3 V) Note: VCC is provided by the on-chip voltage regulator during normal application run time. It is not recommended to use the device in an application with the Vreg disabled due to potential glitching issues; however, if used in this mode, the application should ensure that the specified voltage ranges for VCC are maintained. Figure 5-1. PORRST Timing Diagram Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 35 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 5-2. Switching Characteristics Over Recommended Operating Conditions for RST and PORRST (1) PARAMETER tv(RST) MAX 1024tc(OSC) Valid time, RST active (all others) VCCIOPORL (1) MIN Valid time, RST active after PORRST inactive ns 8tc(VCLK) Vccio low supply level when PORRST must be active during power-up and power-down UNIT 1.1 V MAX UNIT Specified values do NOT include rise/fall times. For rise and fall timings, see Table 5-13. Table 5-3. Internal Voltage Regulator Specifications PARAMETER MIN tD(VCCIOR)0-3 Delay time, input supply to ramp from 0 V to 3 V 12 µs tV(PORRST)L Valid time, PORRST active after input supply becomes ≥ 3.0 V 1 ms VCCIORmin(PORRST)f Minimum input voltage, when PORRST must be made active during power down or brown out 3.0 V C(VCC)core Capacitance distributed over core VCC pins for voltage regulator stability 1.2 6.0 µF ESR(max)core Total combined ESR of stabilization capacitors on core VCC pins 0 0.75 Ω 3V VCCIORmin(PORRST)f tV(PORRST)L tD(VCCIOR)0-3 VCC PORRST Figure 5-2. PORRST Timing Requirements Table 5-4. VREG Recommended Operation Conditions PARAMETER ICC VCC Load Rating CONDITIONS MIN MAX UNIT Normal mode, regulator active 0 200 mA 5 mA - µA Sleep mode, regulator active Off, enable forced off - Table 5-5. VREG Sleep-Mode Timing Characteristics (1) PARAMETER MIN MAX UNIT tnormal-sleep Transition time between normal mode and sleep mode 70 ns tsleep-normal Transition time between sleep mode and normal mode 3.5 µs (1) 36 These times only reflect VREG transition times. Times for other components are not included. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.1.1 Sequence to Wake Up from Doze Mode In doze mode, the HCLK, GCLK, VCLK, and VCLK2 are all turned off. Also, the main oscillator is the only clock source running while in doze mode. For more details on the doze mode, see the TMS470M Series Technical Reference Manual (SPNU495). Doze mode is not supported if the internal voltage regulator is disabled. The RTICLK is still active, which allows the RTI module to generate periodic wake up interrupts, if required. The other wake-up options are: external interrupts via GIO pins, CAN message, and SCI/LIN. The sequence for waking up from doze mode is described below: 1. Wake-up request is received/generated. Figure 5-3 shows the CAN module generating the wakeup interrupt. 2. This wake-up event causes the core VREG to wake up. 3. Since the main oscillator is running already it is used as the clock source upon wake up. 4. The software runs using the main oscillator as the clock source. Also, the PLL can now be enabled. 5. Once the PLL has acquired LOCK, the software can switch over to using the PLL output clock for normal operation. Ready for Normal Operation/CAN Message 8 MHz CrystalOscillator with PLL On-Chip VREG Wake up CPU ON OFF e.g., CAN Module Wake up VREG CPU Update Status and Prepare for Normal Operation Figure 5-3. Wake Up From Doze Mode Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 37 TMS470MF06607 SPNS157C – JANUARY 2012 5.1.2 www.ti.com Sequence to Wake Up from Sleep Mode In sleep mode, all the clocks are turned off: HCLK, GCLK, VCLK, VCLK2, and RTICLK. All the clock sources are also disabled. For more details on sleep mode, see the TMS470M Series Technical Reference Manual (SPNU495). Sleep mode is not supported if the internal voltage regulator is disabled. The wake-up options are: external interrupts via GIO pins, CAN, and SCI/LIN. The sequence for waking up from the sleep mode is described below: 1. Wake-up request is received/generated. Figure 5-4 shows the CAN module generating the wake-up interrupt based on a message received. 2. This wake-up event causes the on-chip VREG to wake up. 3. Once the on-chip VREG wakes up, the CPU and the main oscillator start to wake up. 4. Once the main oscillator output is valid, the software runs using the main oscillator as the clock source. The software can prepare for normal operation. Also, now the PLL can be enabled. 5. Once the PLL has acquired LOCK, the software can switch over to using the PLL output clock for normal operation. Startup to Normal Operation ~2 ms, depending on xtal Ready for Normal Operation/CAN Message 8 MHz CrystalOscillator with PLL OFF Wake up oscillator ON On-Chip VREG Wake up CPU OFF Wake up VREG e.g., CAN Module CPU Start Oscillator Update Status and Prepare for Normal Operation Figure 5-4. Wake Up From Sleep Mode 38 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 5-6. Summary of Wake Up from Low-Power Modes (1) MODE CLOCK SOURCE ACTIVE ACTIVE CLOCKS WAKE-UP OPTIONS WAKE-UP CLOCK SOURCE WAKE-UP TIMES Doze Oscillator RTICLK1 GIO interrupts, CAN Rx, Oscillator SCI/LIN Rx, RTI VREG wake up (2) + flash pump sleep (3) + flash pump standby (4) Sleep None None GIO interrupts, CAN Rx, Oscillator SCI/LIN Rx VREG wakeup + Osc. startup + 1024 Osc. cycles + flash pump sleep + flash pump standby (1) (2) (3) (4) Low-power modes are not supported if the internal voltage regulator is disabled. VREG wake up = thalt-normal (see Table 5-4). Flash pump sleep = minimum time for which the flash pump is in sleep mode before it enters standby mode = 20 µs. The flash pump sleep to standby counter must be programmed such that the (counter value X wake-up clock source period) is at least 20 µs. Flash pump standby = minimum time for which the flash pump is in standby mode before it enters active mode = 1 µs. The flash pump standby2active counter must be programmed such that the (counter value X wake-up clock source period) is at least 1 µs. NOTE The flash banks will wake up in parallel with the flash pump. The flash banks can wake up faster than the flash pump and therefore the overall flash module wake-up time is determined by the pump wake-up time. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 39 TMS470MF06607 SPNS157C – JANUARY 2012 5.2 www.ti.com PLL and Clock Specifications Table 5-7. Timing Requirements for PLL Circuits Enabled or Disabled MIN MAX UNIT f(OSC) Input clock frequency PARAMETER 5 20 MHz tc(OSC) Cycle time, OSCIN 50 ns tw(OSCIL) Pulse duration, OSCIN low 15 ns tw(OSCIH) Pulse duration, OSCIN high 15 ns 5.2.1 External Reference Resonator/Crystal Oscillator Clock Option The oscillator is enabled by connecting the appropriate fundamental 5-20 MHz resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5-5(a). The oscillator is a single stage inverter held in bias by an integrated bias resistor. TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. Vendors are equipped to determine which load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. 5.2.2 External Clock Source An external oscillator source can be used by connecting a 1.5-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 5-5(b). OSCIN C1 (A) OSCOUT Crystal C2 OSCIN (A) External Clock Signal (toggling 0-1.5 V) (a) A. OSCOUT (b) The values of C1 and C2 should be provided by the resonator/crystal vendor. Figure 5-5. Recommended Crystal/Clock Connection 40 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.2.3 LPO and Clock Detection The LPOCLKDET module consists of a clock monitor (CLKDET) and 2 low-power oscillators (LPO): a low-frequency (LF) and a high-frequency (HF) oscillator. The CLKDET is a supervisor circuit for an externally supplied clock signal. In case the externally supplied clock frequency falls out of a frequency window, the clock detector flags this condition and switches to the HF LPO clock (limp mode). The OSCFAIL flag and clock switch-over remain, regardless of the behavior of the oscillator clock signal. The only way OSCFAIL can be cleared (and OSCIN be again the driving clock) is a power-on reset. Table 5-8. LPO and Clock Detection invalid frequency PARAMETER MIN MAX UNIT Lower threshold 1.5 5.0 MHz Higher threshold 20.0 50.0 MHz 14.0 MHz limp mode frequency (HFosc) TYP 9.0 12 LFosc frequency 79 90 110 kHz HFosc frequency 9.0 12 14.0 MHz lower threshold guaranteed fail 1.5 upper threshold guaranteed pass 5.0 20.0 guaranteed fail 50.0 f (MHz) Figure 5-6. LPO and Clock Detection Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 41 TMS470MF06607 SPNS157C – JANUARY 2012 5.2.4 www.ti.com Device Clock Domains Block Diagram The clock domains block diagram and GCM clock source assignments are given in and Table 5-9. OSCOUT OSCIN (5-20 MHz) 0 OSC FMZPLL /1..64 x92..184 /1..8 /1..32 GCLK (to CPU) 4 5 HCLK (to SYSTEM) (A) LF OSC HF OSC LPO (A) 1 /1,2,4,8 (A) RTICLK (to RTI) /1..16 VCLK (to Peripherals) (A) /1..16 (A) VCLK2 (to HET) AVCLK1 24 /1,2..256 /2,3..2 24 /2,3..2 /1,2..256 HRP /1..64 /1,2..65536 ECLK £ 20 MHz /1,..1024 Prop_ seg Phase_ seg2 Phase_ seg1 SPI Baud Rate £ VCLK/2 SCI Baud Rate £ 115.2 kB/s LIN Baud Rate £ 20 kB/s ADCLK £ 20 MHz LRP 0 5 /2 ..2 MibSPI1, MibSPI2 SCI SCI Baud Rate £ 115.2 kB/s ADC HET Loop CLK LIN/SCI HET HiRes CLK External Clock HET CAN Baud Rate £ 1M Baud 8-MHz OSCIN CAN (DCAN1, DCAN2) A. See Table 5-10. Figure 5-7. Device Clock Domains Block Diagram Table 5-9. GCM Clock Source Assignments (1) 42 GCM SOURCE NUMBER CLOCK SOURCE 0 OSCIN 1 F035 FMzPLL 2 Reserved (1) 3 Reserved (1) 4 LF OSC 5 HF OSC 6 Reserved (1) 7 Reserved (1) ‘Reserved’ clock sources should not be enabled or used. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 5-10. Switching Characteristics Over Recommended Operating Conditions for Clocks (1) (2) (3) (4) (5) TEST CONDITIONS (6) PARAMETER (1) (2) (3) (4) (5) (6) MIN MAX Pipeline mode enabled 80 Pipeline mode disabled, 0 flash wait states 28 f(HCLK) System clock frequency f(PROG/ERASE) System clock frequency Flash programming/erase 80 f(VCLK/VCLK2) Peripheral VBUS clock frequency f(HCLK) f(ECLK) External clock output frequency for ECP Module 20 f(RCLK) RCLK - Frequency out of PLL macro into R-divider 180 tc(HCLK) Cycle time, system clock tc(PROG/ERASE) Cycle time, system clock - Flash programming/erase 12.50 tc(VCLK/VCLK2) Cycle time, peripheral clock tc(HCLK) tc(ECLK) Cycle time, ECP module external clock output 50.0 tc(RCLK) Cycle time, minimum input cycle time for the R- divider (RCLK) 5.56 Pipeline mode enabled 12.50 Pipeline mode disabled, 0 flash wait states 35.71 UNIT MHz MHz MHz MHz MHz ns ns ns ns ns f(HCLK) = f(OSC) / NR *NF /ODPLL/PLLDIV; for details, see the PLL documentation. TI strongly recommends selection of NR and NF parameters such that NF ≤ 120 and (f(OSC) / NR *NF) ≤ 400. f(VCLK) = f(HCLK) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the peripheral VBUS clock divider ratio determined by the VCLKR[3:0] bits in the SYS module. Enabling FM mode can reduce maximum rated operating frequencies. The degree of impact is application-specific and the specific settings, as well as the impact of the settings, should be discussed and agreed upon prior to using FM modes. Use of FM modes do not impact the maximum rated external clock output, f(ECLK), for the ECP module. Pipeline mode enabled or disabled is determined by FRDCNTL[2:0]. f(ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCTRL.[15:0] register bits in the ECP module. ECLK output will increase radiated emissions within the system that is used. Rated emissions at the device level do not include emissions due to ECLK output. All test conditions assume FM Mode disabled and RAM ECC enabled with 0 waitstates for RAM. RAM 0 Address Waitstates 0MHz f(HCLK) Data Waitstates 0 f(HCLK) 0MHz Flash 0 Address Waitstates 0MHz Data Waitstates f(HCLK) 0 0MHz 2 1 28MHz 56MHz f(HCLK) Figure 5-8. Timing - Wait States NOTE If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not exceeded. The speed of the device clocks may need be derated to accommodate the modulation depth when FMzPLL frequency modulation is enabled. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 43 TMS470MF06607 SPNS157C – JANUARY 2012 5.2.4.1 www.ti.com ECLK Specification Table 5-11. Switching Characteristics Over Recommended Operating Conditions for External Clocks (1) (2) (see Figure 5-9) NO. PARAMETER TEST CONDITIONS MIN MAX UNIT 1 tw(EOL) Pulse duration, ECLK low Under all prescale factor combinations (X and N) 0.5tc(ECLK) - tf ns 2 tw(EOH) Pulse duration, ECLK high Under all prescale factor combinations (X and N) 0.5tc(ECLK) - tr ns (1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the SYS module. N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the SYS module. (2) 2 ECLK 1 Figure 5-9. ECLK Timing Diagram 5.2.5 JTAG Timing Table 5-12. JTAG Scan Interface Timing (JTAG Clock specification 10-MHz and 50-pF Load on TDO Output) (see Figure 5-10 NO. MIN MAX UNIT 1 tc(JTAG) Cycle time, JTAG low and high period 50 ns 2 tsu(TDI/TMS - TCKr) Setup time, TDI, TMS before TCK rise (TCKr) 5 ns 3 th(TCKr -TDI/TMS) Hold time, TDI, TMS after TCKr 5 ns 4 th(TCKf -TDO) Hold time, TDO after TCKf 5 5 td(TCKf -TDO) Delay time, TDO valid after TCK fall (TCKf) ns 45 ns TCLK 1 1 TMS TDI 2 3 TDO 4 5 Figure 5-10. JTAG Scan Timings 44 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.2.6 Output Timings Table 5-13. Switching Characteristics for Output Timings Versus Load Capacitance (CL) (1) (see Figure 5-11) PARAMETER tr tf (1) MAX Adaptive impedance 4 mA pins Adaptive impedance 4 mA pins CL = 15 pF 4 CL = 50 pF 8 CL = 100 pF 15 CL = 150 pF 21 CL = 15 pF 5 CL = 50 pF 8 CL = 100 pF 12 CL = 150 pF 17 UNIT ns ns Peripheral output timings given within this document are measured in either standard buffer or impedance control mode. tr tf VCCIO 80% 80% Output 20% 20% 0 Figure 5-11. CMOS-Level Outputs 5.2.7 Input Timings Table 5-14. Timing Requirements for Input Timings (1) (see Figure 5-12) MIN tpw (1) Input minimum pulse width MAX tc(VCLK) + 10 UNIT ns tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK). tpw 80% VCC 80% Input 20% 20% 0 Figure 5-12. CMOS-Level Inputs Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 45 TMS470MF06607 SPNS157C – JANUARY 2012 5.2.8 www.ti.com Flash Timings Table 5-15. Timing Requirements for Program Flash tacc_delay tprog(16-bit) tprog(Total) terase(sector) Nwec (1) (2) (3) 46 PARAMETER TEST CONDITIONS MIN Flash pump stabilization time From Sleep Mode to Standby Mode 20 From Standby Mode to Active Mode 1 From Sleep Mode to Standby Mode 1.9 From Standby Mode to Active Mode 0.1 Flash bank stabilization time NOM MAX UNIT µs Half-word (16-bit) programming time 37.5 300 512k-byte programming time (1) 10 78.7 640-k-byte programming time (1) 12.5 98.4 Sector erase time 1.5 µs s 15 s Write/erase cycles at TA = -40 to125°C with 15-year Data Retention requirement 1000 (2) cycles Write/erase cycles at TA = -40 to 125°C EEPROM emulation requirement for 16k flash sectors in Bank 1 25000 (2) (3) cycles tprog(Total) programming time includes overhead of state machine, but does not include data transfer time. Flash write/erase cycles and data retention specifications are based on a validated implementation of the TI flash API. Non-TI flash API implementation is not supported. For detailed description see the F035 Flash Validation Procedure (SPNA127). Flash write/erase cycle and data retention specifications are based on an assumed distribution of write/erase cycles over the life of the product including and even distribution over the rated temperature range and time between cycles. The EEPROM emulation bank has been qualified as outlined in the JEDEC specification JESD22-A117C. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.3 SPIn Master Mode Timing Parameters Table 5-16. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 5-13 and Figure 5-14) NO. 1 MIN 4 5 6 7 Cycle time, SPICLK 90 256tc(VCLK) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 td(SIMO-SPCL)M Delay time, SPISIMO data valid before SPICLK low (clock polarity = 0) 0.5tc(SPC)M - 15 td(SIMO-SPCH)M Delay time, SPISIMO data valid before SPICLK high (clock polarity = 1) 0.5tc(SPC)M - 15 tv(SPCL-SIMO)M Valid time, SPISIMO data valid (clock polarity = 0) 0.5tc(SPC)M - tf(SPC) tv(SPCH-SIMO)M Valid time, SPISIMO data valid (clock polarity = 1) 0.5tc(SPC)M - tr(SPC) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) 4 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) 4 th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) 8 th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) 8 (5) (5) (5) (5) (5) 8 (5) (6) (C2TDELAY+CSHOLD+2)* tc(VCLK) - tf(SPICS) + tr(SPICLK)-6 (C2TDELAY+CSHOLD+ 2)*tc(VCLK) - tf(SPICS) + tr(SPICLK)+38 Setup time CS active until SPICLK low (clock polarity = 1) (C2TDELAY+CSHOLD+2)* tc(VCLK) - tf(SPICS) + tf(SPICLK)-6 (C2TDELAY+CSHOLD+ 2)*tc(VCLK) - tf(SPICS) + tf(SPICLK)+38 Hold time SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPICLK) + tr(SPICS)-28 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPICLK) + tr(SPICS)+8 Hold time SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPICLK) + tr(SPICS)-28 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPICLK) + tr(SPICS)+8 C2TDELAY * tc(VCLK) tf(SPICS) C2TDELAY *tc(VCLK) tC2TDELAY tT2CDELAY (1) (2) (3) (4) (5) (6) tSPIENA SPIENAn sample point UNIT ns Setup time CS active until SPICLK high (clock polarity = 0) 9 (5) (6) 10 (6) MAX tc(SPC)M 2 (5) 3 (4) ns The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear. tc(VCLK) = interface clock cycle time = 1 / f(VCLK). For rise and fall timings, see Table 5-13. When the SPI is in Master mode, the following must be true: • For PS values from 1 to 255: t ≥ (PS +1)tc(VCLK) ≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. • For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 90 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY are programmed in the SPIDELAY register. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 47 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 5-13. SPI Master Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) SPISIMO Master Out Data is Valid 8 9 SPICSn 10 SPIENAn Figure 5-14. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0) 48 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 5-17. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (1) (2) (3) (see Figure 5-15 and Figure 5-16) NO. 1 2 (5) 3 (5) 4 5 6 7 90 256tc(VCLK) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M - tf 0.5tc(SPC)M + 5 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M - tr 0.5tc(SPC)M + 5 td(SIMO-SPCH)M Delay time, SPISIMO data valid before SPICLK high (clock polarity = 0) 0.5tc(SPC)M - 15 td(SIMO-SPCL)M Delay time, SPISIMO data valid before SPICLK low (clock polarity = 1) 0.5tc(SPC)M - 15 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M - tr(SPC) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M - tf(SPC) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) 4 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) 4 th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 0) 8 th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low (clock polarity = 1) 8 (5) (5) 10 (7) (5) (6) (7) Cycle time, SPICLK (5) 9 (5) (6) MAX tc(SPC)M (5) 8 (5) (6) (1) (2) (3) (4) MIN (4) (C2TDELAY+CSHOLD+ 2)*tc(VCLK)+0.5*tc(SPC)M tf(SPICS) + tr(SPICLK)-6 (C2TDELAY+CSHOLD+ 2)*tc(VCLK)+0.5*tc(SPC)M tf(SPICS) + tr(SPICLK)+38 Setup time CS active until SPICLK low (clock polarity = 1) (C2TDELAY+CSHOLD+ 2)*tc(VCLK)+0.5*tc(SPC)M tf(SPICS) + tf(SPICLK)-6 (C2TDELAY+CSHOLD+ 2)*tc(VCLK)+0.5*tc(SPC)M tf(SPICS) + tf(SPICLK)+38 Hold time SPICLK low until CS inactive (clock polarity = 0) T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPICLK) + tr(SPICS)-28 T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPICLK) + tr(SPICS)+8 Hold time SPICLK high until CS inactive (clock polarity = 1) T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPICLK) + tr(SPICS)-28 T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPICLK) + tr(SPICS)+8 C2TDELAY * tc(VCLK) tf(SPICS) C2TDELAY * tc(VCLK) tT2CDELAY tSPIENA ns Setup time CS active until SPICLK high (clock polarity = 0) tC2TDELAY SPIENAn Sample Point UNIT ns he MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear. tc(VCLK) = interface clock cycle time = 1 / f(VCLK). For rise and fall timings, see Table 5-13. When the SPI is in Master mode, the following must be true: • For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. • For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 90 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). C2TDELAY and T2CDELAY is programmed in the SPIDELAY register. C2TDELAY and T2CDELAY is programmed in the SPIDELAY register. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 49 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Data Valid Master Out Data is Valid 6 7 Master In Data Must Be Valid SPISOMI Figure 5-15. SPI Master Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) SPISIMO Master Out Data is Valid 8 9 SPICSn 10 SPIENAn Figure 5-16. SPI Master Mode Chip Select timing (CLOCK PHASE = 1) 50 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.4 SPIn Slave Mode Timing Parameters Table 5-18. SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 5-17 and Figure 5-18) NO. 1 2 (6) 3 (6) 4 (6) 5 Cycle time, SPInCLK tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 0) 30 tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 1) 30 tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 0) 30 tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 1) 30 td(SPCH-SOMI)S Delay time, SPInCLK high to SPInSOMI valid (clock polarity = 0) trf(SOMI)+15 td(SPCL-SOMI)S Delay time, SPInCLK low to SPInSOMI valid (clock polarity = 1) trf(SOMI)+15 tv(SPCH-SOMI)S Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) 0 tv(SPCL-SOMI)S Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) 0 tsu(SIMO-SPCL)S Setup time, SPInSIMO before SPInCLK low (clock polarity = 0) 4 tsu(SIMO-SPCH)S Setup time, SPInSIMO before SPInCLK high (clock polarity = 1) 4 tv(SPCL-SIMO)S Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0) 6 tv(SPCH-SIMO)S Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1) 6 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) (6) 8 9 (1) (2) (3) (4) (5) (6) MAX tc(SPC)S (6) 6 (6) 7 MIN (5) UNIT 90 ns tf(ENAn)+6 ns ns The MASTER bit (SPIGCR1.0) is clear and the CLOCK PHASE bit (SPIFMTx.16) is clear. When the SPI is in Slave mode, the following must be true: tc(SPC)S > 2tc(VCLK) and tc(SPC)S ≥ 90 ns. For rise and fall timings, see Table 5-13. tc(VCLK) = interface clock cycle time = 1 / f(VCLK). When the SPI is in Slave mode, the following must be true: tw(SPCL)S > tc(VCLK), tw(SPCL)S ≥ 30, tw(SPCH)S > tc(VCLK) ns and tw(SPCH)S ≥ 30 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 51 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISOMI Data is Valid SPISOMI 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 5-17. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) 8 SPIENAn 9 SPICSn Figure 5-18. SPI Slave Mode Enable Timing (CLOCK PHASE = 0) 52 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com Table 5-19. SPIn Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output) (1) (2) (3) (4) (see Figure 5-19 and Figure 5-20) NO. 1 MIN (5) MAX UNIT tc(SPC)S Cycle time, SPInCLK tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 0) 30 tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 1) 30 tw(SPCL)S Pulse duration, SPInCLK low (clock polarity = 0) 30 tw(SPCH)S Pulse duration, SPInCLK high (clock polarity = 1) 30 tv(SPCH-SOMI)S Delay time, SPInSOMI data valid after SPInCLK high (clock polarity = 0) trf(SOMI)+15 tv(SPCL-SOMI)S Delay time, SPInSOMI data valid after SPInCLK low (clock polarity = 1) trf(SOMI)+15 tv(SOMI-SPCH)S Valid time, SPInCLK high after SPInSOMI data valid (clock polarity = 0) 0 tv(SOMI-SPCL)S Valid time, SPInCLK low after SPInSOMI data valid (clock polarity = 1) 0 tsu(SIMO-SPCH)S Setup time, SPInSIMO before SPInCLK high (clock polarity = 0) 4 tsu(SIMO-SPCL)S Setup time, SPInSIMO before SPInCLK low (clock polarity = 1) 4 tv(SPCH-SIMO)S Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0) 6 tv(SPCL-SIMO)S Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1) 6 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+ tr(ENAn) 9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn)+6 ns 10 td(SCSL-SOMI)S Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) trf(SOMI)+6 ns 2 (6) 3 (6) 4 (6) 5 (6) 6 (6) 7 (6) 8 (1) (2) (3) (4) (5) (6) 90 ns ns The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set. When the SPI is in Slave mode, the following must be true: tc(SPC)S > 2tc(VCLK) and tc(SPC)S ≥ 90 ns. For rise and fall timings, see Table 5-13. tc(VCLK) = interface clock cycle time = 1 /f(VCLK). When the SPI is in Slave mode, the following must be true: tw(SPCL)S > tc(VCLK), tw(SPCL)S ≥ 30 ns, tw(SPCH)S > tc(VCLK) and tw(SPCH)S ≥ 30 ns. The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 53 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISOMI Data is Valid SPISOMI Data Valid 6 7 SPISIMO Data Must Be Valid SPISIMO Figure 5-19. SPI Slave Mode External Timing (CLOCK PHASE = 1) SPICLK (clock polarity = 0) SPICLK (clock polarity = 1) 8 SPIENAn 9 SPICSn 10 SPISOMI Slave Out is Valid Figure 5-20. SPI Slave Mode Enable Timing (CLOCK PHASE = 1) 54 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.5 CAN Controller (DCANn) Mode Timings Table 5-20. Dynamic Characteristics for the CANnSTX and CANnSRX Pins MAX UNIT td(CANnSTX) Delay time, transmit shift register to CANnSTX pin (1) PARAMETER 15 ns td(CANnSRX) Delay time, CANnSRX pin to receive shift register 6 ns MAX UNIT (1) 5.6 MIN These values do not include rise/fall times of the output buffer. High-End Timer (HET) Timings Table 5-21. Dynamic Characteristics for the HET Pins PARAMETER topw(HET) tipw(HET) (1) (2) MIN Output pulse width, this is the minimum pulse width that can be generated (1) Input pulse width, this is the minimum pulse width that can be captured (2) 1/f(VCLK2) ns 1/f(VCLK2) ns topw(HET)min = HRP(min) = hr(min) / VCLK2. tipw(HET) = LRP(min) = hr(min) * lr(min) / VCLK2. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 55 TMS470MF06607 SPNS157C – JANUARY 2012 5.7 www.ti.com Multi-Buffered A-to-D Converter (MibADC) The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO unless otherwise noted. Resolution 10 bits (1024 values) Monotonic Assured 00h to 3FFh [00 for VAI ≤ ADREFLO; 3FF for VAI ≥ ADREFHI] Output conversion code Table 5-22. MibADC Recommended Operating Conditions (1) ADREFHI A-to-D high -voltage reference source ADREFLO A-to-D low-voltage reference source VAI Analog input voltage IAIC Analog input clamp current (2) (VAI < VSSAD - 0.3 or VAI > VCCAD + 0.3) (1) (2) MIN MAX UNIT 3.0 VCCAD V VSSAD 0.3 V ADREFLO ADREFHI V -2 2 mA For VCCAD and VSSAD recommended operating conditions, see Section 4.2. Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels. Table 5-23. MibADC Operating Characteristics Over Full Range of Recommended Operating Conditions (1) NOM MAX UNIT Rmux Analog input mux on-resistance PARAMETER DESCRIPTION/CONDITIONS See Figure 5-21 125 1.5K Ω Rsamp ADC sample switch on-resistance See Figure 5-21 150 1.5K Ω Cmux Input mux capacitance See Figure 5-21 16 pF Csamp ADC sample capacitance See Figure 5-21 8 pF IAIL Analog input leakage current Input leakage per ADC input pin IADREFHI ADREFHI input current ADREFHI = 3.6 V, ADREFLO = VSSAD CR Conversion range over which specified accuracy is maintained ADREFHI - ADREFLO EDNL Differential non-linearity error EINL ETOT (1) 56 MIN -200 200 nA 5 mA 3.6 V Difference between the actual step width and the ideal value (see Figure 5-22). ±2 LSB Integral non-linearity error Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error (see Figure 5-23). ±2 LSB Total error/Absolute accuracy Maximum value of the difference between an analog value and the ideal midstep value (see Figure 5-24). ±2 LSB 3 1 - LSB = (ADREFHI – ADREFLO)/ 210 for the MibADC. Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 5.7.1 MibADC Input Model Pin Pin Smux Rmux Smux Rmux IAIL Pin IAIL Smux Rmux IAIL IAIL Ssamp Rsamp Cmux Csamp Figure 5-21. MibADC Input Equivalent Circuit Table 5-24. Multi-Buffer ADC Timing Requirements PARAMETER MIN tc(ADCLK) Cycle time, MibADC clock 0.05 µs td(SH) Delay time, sample and hold time 1 µs td(C) Delay time, conversion time 0.55 µs td(SHC) (1) Delay time, total sample/hold and conversion time 1.55 µs (1) NOM MAX UNIT This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors. Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 57 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com The differential non-linearity error shown in Figure 5-22 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB. 0 ... 110 Digital Output Code 0 ... 101 0 ... 100 0 ... 011 Differential Linearity Error (1/2 LSB) 1 LSB 0 ... 010 0 ... 001 Differential Linearity Error (-1/2 LSB) 1 LSB 0 ... 000 1 0 A. 2 3 4 5 Analog Input Value (LSB) 1 LSB = (ADREFHI – ADREFLO)/210 Figure 5-22. Differential Non-linearity (DNL) The integral non-linearity error shown in Figure 5-23 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. 0 ... 111 Digital Output Code 0 ... 110 Ideal Transition 0 ... 101 0 ... 100 Actual Transition 0 ... 011 0 ... 010 At Transition 011/100 (-1/2 LSB) End-Point Lin. Error 0 ... 001 At Transition 001/010 (-1/4 LSB) 0 ... 000 0 A. 1 2 3 4 5 Analog Input Value (LSB) 6 7 1 LSB = (ADREFHI – ADREFLO)/210 Figure 5-23. Integral Non-linearity (INL) Error The absolute accuracy or total error of an MibADC as shown in Figure 5-24 is the maximum value of the difference between an analog value and the ideal midstep value. 58 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 Copyright © 2012, Texas Instruments Incorporated TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 0 ... 111 Digital Output Code 0 ... 110 0 ... 101 0 ... 100 Total Error At Step 0 ... 101 (-1 1/4 LSB) 0 ... 011 0 ... 010 Total Error at Step 0 ... 001 (1/2 LSB) 0 ... 001 0 ... 000 0 A. 1 2 3 4 5 Analog Input Value (LSB) 6 7 1 LSB = (ADREFHIµ – ADREFLO)/210 Figure 5-24. Absolute Accuracy (Total) Error Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 59 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 6 Revision History This data sheet revision history highlights the technical changes made to the device or the datasheet. Date October 2010 Additions, Deletions, And Modifications Revision Updated the MibADC Input Equivalent Circuit illustration. Renamed f(PLLDIV) to f(RCLK). Fixed the formulas in SPI timing, including item 4,5,8,9,10 in master mode, and item 1,2,3 and footnotes in slave mode. Removed slew rate control description, renamed low EMI buffer to adaptive impedance 4 mA buffer. A Swapped DCAN1 and DCAN0 RAM Map. Removed VIH of PORRST pin from section 5.1 RST and PORRST timings. Changed the footnotes in the Electrical characterization section so that the VIH of general IO pins also applies to PORRST pin. Added a new section "Terms and Acronyms". August 2011 Fixed the Device ID in . B Added descriptions for the ENZ pin. January 2012 Added maximum programming time specifications to Flash Timings table. Added note to clarify application use and qualification methodology of EEPROM emulation bank in Flash Timings table. 60 Revision History C Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 TMS470MF06607 SPNS157C – JANUARY 2012 www.ti.com 7 Mechanical Data 7.1 Thermal Data Table 7-1 show the thermal resistance characteristics for the PQFP - PZ mechanical packages. Table 7-1. Thermal Resistance Characteristics (S-PQFP Package) [PZ] 7.2 PARAMETER °C/W RθJA 48 RθJC 5 Packaging Information The following packaging information reflects the most current released data available for the designated device. This data is subject to change without notice and without revision of this document. Mechanical Data Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS470MF06607 61 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) S4MF06607BSPZQQ1 ACTIVE LQFP PZ 100 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 S4MF06607BSPZ TMS470 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of