SCAN12100TYA

SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement ■ DCM also measures chip and other delays to ≤ ± 1200 ps General Description The SCAN12100 is a 1228.8 and 614.4 Mbps serializer/deseralizer (SerDes) for high-speed bidirectional serial data transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. The SCAN12100 integrates precision delay calibration measurement (DCM) circuitry that measures link delay components to better than ± 800 ps accuracy. The SCAN12100 features independent transmit and receive PLLs, on-chip oscillator, and intelligent clock management circuitry to automatically perform remote radio head synchronization and reduce the cost and complexity of external clock networks. The SCAN12100 is programmable though an MDIO interface as well as through pins, featuring configurable transmitter deemphasis, receiver equalization, speed rate selection, internal pattern generation/verification, and loop back modes. In addition to at-speed BIST, the SCAN12100 includes IEEE 1149.1 and 1149.6 testability. Features ■ ■ ■ ■ Exceeds LV and HV CPRI voltage and jitter requirements 1228.8, and 614.4 Mbps operation Pin and package compatibility with the SCAN25100 Integrated delay calibration measurement (DCM) directly measures T14 and Toffset delays to ≤ ± 800 ps ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ accuracy Deterministic chip latency Independent transmit and receive PLLs for seamless RE synchronization Low noise recovered clock output Requires no jitter cleaning in single-hop applications >8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV CDM Hot plug protection LOS, LOF, 8b/10b line code violation, comma, and receiver PLL lock reporting Programmable hyperframe length and start of hyperframe character Programmable transmit de-emphasis and receive equalization with on-chip termination Advanced testability features — IEEE 1149.1 and 1149.6 — At-speed BIST pattern generator/verifier — Multiple loopback modes 1.8V or 3.3V compatible parallel bus interface 100-pin TQFP package with exposed dap Industrial –40 to +85° C temperature range Block Diagram 20209542 © 2008 National Semiconductor Corporation 202095 www.national.com SCAN12100 1228.8 and 614.4 Mbps CPRI SerDes May 19, 2008 SCAN12100 Pin Diagram SCAN12100 20209502 (Top View) 100–Pin TQFP with Exposed Ground Pad Order Number SCAN12100TYA See NS Number VXF100B www.national.com 2 SCAN12100 Pin Descriptions Pin # Pin Name I/O, Type Description HIGH SPEED DIFFERENTIAL I/O 12 11 DOUTP DOUTN O, CML Inverting and non-inverting high speed CML differential outputs of the serializer. Onchip termination resistors connect from DO+ and DO− to an internal reference 18 17 RINP RINN I, CML Inverting and non-inverting high speed differential inputs of the deseralizer. On-chip termination resistors connect from RI+ and RI− to an internal reference. On-chip termination resistors are configured for AC-coupled applications. PARALLEL DATA BUS 65 66 67 68 69 70 71 72 73 74 DIN [0] DIN [1] DIN [2] DIN [3] DIN [4] DIN [5] DIN [6] DIN [7] DIN [8] DIN [9] I, LVTTL or 1.8V Transmit data word. LVCMOS Internal   pull down In 10-bit mode, the 10-bit code-group at DIN [0–9] is serialized with the internal 8b/ 10b encoder disabled. Bit 9 is the msb.   In 8-bit mode, DIN [0-7] is first converted into 10-bit code-group by the internal 8b/10b encoder before it is serialized. Bit 7 is the msb. DIN [8] is used as K-code select pin and DIN[9] should be tied Low. When DIN [8] is low, DIN [0-7] is mapped to the corresponding 10-bit D-group. When DIN [8] is high, DIN [0-7] is mapped to the corresponding 10-bit K-group. The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 53 54 55 56 57 58 59 60 61 62 ROUT [0] ROUT [1] ROUT [2] ROUT [3] ROUT [4] ROUT [5] ROUT [6] ROUT [7] ROUT [8] ROUT [9] O, LVTTL or 1.8V Deserialized receive data word. LVCMOS Internal   pull down In 10-bit mode, ROUT [0-9] is the deserialized received data word in 10-bit code group. Bit 9 is the msb.   In 8-bit mode, ROUT [0-7] is the deserialized received data byte. Bit 7 is the msb. ROUT [8] is the K-group indicator. A low at ROUT [8] indicates ROUT [0-7] belongs to the D-group, while a high indicates it belongs to the K-group. ROUT [9] is the line code violation (LCV) indicator. ROUT [9] is high for one ROUT cycle when a line code violation occurs. The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 CLOCK SIGNALS 6 7 REFCLKP REFCLKN I, LVDS or LVPECL 64 TXCLK I, LVTTL or 1.8V Transmit clock. TXCLK must be synchronous to REFCLK to avoid FIFO under/ LVCMOS Internal overflow though it may differ in phase. pull down 52 RXCLK I/O, LVTTL or 1.8V Write mode: RXCLK is recovered clock output pin. LVCMOS   Read mode: RXCLK is an input pin. ROUT [9:0] are latched out on RXCLK rising and falling edges. RXCLK must be synchronous to the incoming serial data to avoid FIFO over/underflow, though it may differ in phase. See RXCLKMODE pin description for more details. 22 23 SYSCLKP SYSCLKN O, LVDS Inverting and non-inverting differential serializer reference clock. A low jitter clock source should be connected to REFCLKP & REFCLKN. 30.72 MHz output clock. (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V Receiver CPRI loss of signal (LOS) status (8-bit mode only). LVCMOS   0 = signal detected (per CPRI standard) 1 = signal lost (per CPRI standard)   See “LOS Detection” under “Functional Description” for more details. 77 LOCKB O, LVTTL or 1.8V Receiver PLL lock status LVCMOS 0 = Receiver PLL locked 1 = Receiver PLL not locked 3 www.national.com SCAN12100 Pin # 79 Pin Name CDET I/O, Type Description O, LVTTL or 1.8V Comma Detect. LVCMOS 0 = no comma yet detected in the incoming serial stream or receiver PLL not locked.   1 = the receiver PLL is locked and a positive or negative comma bit sequence detected in the incoming bit stream. The serial to parallel converter is aligned to the proper 10bit word boundary when comma alignment is enabled (CALIGN_EN = 1). CONTROL PINS 82 81 88 89 PE [0] PE [1] EQ [0] EQ [1] I, LVTTL or 1.8V Transmitter de-emphasis configuration. LVCMOS Internal Pulling both pins low enables MDIO control, default is no de-emphasis. pull down PE1 PE0 0 0 No de-emphasis 0 1 Low de-emphasis 1 0 Medium de-emphasis 1 1 Maximum de-emphasis I, LVTTL or 1.8V Receive input equalization configuration. LVCMOS Internal Pulling both pins low enables MDIO control, default is no receive equalization. pull down EQ1 EQ0 0 0 No receive equalization 0 1 Low receive equalization 1 0 Medium receive equalization 1 1 Maximum receive equalization 90 91 TXPWDNB RXPWDNB I, LVTTL or 1.8V Power down control signals. LVCMOS Internal TXPWDNB pull down 0 = Transmitter is powered down and DOUT± pins are high impedance. 1 = Transmitter is powered up. RXPWDNB 0 = Receiver is powered down and ROUT [9:0] as well as LOS, LOCKB, CDET, RXCLK, and SYSCLK are high impedance. 1 = Receiver is powered up. 92 CALIGN_EN I, LVTTL or 1.8V Comma alignment enable. LVCMOS Internal 0 = comma alignment circuitry disabled. Receiver will not realign 10-bit data based on pull down incoming comma characters. CDET pin still flags comma detection. 1 = comma detect and alignment circuitry enabled. Receiver aligns 10-bit data to incoming comma character and flags comma detect through CDET pin. 93 RXCLKMODE I, LVTTL or 1.8V Receiver recovered clock mode LVCMOS Internal 0 = Write mode. RXCLK pin is a recovered clock output. pull down (RXCLK = output pin) 1 = Read mode. RXCLK pin is ROUT [9:0] bus read input strobe. (RXCLK = input pin) 80 VSEL I, LVTTL or 1.8V Selects whether single-ended data and control pins are 3.3V LVTTL or 1.8V LVCMOS. LVCMOS Internal 0 = 1.8V LVCMOS. Tie VSEL to ground and power IOVDD at 1.8 V. pull down 1 = 3.3V LVTTL. Tie VSEL to IOVDD supply and power IOVDD at 3.3 V. 94 OPMODE I, LVTTL or 1.8V Selects SerDes mode. LVCMOS Internal   pull down 0 = Base station mode 1 = Reserved for future use 95 RESETB I, LVTTL or 1.8V Hardware SerDes reset. Resets PLLs and MDIO registers. LVCMOS Internal   pull down 0 = Hardware SerDes reset 1 = Normal operation www.national.com 4 96 97 Pin Name SPMODE [0] SPMODE [1] I/O, Type SCAN12100 Pin # Description I, LVTTL or 1.8V Speed mode configuration. (OPMODE must be low) LVCMOS Internal Pulling both pins low enables MDIO control. pull down SPMODE [1] SPMODE [0] 0 0 Rate selected via MDIO 0 1 614.4 Mbps rate mode 1 0 1228.8 Mbps rate mode 1 1 Reserved 98 TENBMODE I, LVTTL or 1.8V Enable 10-bit mode LVCMOS, Internal The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 pull down 0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder. 1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder. 99 100 LOOP [0] LOOP [1] I, LVTTL or 1.8V Loop back configuration. LVCMOS, Internal Pulling both pins low enables MDIO control. pull down Note: During Special line (remote) loop back mode, the output de-emphasis control is disabled. LOOP [1] LOOP [0] 0 0 Normal mode—no loop back 0 1 Line (remote) loop back mode 1 0 Local loop back mode 1 1 Special line (remote) loop back mode MDC/MDIO 30 31 37 36 35 34 33 MDC MDIO ADD0 ADD1 ADD2 ADD3 ADD4 3.3V LVTTL MDC/MDIO configuration bus. Internal pull up on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL ADDR pins compatible, not 1.2V signal compatible. IEEE 1149.1 (JTAG) 45 41 44 43 46 TDI TDO TMS TCK TRSTB 3.3V LVTTL JTAG test bus for IEEE 1149.1 and 1149.6 support. Internal pull up on TDI, TMS, and TRSTB RESERVED PINS 83 84 RES1 RES2 I Reserved. Tie with 5 KΩ resistor to ground. POWER 9, 15, 20, AVDD18 32, 38, 47, 85 I, Power 1.8V analog supply. 8, 14, 21, AVDD33 42 I, Power 3.3V analog supply. 1, 2, 28, 29 PVDD33 I, Power 3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak). 50, 51, 76, IOVDD 87 I, Power 1.8V or 3.3V parallel I/O bus and control pin supply. See VSEL pin description for additional information. I, Ground Device ground. GROUND 3, 4, 5, 10, GND 13, 16, 19, 24, 25, 26, 27, 39, 40, 48, 49, 63, 75, 86 5 www.national.com SCAN12100 Pin # Pin Name I/O, Type Description I, Ground Device ground. Pad must be soldered and contected to GND plane with a minimum of 8 thermal vias to achieve specified thermal performance. GROUND DAP 101 GND Note: I= input resistor www.national.com O = output Internal pull down = input pin is pulled low by an internal resistor 6 Internal pull up = input pin is pulled high by an internal Derating above 25°C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (AVDD18) Supply Voltage (PVDD, IOVDD) Supply Voltage (AVDD33) LVCMOS Input Voltage −0.3V to +2.0V −0.3V to +3.6V −0.3V to +3.6V −0.3V to (IOVDD + 0.5V) LVCMOS Output Voltage −0.3V to (IOVDD + 0.5V) MDC/MDIO/ADD[0:4],VSEL Input Voltage −0.3V to (AVDD33 + 0.5V) MDIO Output Voltage −0.3V to (AVDD33 + 0.5V) CML Receiver Input Voltage −0.3V to (AVDD + 0.3V) CML Receiver Output Voltage −0.3V to (AVDD + 0.3V) Junction Temperature +125°C Storage Temperature −65°C to +150°C Lead Temperature Soldering, 10–20 sec 235 °C Lead-free +260°C flow is available Maximum Package Power Dissipation at 25°C 100-pin TQFP with Exposed Pad 4.16 W Note: This is the maximum TQFP-100 package power dissipation capability. For SCAN12100 power dissipation, see the information in the Electrical Characteristics section. Electrical Characteristics Symbol 41.6 mW/°C 24.0°C/W Thermal Resistance , θJA (0 airflow) ESD Rating CML RIN/DOUT Pins HBM, 1.5 kΩ, 100 pF >8 kV EIAJ, 0Ω, 200 pF CDM All Other Pins >250V >2 kV HBM, 1.5 kΩ, 100 pF >7 kV EIAJ, 0Ω, 200 pF CDM >250V >2 kV Recommended Operating Conditions Supply Voltage AVDD18 AVDD33, PVDD33 IOVDD (1.8V Mode) IOVDD (3.3V Mode) Temperature Junction temperature Supply Noise (Peak-to-Peak) Min Typ Max Unit 1.7 3.135 1.7 3.135 -40 1.8 3.3 1.8 3.3 25 1.9 3.465 1.9 3.465 85 125 V V V V °C °C