SN65HVD1040-HT
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SLLSEA6D – DECEMBER 2011 – REVISED AUGUST 2012
LOW-POWER CAN TRANSCEIVER WITH BUS WAKE-UP
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FEATURES
1
•
•
•
•
•
•
•
•
•
Improved Drop-in Replacement for the
TJA1040
±12 kV ESD Protection
Low-Current Standby Mode with Bus Wake-up:
5 μA Typical
Bus-Fault Protection of –27 V to 40 V
Rugged Split-Pin Bus Stability
Dominant Time-Out Function
Thermal Shutdown Removed
Power-Up/Down Glitch-Free Bus Inputs and
Outputs
– High Input Impedance with Low VCC
– Monotonic Outputs During Power Cycling
DeviceNet Vendor ID # 806
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
•
•
Down-Hole Drilling
High Temperature Environments
Vibration/Modal Analysis
Multi-Channel Data Acquisition
Acoustics/Dynamic Strain Gauges
Pressure Sensors
(1)
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/210°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours continuous
operating life at maximum rated temperature.
Custom temperature ranges available
DESCRIPTION
The SN65HVD1040 meets or exceeds the specifications of the ISO 11898 standard for use in applications
employing a Controller Area Network (CAN). As CAN transceivers, these devices provide differential transmit and
receive capability for a CAN controller at signaling rates of up to 1 megabit per second (Mbps). (2)
Designed for operation in especially harsh environments, the device features ±12 kV ESD protection on the bus
and split pins, cross-wire, overvoltage and loss of ground protection from –27 to 40 V, a –12 V to 12 V commonmode range, and will withstand voltage transients from –200 V to 200 V according to ISO 7637.
The STB input (pin 8) selects between two different modes of operation; high-speed or low-power mode. The
high-speed mode of operation is selected by connecting STB to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor
standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater
than 5 μs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may
then reactivate the device when it needs to transmit to the bus.
A dominant-time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication
during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no
rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then
reset by the next rising edge on TXD.
(2)
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
SN65HVD1040-HT
SLLSEA6D – DECEMBER 2011 – REVISED AUGUST 2012
www.ti.com
The SPLIT output (pin 5) is available on the SN65HVD1040 as a VCC/2 common-mode bus voltage bias for a
split-termination network.
The SN65HVD1040 is characterized for operation from –55°C to 210°C.
VCC
VCC
TXD
DOMINANT
TIME -OUT
30 mA
1
OVER
TEMPERATURE
SENSOR
INPUT
LOGIC
3
VCC / 2
5
SPLIT
DRIVER
VCC
7
STB
RXD
8
4
10 mA
6
SLEEP
OUTPUT
LOGIC
MODE
CANH
CANL
MUX
WAKE UP
FILTER
BUS MONITOR
2
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
TJ
–55°C to 210°C
PACKAGE
ORDERABLE PART NUMBER
KGD (bare die)
SN65HVD1040SKGD3
NA
HKQ
SN65HVD1040SHKQ
HVD1040SHKQ
D
SN65HVD1040HD
H1040
–55°C to 175°C
(1)
TOP-SIDE MARKING
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
BARE DIE INFORMATION
DIE
THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
BOND PAD THICKNESS
15 mils.
Silicon with backgrind
Floating
CuNiPd
15 microns
Table 2. BOND PAD COORDINATES (µm)
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
PAD SIZE X
PAD SIZE Y
TXD
1
53.64
162
137.7
246.06
84.06
84.06
GND
2
804.06
50.85
888.12
134.91
84.06
84.06
GND
3
920.07
50.85
1004.13
134.91
84.06
84.06
Vcc
4
1320.21
54.18
1404.27
138.24
84.06
84.06
Vcc
5
1431.09
54.18
1515.15
138.24
84.06
84.06
RXD
6
2148.75
164.34
2232.81
248.4
84.06
84.06
SPLIT
7
2147.4
707.49
2231.46
791.55
84.06
84.06
CANL
8
771.93
907.38
855.99
991.44
84.06
84.06
CANH
9
527.31
907.38
611.37
991.44
84.06
84.06
STB
10
62.28
806.13
146.34
890.19
84.06
84.06
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ABSOLUTE MAXIMUM RATINGS (1)
VALUE
VCC
Supply voltage (2)
VI(bus)
Voltage range at any bus terminal (CANH, CANL, SPLIT)
IO(OUT)
Receiver output current
–0.3 V to 7 V
–27 V to 40 V
-20 mA to 20 mA
Voltage input, transient pulse (3), (CANH, CANL, SPLIT)
IEC Contact Discharge
Bus terminals vs GND
±6 kV
Human body model
JEDEC Standard 22,
Test Method A114-C.01
Bus terminals vs GND
±12 kV
All pins
±4 kV
Field-Induced-Charged
Device Model
JEDEC Standard 22,
Test Method C101
All pins
±1 kV
Machine model
ANSI/ESDS5.2-1996
ESD
IEC
Voltage input range (TXD, STB)
TJ
Junction temperature
(2)
(3)
±200 V
Bus terminals vs GND
VI
(1)
–200 V to 200 V
(IEC 61000-4-2)
±6 kV
–0.5 V to 6 V
–55°C to 210°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6 & 7.
THERMAL CHARACTERISTICS FOR HKQ PACKAGE
over operating free-air temperature range (unless otherwise noted)
PARAMETER
θJC
Junction-to-case thermal resistance
MIN
TYP
to ceramic side of case
MAX
5.7
to top of case lid (metal side of case)
13.7
UNIT
°C/W
THERMAL INFORMATION FOR D PACKAGE
SN65HVD1040
THERMAL METRIC (1)
D
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance (2)
91.9
θJCtop
Junction-to-case (top) thermal resistance (3)
39.9
θJB
Junction-to-board thermal resistance (4)
40.6
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
39.6
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
3.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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RECOMMENDED OPERATING CONDITIONS
TJ = -55°C to 125°C
MIN
VCC
Supply voltage
VI or
VIC
Voltage at any bus terminal (separately
or common mode)
VIH
High-level input
voltage
TJ = -55°C to 175°C
MAX
MIN
4.75
5.25
–12 (1)
NOM
TJ = -55°C to 210°C
NOM
MAX
UNIT
MAX
MIN
4.75
5.25
4.75
5.25
V
12
–12 (1)
12
–12 (1)
12
V
2
5.25
2
5.25
2
5.25
V
0
0.8
0
0.8
0
0.8
V
–6
6
–6
6
–6
6
V
TXD, STB
VIL
Low-level input
voltage
VID
Differential input voltage
IOH
High-level output
current
Driver
IOL
Low-level output
current
Driver
tSS
Maximum pulse width to remain in
standby
TJ
Junction temperature
(1)
NOM
Receiver
–70
–70
–70
–2
–2
–2
70
70
70
2
2
2
0.7
0.7
0.7
μs
210
°C
Receiver
–55
mA
125
–55
175
–55
mA
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
SUPPLY CURRRENT
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply
current,
VCC
TJ = -55°C to 125°C
TYP
MAX
VI = 0 V, 60 Ω Load,
STB at 0 V
50
Recessi VI = VCC, STB at 0 V
ve
Standby STB at VCC, VI =
VCC
Domina
nt
ICC
TEST CONDITIONS
MIN
TJ = -55°C to 175°C
MIN
TJ = -55°C to 210°C
TYP
MAX
70
50
6
10
5
12
MIN
TYP
MAX
70
50
70
6
10
6
10
5
20
5
50
UNIT
mA
μA
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
tloop Total loop delay,
driver input to
1
receiver output,
Recessive to
Dominant
tloop Total loop delay,
driver input to
2
receiver output,
Dominant to
Recessive
TEST CONDITIONS
TJ = -55°C to 125°C
MIN
90
TYP
TJ = -55°C to 175°C
MAX
MIN
230
90
TYP
TJ = -55°C to 210°C
MAX
MIN
325
90
TYP
MAX
UNIT
450
STB at 0 V,
See Figure 10
ns
90
230
90
325
90
450
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
VO(D)
Bus
output
voltage
(Domina
nt)
CAN
H
VI = 0 V, STB at 0 V, RL =
60 Ω, See Figure 2 and
CANL Figure 3
VO(R)
Bus output
voltage
(Recessive)
VO
Bus output
RL = 60 Ω, STB at VCC,
voltage (Standby) See Figure 2 and Figure 3
VOD(D)
VI = 0 V, RL = 60 Ω, STB
at 0 V, See Figure 2 and
Differential output Figure 3, and Figure 4
voltage
VI = 0 V, RL = 45 Ω, STB
(Dominant)
at 0 V, See Figure 2 and
Figure 3
VSYM
VOD(R)
VI = 3 V, RL = 60 Ω, STB
Differential output at 0 V, See Figure 2 and
Figure 3
voltage
(Recessive)
VI = 3 V, STB at 0 V, No
Load
Common-mode
VOC(D) output voltage
(Dominant)
)
Peak-to-peak
common-mode
output voltage
STB at 0 V, See Figure 3
and Figure 14
TJ = -55°C to 175°C
TJ = -55°C to 210°C
MIN
TYP (1)
MAX
MIN
TYP (1)
MAX
MIN
TYP (1)
MAX
2.9
3.4
4.5
2.9
3.4
4.6
2.9
3.4
4.6
1.75
0.8
1.75
0.8
3
2
3
2
–0.1
0.1
–0.125
0.125
1.5
3
1.5
1.4
3
1.4
UNIT
V
0.8
VI = 3 V, STB at 0 V, See
Figure 2 and Figure 3
Output symmetry
(Dominant or
Recessive)
[ VO(CANH) +
VO(CANL) ]
VOC(pp
TJ = -55°C to 125°C
TEST CONDITIONS
2
2.5
2.5
1.75
2.5
3
V
–0.15
0.15
V
3
1.5
3
3
1.4
3
1.1×VC
0.9×VC
C
C
V
0.9×VCC
VCC
1.1×VC
C
0.9×VCC
VCC
VCC
1.2×VCC
–0.012
0.012
–0.014
0.017
–0.015
0.02
–0.5
0.05
–0.5
0.225
–0.75
0.8
3
2
3
2
V
V
2
2.3
2.3
2.3
3.1
STB at 0 V, See Figure 9
V
0.3
0.3
0.3
IIH
High-level input
current, TXD
input
VI at VCC
–2
2
–3
3
–3
3
μA
IIL
Low-level input
current, TXD
input
VI at 0 V
–50
–10
–50
–10
–50
–10
μA
IO(off)
Power-off TXD
Leakage current
VCC at 0 V, TXD at 5 V
600
μA
1
VCANH = –12 V, CANL
Open, See Figure 13
IOS(ss)
Short-circuit
steady-state
output current
–120
VCANH = 12 V, CANL Open,
See Figure 13
0.36
(1)
6
Output
capacitance
–120
1
–72
0.36
–130
1
–72
0.36
1.1
mA
VCANL = –12 V, CANH
Open, See Figure 13
–1
VCANL = 12 V, CANH
Open, See Figure 13
CO
–72
180
–0.5
71
–1
120
–0.5
71
–1.1
120
–0.5
71
130
See Input capacitance to
ground in RECEIVER
ELECTRICAL
CHARACTERISTICS .
All typical values are at 25°C with a 5-V supply.
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TJ = -55°C to 125°C
TJ = -55°C to 175°C
MIN
TYP
MAX
MIN
TYP
MAX
TJ = -55°C to 210°C
MIN TYP
MAX
tPLH
Propagation delay time, lowto-high-level output
25
65
120
25
65
175
25
65
250
tPHL
Propagation delay time,
high-to-low-level output
25
45
120
25
45
175
25
45
250
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Differential output signal rise
time
25
25
25
tf
Differential output signal fall
time
50
50
50
ten
Enable time from silent
mode to dominant
See Figure 8
tdom
Dominant time-out
See Figure 11
STB at 0 V, See Figure 5
25
25
11
300
450
700
14.5
300
450
700
300
450
25
ns
18
μs
700
μs
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UNIT
7
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TJ = -55°C to 125°C
TEST CONDITIONS
MIN
VIT+
Positivegoing input
threshold
voltage
VIT–
Negativegoing input
threshold
voltage
Vhys
Hysteresis
voltage
(VIT+ – VIT–)
VIT
Input
threshold
voltage
VOH
High-level output voltage
IO = –2 mA, See Figure 7
VOL
Low-level output voltage
IO = 2 mA, See Figure 7
II(off)
Power-off bus input current
CANH or CANL = 5 V, VCC at 0
V, TXD at 0 V
IO(off)
Power-off RXD leakage
current
VCC at 0 V, RXD at 5 V
CI
Input capacitance to ground,
(CANH or CANL)
TXD at 3 V, VI = 0.4 sin (4E6πt)
+ 2.5 V
CID
Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt)
RID
Differential input resistance
TXD at 3 V, STD at 0 V
30
RIN
Input resistance, (CANH or
CANL)
TXD at 3 V, STD at 0 V
15
RI(m)
Input resistance matching
[1 – (RIN (CANH) / RIN (CANL))] x
100%
VCANH = VCANL
–3%
TJ = -55°C to 175°C
TYP
MAX
800
900
MIN
TJ = -55°C to 210°C
TYP
MAX
MIN TYP
MAX
800
900
800
900
UNIT
STB at 0 V, See Table 3
High-speed
mode
500
650
500
650
500
650
mV
Standby
mode
STB at VCC
100
STB at VCC
500
125
70
1150
4
4.6
125
500
1300
4
0.2
70
400
4.6
0.4
4
0.2
125
0.5
1350
4.6
V
0.2
0.55
V
5
15
30
μA
20
30
30
μA
20
20
10
20
10
80
30
30
40
15
0%
3%
–5%
pF
10
pF
80
30
80
30
40
15
30
40
0%
5%
–12%
0%
12%
kΩ
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TJ = -55°C to 125°C
TJ = -55°C to 175°C
MIN
TYP
MAX
MIN
TYP
MAX
TJ = -55°C to 210°C
MIN
TYP
MAX
60
100
130
60
100
200
60
100
200
45
70
130
45
70
200
45
70
200
ns
5.25
μs
tpLH
Propagation delay time, lowto-high-level output
tpHL
Propagation delay time, highto-low-level output
tr
Output signal rise time
8
8
8
tf
Output signal fall time
8
8
8
tBUS
Dominant time required on
bus for wake-up from
standby (1)
(1)
STB at 0 V, TXD at 3 V, See
Figure 7
STB at VCC Figure 12
0.7
5
1.0
5.1
1.45
UNIT
The device under test shall not signal a wake-up condition with dominant pulses shorter than tBUS (min) and shall signal a wake-up
condition with dominant pulses longer than tBUS (max). Dominant pulses with a length between tBUS (min) and tBUS (max) may lead to a
wake-up.
SPLIT-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
PARAMETER
VO
IO(st
b)
8
Output voltage
Standby mode leakage
current
TEST
CONDITIONS
–500 μA < IO <
500 μA
STB at 2 V,
–12 V ≤ VO ≤ 12
V
TJ = -55°C to 125°C
TJ = -55°C to 175°C
TJ = -55°C to 210°C
MIN
TYP
MAX
MIN
TYP
MAX
0.3×VCC
0.5×VCC
0.7×VCC
0.28×VCC
0.5×VCC
0.7×VCC
5
–7
–5
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7
MIN
TYP
0.28×VC
0.5×VC
C
C
–15
MAX
UNIT
0.7×VCC
V
15
μA
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STB-PIN CHARACTERISTICS
over recommended operating conditiions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
TJ = -55°C to 125°C
TJ = -55°C to 175°C
MIN
MAX
MIN
TYP
TYP
TJ = -55°C to 210°C
MAX
MIN
TYP
MAX
UNIT
IIH
High level input current
STB at 2 V
–10
0
–10
0
–10
0
μA
IIL
Low level input current
STB at 0 V
–10
0
–10
0
–10
0
μA
Estimated Life (Hrs)
100000
10000
1000
130
140
150
160
170
180
190
200
210
220
Continuous TJ (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
C.
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wear out for the specific device process and design characteristics.
Figure 1. SN65HVD1040-HT Operating Life Derating Chart
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PARAMETER MEASUREMENT INFORMATION
Dominant
IO(CANH)
II
TXD
VOD
3.5 V
Recessive
RL VO(CANH)
2.5 V
VO(CANH) + VO(CANL)
2
VI
STB
VO(CANH)
1.5 V
VO(CANL)
VOC
IO(CANL)
VO(CANL)
Figure 2. Driver Voltage, Current, and Test
Definition
CANH
0V
TXD
VOD
Figure 3. Bus Logic State Voltage Definitions
330 +1%
60 +1%
+
_
STB
CANL
−2 V 3 VTEST 3 7 V
330 +1%
Figure 4. Driver VOD Test Circuit
CANH
VCC
TXD
RL = 60 W
VO
+1‘%
VI
(see Note A)
VCC
2
VI
STB
VCC
2
0V
CL = 100 pF +20%
(see Note B)
tPLH
tPHL
90%
0.9 V
VO
CANH
0.5 V
10%
tr
V O(D)
VO(R)
tf
Figure 5. Driver Test Circuit and Voltage Waveforms
CANH
RXD
V I (CANH)
VIC =
IO
V ID
VI(CANH) + VI(CANL)
2
V I (CANL)
CANL
VO
Figure 6. Receiver Voltage and Current Definitions
10
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PARAMETER MEASUREMENT INFORMATION (continued)
3.5 V
CANH
1.5 V
CANL
1.5 V
IO
VI
(see NoteA)
2.4 V
2V
VI
RXD
tPLH
CL = 15 pF ±20%
(see Note B)
VO
STB
tPLH
V OH
90%
0.7 VCC
0.3 VCC
VO
10%
tf
tr
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6 ns, tf ≤ 6ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 7. Receiver Test Circuit and Voltage Waveforms
Table 3. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
R
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
6V
H
6V
12 V
6V
H
Open
Open
X
H
VOL
VOH
DUT
CANH
0V
TXD
C
L
60W ±1%
VCC
VI
50%
0V
VI
STB
CANL
NOTE: CL = 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
RXD
+
VO
−
VOH
50%
VO
VOL
ten
15 pF ±20%
Figure 8. ten Test Circuit and Voltage Waveforms
CANH
27 W +1%
TXD
V
I
CANL
STB
A.
27 W +1%
VOC(PP)
47 nF
+20%
VOC =
VO (CANH) + VO (CANL)
2
VOC
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. Peak-to-Peak Common Mode Output Voltage Test and Waveform
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DUT
CANH
TXD
C
L
STB
A.
TXD
Input
CANL
50%
0V
tloop2
NOTE: CL = 100 pF
Includes Instrumentation
and Fixture Capacitance
Within ±20%
RXD
+
VO
−
VCC
60 W 1%
tloop1
VOH
50%
RXD Output
50%
VOL
15 pF 20%
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 10. tloop Test Circuit and Voltage Waveforms
CANH
VCC
VI
TXD
0V
VO
RL = 60 W +1%
CL
(see Note B)
VI
(see Note A)
VOD(D)
VO
CANL
STB
900 mV
500 mV
0V
tdom
A.
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
B.
CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 11. Dominant Time-Out Test Circuit and Waveform
CANH
VCC
3.5 V
STB
RXD
2.65 V
VI
IO
VI
(see Note A)
1.5 V
CANL
1.5 V
(see Note B)
CL
VO
tBUS
0.7 s
VOH
VO
400 mV
V OL
A.
For VI bit width ≤ 0.7 μs, VO = VOH. For VII bit width ≥ 5 μs, VO = VOL. VI input pulses are supplied from a generator
with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B.
CL = 15 pF includes instrumentation and fixture capacitance within ±20%.
Figure 12. tBUS Test Circuit and Waveform
12
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SLLSEA6D – DECEMBER 2011 – REVISED AUGUST 2012
IOS
IOS(SS)
IOS(P)
CANH
TXD
200 ms
0 V or VCC
0V
STB
CANL
VIN
12 V
−12 V or 12 V
Vin
0V
10 ms
or
0V
Vin
−12 V
Figure 13. Driver Short-Circuit Current Test and Waveform
CANH
VI
60 W ± 1%
TXD
60 W ± 1%
STB
CANL
V O (CANL)
4.7 nF
± 20%
VSYM =
+VO
VO(CANH)
(CANL)
VO (CANH)
Figure 14. Driver Output Symmetry Test Circuit
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DEVICE INFORMATION
Table 4. DRIVER FUNCTION TABLE (1)
INPUTS
(1)
OUTPUTS
TXD
STB
CANH
BUS STATE
CANL
L
L
H
L
DOMINANT
H
L
Z
Z
RECESSIVE
Open
X
Z
Z
RECESSIVE
X
H or Open
Z
Z
RECESSIVE
H = high level; L = low level; X = irrelevant; Z = high impedance
Table 5. RECEIVER FUNCTION TABLE (1)
DIFFERENTIAL INPUTS
VID = CANH - CANL
STB
OUTPUT
RXD
BUS STATE
VID ≥ 0.9 V
L
L
DOMINANT
DOMINANT
(1)
14
VID ≥ 1.15 V
H or Open
L
0.5 V < VID < 0.9 V
X
?
?
VID ≤ 0.5 V
X
H
RECESSIVE
Open
X
H
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z =
high impedance
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DEVICE INFORMATION
Table 6. Parametric Cross Reference With the TJA1040
TJA1040
(1)
PARAMETER
HVD10xx
TJA1040 DRIVER SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
Driver IIH
IIL
Low-level input current
Driver IIL
TJA1040 BUS SECTION
Vth(dif)
Differential input voltage
Receiver VIT and recommended VID
Vhys(dif)
Differential input hysteresis
Receiver Vhys
VO(dom)
Dominant output voltage
Driver VO(D)
VO(reces)
Recessive output voltage
Driver VO(R)
Vi(dif)(th)
Differential input voltage
Receiver VIT and recommended VID
VO(dif0(bus)
Differential bus voltage
Driver VOD(D) and VOD(R)
ILI
Power-off bus input current
Receiver II(off)
IO(SC)
Short-circuit output current
Driver IOS(SS)
Ri(cm)
CANH, CANL input resistance
Receiver RIN
Ri(def)
Differential input resistance
Receiver RID
Ri(cm) (m)
Input resistance matching
Receiver RI (m)
Ci(cm)
Input capacitance to ground
Receiver CI
Ci(dif)
Differential input capacitance
Receiver CID
IOH
High-level output current
Recommended IOH
IOL
Low-level output current
Recommended IOL
VO
Reference output voltage
TJA1040 RECEIVER SECTION
TJA1040 SPLIT PIN SECTION
VO
TJA1040 TIMING SECTION
td(TXD-BUSon)
Delay TXD to bus active
Driver tPLH
td(TXD-BUSoff)
Delay TXD to bus inactive
Driver tPHL
td(BUSon-RXD)
Delay bus active to RXD
Receiver tPHL
td(BUSoff-RXD)
Delay bus inactive to RXD
Receiver tPLH
tPD(TXD–RXD)
Prop delay TXD to RXD
Device tLOOP1 and tLOOP2
td(stb-norm)
Enable time from standby to dominant
Driver ten
TJA1040 STB PIN SECTION
VIH
High-level input voltage
Recommended VIH
VIL
Low-level input voltage
Recommended VIL
IIH
High-level input current
IIH
IIL
Low-level input current
IIL
(1)
From TJA1040 Product Specification, Philips Semiconductors, 2003 February 19.
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Equivalent Input and Output Schematic Diagrams
TXD Input
RXD Output
Vcc
Vcc
15 W
4. 3 k W
Output
Input
6V
6V
CANH Input
CANL Input
Vcc
Vcc
10 k W
10 k W
Input
20 k W
Input
10 kW
40 V
40 V
20 k W
10 k W
CANH and CANL Outputs
STB Input
Vcc
Vcc
4. 3 k W
Output
Input
40 V
6V
SPLIT Output
Vcc
2kW
Output
2k W
40 V
16
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SLLSEA6D – DECEMBER 2011 – REVISED AUGUST 2012
150
145
140
RECESSIVE-TO-DOMINANT LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
t LOOP2 − Dominant-to-Recessive Loop Time − ns
t LOOP1− Recessive-to-Dominant Loop Time − ns
TYPICAL CHARACTERISTICS
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 4.75 V
135
130
VCC = 5 V
125
VCC = 5.25 V
120
−40
0
25
70
TA − Free-Air Temperature − °C
160
S at 0 V,
RL = 60 W,
CL = 100 pF,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz,
50% Duty Cycle Pulse
VCC = 5.25 V
155
VCC = 5 V
150
145
VCC = 4.75 V
140
−40
0
25
70
125
TA − Free-Air Temperature − °C
Figure 15.
Figure 16.
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
90
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
RXD = 15 pF
80
I OL − Low-Level Output Current − mA
I CC − RMS Supply Current − mA
40
165
125
50
45
170
DOMINANT-TO-RECESSIVE LOOP TIME
vs
FREE-AIR TEMPERATURE (across VCC)
35
30
25
20
15
10
5
70
60
50
40
30
20
TA = 255C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
10
0
0
200
400
500
600
800
Signaling Rate − kbps
1000
−10
0
1
2
3
4
5
VOCANL − Low-Level Output Voltage − V
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = 25 C,
VCC = 5 V,
S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
-70
-60
-50
-40
-30
-20
-10
3
Dominant Driver Differential Output Voltage − V
-0
1
S at 0 V,
RL = 60 W,
Air Flow at 7 cf/m,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
0.5
0
25
70
TA − Free-Air Temperature − °C
Figure 19.
Figure 20.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
125
6
TA = 255C,
VCC = 5 V,
S at 0 V,
RL = 60 W,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
VIT+
VIT−
5
30
25
20
15
10
VCM = 12 V
4
VCM = 2.5 V
3
VCM = −12 V
2
TA = 255C,
VCC = 5 V,
S at 0 V,
RXD = 15 pF
1
0.60
0.65
5.25
0.70
5
0.75
3.5
4
4.5
VCC − Supply Voltage − V
0.80
3
0.85
2
0.85
1
−1
1
0.80
0
0.75
0
5
0.70
35
VCC = 4.75 V
1.5
0.65
40
2
−40
VO − Receiver Output Voltage − V
I O − Differential Driver Output Current − mA
45
VCC = 5.25 V
0
0
1
2
3
4
5
VOCANH − High-Level Output Voltage − V
50
VCC = 5 V
2.5
0.60
I OH − High-Level Output Current − mA
-80
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE (across VCC)
VID − Differential Input Voltage − V
Figure 21.
18
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
TYPICAL ELECTROMAGNETIC EMISSIONS
UP TO 50 MHZ (Peak Amplitude)
TYPICAL ELECTROMAGNETIC
IMMUNITY PERFORMANCE
80
dBm
DB mV
60
40
20
0
0.1
Figure 23. Frequency Spectrum of Common-Mode
Emissions
1
10
f − Frequency − MHz
100
1000
Figure 24. Direct Power Injection (DPI) Response vs
Frequency
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APPLICATION INFORMATION
CAN Basics
The basics of arbitration require that the receiver at the sending node designate the first bit as dominant or
recessive after the initial wave of the first bit of a message travels to the most remote node on a network and
back again. Typically, this “sample” is made at 75% of the bit width, and within this limitation, the maximum
allowable signal distortion in a CAN network is determined by network electrical parameters.
Factors to be considered in network design include the approximately 5 ns/m propagation delay of typical
twisted-pair bus cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in
a system also need to be accounted for with adjustments in signaling rate and stub and bus length. Table 7 lists
the maximum signaling rates achieved with the SN65HVD1040 with several bus lengths of category 5, shielded
twisted pair (CAT 5 STP) cable.
Table 7. Maximum Signaling Rates for Various Cable
Lengths
Bus Length (m)
Signaling Rate (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes to a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A large
number of nodes requires a transceiver with high input impedance such as the HVD1040.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120 Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the Standard’s –2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The HVD1040 enhances the Standard’s insurance of data
integrity with an extended –12 V to 12 V range of common-mode operation.
20
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PACKAGE OPTION ADDENDUM
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4-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVD1040HD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-55 to 175
H1040
SN65HVD1040SHKQ
ACTIVE
CFP
HKQ
8
25
RoHS & Green
AU
N / A for Pkg Type
-55 to 210
HVD1040S
HKQ
SN65HVD1040SKGD3
ACTIVE
XCEPT
KGD
0
210
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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