SN65HVD21MDREPG4

  www.ti.com SGLS321 − DECEMBER 2005     
 

FEATURES D Controlled Baseline D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Common-Mode Voltage Range (−20 V to 25 V) More Than Doubles TIA/EIA-485 Requirement Receiver Equalization Extends Cable Length, Signaling Rate (HVD23, HVD24) Reduced Unit-Load for up to 256 Nodes Bus I/O Protection to Over 16-kV HBM D D D Failsafe Receiver for Open-Circuit, Short-Circuit and Idle-Bus Conditions D Low Standby Supply Current 1.5-µA Max D More Than 100 mV Receiver Hysteresis † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. APPLICATIONS D Long Cable Solutions − − − Factory Automation Security Networks Building HVAC D Severe Electrical Environments − − − Electrical Power Inverters Industrial Drives Avionics DESCRIPTION The SN65HVD21M offers performance exceeding typical RS−485 devices. In addition to meeting all requirements of the TIA/EIA−485−A standard, the HVD2x family operates over an extended range of common-mode voltage, and has features such as high ESD protection, wide receiver hysteresis, and failsafe operation. This family of devices is ideally suited for long-cable networks, and other applications where the environment is too harsh for ordinary transceivers. The SN65HVD21M is designed for bidirectional data transmission on multipoint twisted-pair cables. Example applications are digital motor controllers, remote sensors and terminals, industrial process control, security stations, and environmental control systems. The SN65HVD21M combines a 3-state differential driver and a differential receiver, which operates from a single 5-V power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a differential bus port that offers minimum loading to the bus. This port features an extended common-mode voltage range making the device suitable for multipoint applications over long cable runs. The SN65HVD21M allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver output slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.    ! "#$ !  %#&'" ($) (#"! "  !%$""! %$ *$ $!  $+! !#$! !(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!) Copyright  2005, Texas Instruments Incorporated 
  www.ti.com SGLS321 − DECEMBER 2005 APPLICATION SPACE SN65HVDM21 Operates Over a Wider Common-Mode Voltage Range 100 Signaling Rate − Mbps −20 V +25 V SUPER−485 10 HVD21 RS−485 1 −7 V −20 V −15 V −10 V +12 V −5 V 0 5V 10 V 15 V 20 V 25 V 0.1 10 100 Cable Length − m 1000 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (continued) The receiver also includes a failsafe circuit that provides a high-level output within 250 µs after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active transmitters on the bus. This feature prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. The SN65HVD21M is characterized for operation over the temperature range of −55°C to 125°C. PRODUCT SELECTION GUIDE PART NUMBERS CABLE LENGTH AND SIGNALING RATE(1) SN65HVD21MDREP Up to 150 m at 5 Mbps (with slew rate limit) (1) Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter. AVAILABLE OPTIONS PLASTIC SMALL-OUTLINE(1) D PACKAGE (JEDEC MS-012) SN65HVD21MDREP (1) Add R suffix for taped and reeled carriers. 2 NODES Up to 256 MARKING D: V21MEP 
  www.ti.com SGLS321 − DECEMBER 2005 DRIVER FUNCTION TABLE INPUT ENABLE OUTPUTS D DE A B H H H L L H L H X L Z Z X OPEN Z Z OPEN H H L H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate RECEIVER FUNCTION TABLE DIFFERENTIAL INPUT ENABLE OUTPUT VID = (VA – VB) 0.2 V ≤ VID RE R L H −0.2 V < VID < 0.2 V L H (see Note A) VID ≤ −0.2 V X L L H Z X OPEN Z Open circuit L H Short Circuit L H Idle (terminated) bus L H H = high level, L= low level, Z = high impedance (off) NOTE A: If the differential input VID remains within the transition range for more than 250 µs, the integrated failsafe circuitry detects a bus fault, and set the receiver output to a high state. See Figure 15. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Supply voltage(2), VCC −0.5 V to 7 V Voltage at any bus I/O terminal −27 V to 27 V Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 16) Voltage input at any D, DE or RE terminal Receiver output current, IO −10 mA to 10 mA Human Body Model(3) Electrostatic discharge Charged-Device Model(4) Machine Model(5) Continuous total power dissipation Junction temperature, TJ −60 V to 60 V −0.5 V to VCC+ 0.5 V A, B, GND 16 kV All pins 5 kV All pins 1.5 kV All pins 200 V See Power Dissipation Rating Table 150°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. (5) Tested in accordance with JEDEC Standard 22, Test Method A115-A. 3 
  www.ti.com SGLS321 − DECEMBER 2005 POWER DISSIPATION RATINGS TA ≤ 25°C POWER RATING CIRCUIT BOARD MODEL Low-K(1) DERATING FACTOR(3) ABOVE TA = 25°C 4.62 mW/°C TA = 70°C POWER RATING TA = 85°C POWER RATING 369 mW 300 mW 913 mW 7.3 mW/°C 584 mW (1) In accordance with the Low-K thermal metric definitions of EIA/JESD51−3. (2) In accordance with the High-K thermal metric definitions of EIA/JESD51−7. (3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 474 mW PACKAGE D 577 mW High-K(2) THERMAL CHARACTERISTICS PARAMETER θJB θJC TEST CONDITIONS 86.2 Junction-to-case thermal resistance 47.1 Typical PD Device power dissipation Worst case TSD VALUE Junction-to-board thermal resistance VCC = 5 V, TJ = 25°C, RL = 54 Ω, CL = 50 pF (driver), CL = 15 pF (receiver), 50% Duty cycle square-wave signal, Driver and receiver enabled VCC = 5.5 V, TJ = 125°C,RL = 54 Ω, CL = 50 pF, CL = 15 pF (receiver), 50% Duty cycle square-wave signal, Driver and receiver enabled 5 Mbps UNITS °C/W 260 mW 5 Mbps 342 Thermal shut-down junction temperature °C 170 RECOMMENDED OPERATING CONDITIONS Supply voltage, VCC Voltage at any bus I/O terminal High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID A, B D, DE, RE A with respect to B Driver Output current Receiver Operating free-air temperature, TA(1) MIN NOM 4.5 5 5.5 V −20 25 V 2 VCC 0.8 V V 0 −25 25 −110 110 −8 8 −55 125 °C 130 °C Junction temperature, TJ −55 (1) Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded. 4 MAX UNIT mA 
  www.ti.com SGLS321 − DECEMBER 2005 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted)(1) PARAMETER VIK VO VOD(SS) Input clamp voltage Open-circuit output voltage Steady-state differential output voltage magnitude TEST CONDITIONS II = −18 mA A or B, No load −1.5 No load (open circuit) 3.3 4.2 RL = 54 Ω, See Figure 1 With common-mode loading, See Figure 2 1.8 2.5 Change in steady-state differential output voltage between logic states See Figure 1 and Figure 3 VOC(SS) Steady-state common-mode output voltage See Figure 1 ∆VOC(SS) Change in steady-state common-mode output voltage, VOC(H) – VOC(L) See Figure 1 and Figure 4 VOC(PP) Peak-to-peak common-mode output voltage, VOC(MAX) – VOC(MIN) RL = 54 Ω, CL = 50 pF, See Figure 1 and Figure 4 VOD(RING) II Differential output voltage over and under shoot RL = 54 Ω, CL = 50 pF, See Figure 5 D, DE IO(OFF) IOZ Output current with power off High impedance state output current IOS Short-circuit output current COD Differential output capacitance (1) All typical values are at VCC = 5 V and 25°C. V VCC VCC 2.5 −0.1 0.1 V 2.9 V 0.1 V 0.35 V 10% −100 100 −100 See Figure 9 V V −0.1 VCC < = 2.5 V DE at 0 V UNIT 1.8 2.1 VO = −7 V to 12 V, MAX 0.75 0 ∆|VOD(SS)| Input current MIN TYP(1) 125 −270 µA µA 250 mA MAX UNIT See receiver CI DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPHL Differential output propagation delay, high-to-low tr tf Differential output rise time tPZH tPHZ Propagation delay time, high impedance-to-high level output tPZL tPLZ Propagation delay time, high impedance-to-low level output Differential output fall time Propagation delay time, high level-output-to-high impedance Propagation delay time, low level output-to-high impedance td(standby) Time from an active differential output to standby td(wake) Wake-up time from standby to an active differential output tsk(p) Pulse skew | tPLH – tPHL | (1) All typical values are at VCC = 5 V and 25°C. TEST CONDITIONS MIN TYP(1) RL = 54 Ω, CL = 50 pF, See Figure 3 15 32 60 ns RL = 54 Ω, CL = 50 pF, See Figure 3 15 40 60 ns RE at 0 V, See Figure 6 140 ns RE at 0 V, See Figure 7 140 ns RE at VCC, See Figure 8 4 µs 10 µs 10 ns 5 
  www.ti.com SGLS321 − DECEMBER 2005 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions PARAMETER VIT(+) VIT(−) Positive-going differential input voltage threshold VHYS Hysteresis voltage (VIT+ − VIT−) TEST CONDITIONS Negative-going differential input voltage threshold See Figure 10 VO = 2.4 V, IO = −8 mA VO = 0.4 V, IO = 8 mA VIT(F+) Positive-going differential input failsafe voltage threshold See Figure 15 VCM = −7 V to 12 V VCM = −20 V to 25 V VIT(F−) Negative-going differential input failsafe voltage threshold See Figure 15 VCM = −7 V to 12 V VCM = −20 V to 25 V VIK VOH Input clamp voltage VOL II(BUS) Low-level output voltage II RI II = −18 mA VID = 200 mV, IOH = −8 mA, See Figure 11 High-level output voltage MIN TYP(1) MAX 60 200 −200 −60 100 130 40 120 200 120 250 −200 −120 −40 −250 −120 −100 Input current RE −100 Input resistance mV V 0.4 V 125 µA 125 96 µA kΩ VID = 0.5 + 0.4 sine (2π x 1.5 x 106t) CID Differential input capacitance (1) All typical values are at 25°C. mV V 4 Bus input current (power on or power off) mV mV −1.5 VID = −200 mV, IOL = 8 mA, See Figure 11 VI = −7 to 12 V, Other input = 0 V UNIT 20 pF RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions PARAMETER TEST CONDITIONS tPHL tr Propagation delay time, high-to-low level output tf tPZH Receiver output fall time tPHZ tPZL Receiver output disable time from high level tPLZ tr(standby) Receiver output disable time from low level Receiver output rise time Receiver output enable time to high level TYP MAX See Figure 11 MIN 25 70 ns See Figure 11 2 7 ns 90 145 16 45 90 145 16 45 See Figure 12 Receiver output enable time to low level See Figure 13 Time from an active receiver output to standby tr(wake) Wake-up time from standby to an active receiver output tsk(p) tp(set) Pulse skew | tPLH – tPHL | Delay time, bus fail to failsafe set tp(reset) Delay time, bus recovery to failsafe reset UNIT ns ns 4 See Figure 14, DE at 0 V 11 250 See Figure 15, pulse rate = 1 kHz µs 7 ns 385 µs 70 ns SUPPLY CURRENT over recommended operating conditions (unless otherwise noted) PARAMETER ICC Supply current TYP MAX Driver enabled (DE at VCC), Receiver enabled (RE at 0 V) No load, VI = 0 V or VCC TEST CONDITIONS 8 15 mA Driver enabled (DE at VCC), Receiver disabled (RE at VCC) No load, VI = 0 V or VCC 7 14 mA Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V) No load 5 9 mA 1.5 µA Driver disabled (DE at 0 V), Receiver disabled (RE at VCC) D open 6 MIN UNIT 
  www.ti.com SGLS321 − DECEMBER 2005 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS RE Inputs D Inputs VCC 100 kΩ 1 kΩ Input 9V A Input VCC R1 R3 Input 29 V R2 29 V A and B Outputs VCC Output 29 V HVD21 R1/R2 36 kΩ R3 180 kΩ 7 
  www.ti.com SGLS321 − DECEMBER 2005 PARAMETER MEASUREMENT INFORMATION NOTES: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 Ω (unless otherwise specified) IO II 27 Ω VOD 0 V or 3 V 50 pF 27 Ω IO VOC Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading 375 Ω IO VOD 0 V or 3 V 60 Ω 375 Ω IO VTEST = −20 V to 25 V VTEST Figure 2. Driver Test Circuit, VOD With Common-Mode Loading 3V INPUT RL = 54 Ω Signal Generator VOD 1.5 V 90% 0V tPHL VOD(H) 10% VOD(L) tPLH CL = 50 pF 50 Ω 1.5 V 0V OUTPUT tr tf Figure 3. Driver Switching Test Circuit and Waveforms 27 Ω A VA D Signal Generator 50 Ω B 27 Ω ≈ 3.25 V VB 50 pF ≈ 1.75 V VOC(PP) VOC VOC Figure 4. Driver VOC Test Circuit and Waveforms 8 ∆VOC(SS) 
  www.ti.com SGLS321 − DECEMBER 2005 VOD(SS) VOD(RING) VOD(PP) 0 V Differential VOD(RING) VOD(SS) NOTE: VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values. Figure 5. VOD(RING) Waveform and Definitions A S1 D 0 V or 3 V 3 V if Testing A Output 0 V if Testing B Output DE Signal Generator 3V Output B 1.5 V DE CL = 50 pF RL = 110 Ω 1.5 V 0.5 V tPZH 0V VOH Output 50 Ω 2.5 V tPHZ VOff 0 Figure 6. Driver Enable/Disable Test, High Output 5V S1 D 3V Output 0 V or 3 V 0 V if Testing A Output 3 V if Testing B Output DE Signal Generator RL = 110 Ω 1.5 V DE 1.5 V 0V CL = 50 pF tPZL Output 50 Ω tPLZ 5V 2.5 V VOL 0.5 V Figure 7. Driver Enable/Disable Test, Low Output A 0 V or 3 V D RL = 54 Ω B DE Signal Generator CL = 50 pF VOD 3V DE 1.5 V 0V td(Wake) td(Standby) 1.5 V VOD 0.2 V 50 Ω Figure 8. Driver Standby/Wake Test Circuit and Waveforms 9 
  www.ti.com SGLS321 − DECEMBER 2005 IOS VO Voltage Source Figure 9. Driver Short-Circuit Test IO VID VO Figure 10. Receiver DC Parameter Definitions Signal Generator 50 Ω Input B VID A B Signal Generator 50 Ω IO R CL = 15 pF 1.5 V 50% Input A 0V tPHL VOH tPLH VO Output 90% 1.5 V tr 10% V OL tf Figure 11. Receiver Switching Test Circuit and Waveforms VCC VCC D DE A 54 Ω B 3V R RE Signal Generator 1 kΩ 0V RE 1.5 V 0V CL = 15 pF tPZH tPHZ 50 Ω R 1.5 V VOH VOH −0.5 V GND Figure 12. Receiver Enable Test Circuit and Waveforms, Data Output High 10 
  www.ti.com SGLS321 − DECEMBER 2005 0V VCC D DE A 54 Ω B 3V 1 kΩ R RE 5V 1.5 V 0V CL = 15 pF RE tPZL Signal Generator tPLZ VCC 50 Ω R 1.5 V VOL +0.5 V VOL Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output Low VCC Switch Down for V(A) = 1.5 V, Switch Up for V(A) = −1.5 V A 1.5 V or −1.5 V R 3V B 1 kΩ RE CL = 15 pF 1.5 V 0V RE Signal Generator tr(Standby) tr(Wake) 50 Ω 5V R 1.5 V VOH −0.5 V VOL +0.5 V 0V VOH VOL Figure 14. Receiver Standby and Wake Test Circuit and Waveforms Bus Data Valid Region 200 mV Bus Data Transition Region −40 mV VID −200 mV −1.5 V Bus Data Valid Region tp(SET) tp(RESET) VOH R 1.5 V VOL Figure 15. Receiver Active Failsafe Definitions and Waveforms 100 Ω VTEST 0V Pulse Generator, 15 µs Duration, 1% Duty Cycle 15 µs 1.5 ms −VTEST Figure 16. Test Circuit and Waveforms, Transient Overvoltage Test 11 
  www.ti.com SGLS321 − DECEMBER 2005 PIN ASSIGNMENTS D or P PACKAGE (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND LOGIC DIAGRAM POSITIVE LOGIC R 1 RE DE 2 3 D 4 6 A 7 B TYPICAL CHARACTERISTICS BUS PIN CURRENT vs BUS PIN VOLTAGE 150 DE = 0 V Bus Pin Current − µ A 100 50 VCC = 0 V 0 VCC = 5 V −50 −100 −150 −30 −20 −10 0 10 Bus Pin Voltage − V Figure 17 12 20 30 
  www.ti.com SGLS321 − DECEMBER 2005 SUPPLY CURRENT vs SIGNALING RATE DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs DRIVER LOAD CURRENT 75 VOD − Driver Differential Output Voltage − V 70 ICC − Supply Current − mA 5 VCC = 5 V, DE = RE = VCC, LOAD = 54 Ω, 50 pF 65 HVD21 60 55 50 45 40 0.1 1 10 Signaling Rate − Mbps 4.5 VCC = 5.5 V 4 3.5 VCC = 5 V 3 2.5 2 VCC = 4.5 V 1.5 1 0.5 0 100 0 10 20 30 40 50 60 IL − Driver Load Current − mA Figure 18 PEAK-TO-PEAK JITTER vs CABLE LENGTH 6 70 VIT(−) 5 VIT(+) 60 VCM = 25 V VCM = 25 V 4 VCM = 0 V VCM = 0 V 3 VCM = −20 V VCM = −20 V 1 0 −1 −0.2 Peak-to-Peak Jitter − ns VO − Receiver Output Voltage − V 80 Figure 19 RECEIVER OUTPUT VOLTAGE vs DIFFERENTAL INPUT VOLATGE 2 70 VCC = 5 V, TA = 25°C, VIC = 2.5 V, Cable: Belden 3105A HVD21 = 10 Mbps 50 40 30 20 10 −0.1 0 0.1 VID − Differential Input Voltage − V Figure 20 0.2 0 200 220 240 260 280 300 Cable Length − m Figure 21 13 
  www.ti.com SGLS321 − DECEMBER 2005 APPLICATION INFORMATION THEORY OF OPERATION The SN65HVD21M integrates a differential receiver and differential driver with additional features for improved performance in electrically-noisy, long-cable, or other fault-intolerant applications. The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps reject spurious noise signals which would otherwise cause false changes in the receiver output state. Slew rate limiting on the driver outputs reduces the high-frequency content of signal edges. This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and the main bus line. Designers should consider the maximum signaling rate and cable length required for a specific application, and choose the transceiver best matching those requirements. When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D input. When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance state. When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential bus inputs on the A and B pins. If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This reduces power consumption to less than 5 µW. When either enable input is asserted, the circuitry again becomes active. In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to implement an active receiver failsafe feature. These components determine whether the differential bus signal is valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the differential input remains within the transition range for more than 250 µs, the timer expires and set the receiver output to the high state. If a valid bus input (high or low) is received at any time, the receiver output reflects the valid bus state, and the timer is reset. (V A−V B) : Not High + − Bus Input Invalid (V A−VB) : Not Low Timer 250 ms R 1 120 mV + − 120 mV Active Filters 2 RE STANDBY 3 DE 6 D 4 Slew Rate Control Figure 22. Function Block Diagram 14 7 A B 
  www.ti.com SGLS321 − DECEMBER 2005 ƪ ƫƪǒ ƫƪ ƫ k0 (DC loss) p1 (MHz) k1 p2 (MHz) k2 p3 (MHz) k3 Similar to 160m of Belden 3105A 0.95 0.25 0.3 3.5 0.5 15 1 Similar to 250m of Belden 3105A 0.9 0.25 0.4 3.5 0.7 12 1 Similar to 500m of Belden 3105A 0.8 0.25 0.6 2.2 1 8 1 Similar to 1000m of Belden 3105A 0.6 0.3 1 3 1 6 1 H(s) + k0 ǒ1–k 1Ǔ ) k1p1 ǒs ) p 1Ǔ 1–k Ǔ) 2 k p 2 2 ǒs ) p2Ǔ ǒ1–k3Ǔ ) Signal Generator k p 3 3 ǒs ) p3Ǔ H(s) Figure 23. Cable Attenuation Model for Jitter Measurements NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS The simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. If the maximum attenuation of frequencies of interest is 20 dB, increasing the receiver gain by a factor of ten compensates for the cable. However, this means that both signal and noise are amplified. Therefore, the receiver with higher gain is more sensitive to noise and it is important to minimize differential noise coupling to the equalized receiver. Differential noise is crated when conducted or radiated noise energy generates more voltage on one line of the differential pair than the other. For this to occur from conducted or electric far-field noise, the impedance to ground of the lines must differ. For noise frequency out to 50 MHz, the input traces can be treated as a lumped capacitance if the receiver is approximately 10 inches or less from the connector. Therefore, matching impedance of the lines is accomplished by matching the lumped capacitance of each. The primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material, distance from the signal return path, stray capacitance, and proximity to other conductors. It is difficult to match each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines balanced and less susceptible to differential noise coupling. Another source of differential noise is from near-field coupling. In this situation, an assumption of equal noise-source impedance cannot be made as in the far-field. Familiarly known as crosstalk, more energy from a nearby signal is coupled to one line of the differential pair. Minimization of this differential noise is accomplished by keeping the signal pair close together and physical separation from high-voltage, high-current, or high-frequency signals. In summary, follow these guidelines in board layout for keeping differential noise to a minimum. D D D D D Keep the differential input traces short. Match the length, physical dimensions, and routing of each line of the pair. Keep the lines close together. Match components connected to each line. Separate the inputs from high-voltage, high-frequency, or high-current signals. 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65HVD21MDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 V21MEP SN65HVD21MDREPG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 V21MEP V62/06615-01XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 V21MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of