SN65HVD20, SN65HVD21, SN65HVD22, SN65HVD23, SN65HVD24
SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
SN65HVD2x Extended Common-Mode RS-485 Transceivers
1 Features
3 Description
•
The transceivers in the SN65HVD2x family offer
performance far exceeding typical RS-485 devices.
In addition to meeting all requirements of the
TIA/EIA‑485-A standard. The SN65HVD2x family
operates over an extended range of common-mode
voltages and has features such as high ESD
protection, wide receiver hysteresis, and failsafe
operation. This family of devices is designed for longcable networks, and other applications where the
environment is too harsh for ordinary transceivers.
•
•
•
•
•
•
Common-mode voltage range (–20 V to 25 V)
more than doubles TIA/EIA-485 requirement
Receiver equalization extends cable length,
signaling rate (SN65HVD2[3,4])
Reduced unit-load for up to 256 nodes
Bus I/O protection to over 16-kV HBM
Failsafe receiver for open-circuit, short-circuit, and
idle-bus conditions
Low standby supply current 1 µA (maximum)
More than 100 mV receiver hysteresis
2 Applications
•
Long cable solutions
– Factory automation
– Security networks
– Building HVAC
Severe electrical environments
– Electrical power inverters
– Industrial drives
– Avionics
These devices combine a 3-state differential driver
and a differential receiver that operate from a single
5-V power supply. The driver differential outputs and
the receiver differential inputs are connected internally
to form a differential bus port that offers minimum
loading to the bus. This port features an extended
common-mode voltage range, making the device
suitable for multipoint applications over long cable
runs.
Package Information
PACKAGE(1)
PART NUMBER
SN65HVD2x
(1)
100
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
PDIP (8)
9.81 mm × 6.35 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
-20 V
+25 V
HVD23
SUPER485
HVD20
Signaling Rate - Mbps
•
These devices are designed for bidirectional data
transmission on multipoint twisted-pair cables.
Example applications are digital motor controllers,
remote sensors and terminals, industrial process
control, security stations, and environmental control
systems.
10
HVD24
HVD21
RS485
1
-7 V
+12 V
HVD22
-20 V -15 V
0.1
10
100
Cable Length - m
1000
-10 V
-5 V
0
5V
10 V
15 V
20 V
25 V
SN65HVD2x Devices Operate Over a Wider
Common-Mode Voltage Range
SN65HVD2x Application Space
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD20, SN65HVD21, SN65HVD22, SN65HVD23, SN65HVD24
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Device Comparison......................................................... 4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Information....................................................8
8.5 Driver Electrical Characteristics.................................. 8
8.6 Receiver Electrical Characteristics............................. 9
8.7 Driver Switching Characteristics................................. 9
8.8 Receiver Switching Characteristics...........................10
8.9 Receiver Equalization Characteristics...................... 10
8.10 Power Dissipation................................................... 11
8.11 Typical Characteristics............................................ 12
9 Parameter Measurement Information.......................... 14
10 Detailed Description....................................................18
10.1 Overview................................................................. 18
10.2 Functional Block Diagram....................................... 18
10.3 Feature Description.................................................18
10.4 Device Functional Modes........................................20
11 Application and Implementation................................ 23
11.1 Application Information............................................23
11.2 Typical Application.................................................. 23
12 Power Supply Recommendations..............................25
13 Layout...........................................................................26
13.1 Layout Guidelines................................................... 26
13.2 Layout Example...................................................... 26
14 Device and Documentation Support..........................27
14.1 Receiving Notification of Documentation Updates..27
14.2 Support Resources................................................. 27
14.3 Trademarks............................................................. 27
14.4 Electrostatic Discharge Caution..............................27
14.5 Glossary..................................................................27
15 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November 2016) to Revision G (August 2022)
Page
• Deleted the Available Options table....................................................................................................................4
• Changed the D (SOIC) values in the Thermal Information ................................................................................ 8
Changes from Revision E (May 2010) to Revision F (November 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Deleted Ordering Information table; see POA at the end of the data sheet....................................................... 1
• Added maximum temperature value (150°C) to the Storage temperate, Tstg parameter................................... 6
Changes from Revision D (April 2005) to Revision E (May 2010)
Page
• Replaced the Dissipation Rating table with the Thermal Information table........................................................ 8
• Changed IO - Added test condition and values per device number (Driver Electrical Characteristics table)...... 8
• Changed the Thermal Characteristics table to Power Dissipation table........................................................... 11
• Added the TEST MODE DRIVER DISABLE section........................................................................................ 21
Changes from Revision C (September 2003) to Revision D (April 2005)
Page
• Added Receiver output current, IO to the Absolute Maximum Ratings table...................................................... 6
Changes from Revision B (June 2003) to Revision C (September 2003)
Page
• Added the Thermal Information table................................................................................................................. 8
• Added the Theory of Operation section............................................................................................................ 18
• Added the Noise Considerations for Equalized Receivers section...................................................................23
2
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
Changes from Revision A (March 2003) to Revision B (June 2003)
Page
• Added VIK Typical Value of 0.75 V (Driver Electrical Characteristics table)........................................................8
• Deleted VIT(F+) – VCM = –20 V to 25 V Minimum value (Receiver Electrical Characteristics table)...................9
• Added the Receiver Equalization Characteristics table.................................................................................... 10
• Added Figure 8-6, Figure 8-7, and Figure 8-8 to the Typical Characteristics .................................................. 12
• Changed A Input circuit in the Equivalent Input and Output Schematic Diagrams ..........................................22
• Changed the Integrated Receiver Equalization Using the SN65HVD23 section.............................................. 24
Changes from Revision * (December 2002) to Revision A (March 2003)
Page
• Changed tPZH, tPHZ, tPZL, and tPLZ - From a maximum value of 120 to include typical and maximum values for
each entry (Receiver Switching Characteristics table)..................................................................................... 10
• Changed tPZH, tPHZ, tPZL, and tPLZ - From a maximum value of 120 to include typical and maximum values for
each entry (Receiver Switching Characteristics table)..................................................................................... 10
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
5 Description (continued)
The SN65HVD20 device provides high signaling rate (up to 25 Mbps) for interconnecting networks of up to 64
nodes.
The SN65HVD21 device allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver
output slew rate is controlled to provide reliable switching with shaped transitions which reduce high-frequency
noise emissions.
The SN65HVD22 device has controlled driver output slew rate for low radiated noise in emission-sensitive
applications and for improved signal quality with long stubs. Up to 256 SN65HVD22 nodes can be connected at
signaling rates up to 500 kbps.
The SN65HVD23 device implements receiver equalization technology for improved jitter performance on
differential bus applications with data rates up to 25 Mbps at cable lengths up to 160 meters.
The SN65HVD24 device implements receiver equalization technology for improved jitter performance on
differential bus applications with data rates from 1 Mbps to 10 Mbps at cable lengths up to 1000 meters.
The receivers include a failsafe circuit that provides a high-level output within 250 microseconds after loss of the
input signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of
any active transmitters on the bus. This feature prevents noise from being received as valid data under these
fault conditions. This feature may be used for Wired-OR bus signaling.
The SN65HVD2x devices are characterized for operation temperatures from –40°C to 85°C.
6 Device Comparison
Table 6-1. Product Selection Guide
PART NUMBERS
NODES
MARKING
SN65HVD20
Up to 50 m at 25 Mbps
Up to 64
D: VP20, P: 65HVD20
SN65HVD21
Up to 150 m at 5 Mbps (with slew rate limit)
Up to 256
D: VP21, P: 65HVD21
SN65HVD22
Up to1200 m at 500 kbps (with slew rate limit)
Up to 256
D: VP22, P: 65HVD22
SN65HVD23
Up to 160 m at 25 Mbps (with receiver equalization)
Up to 64
D: VP23, P: 65HVD23
SN65HVD24
Up to 500 m at 3 Mbps (with receiver equalization)
Up to 256
D: VP24, P: 65HVD24
(1)
4
CABLE LENGTH AND SIGNALING RATE(1)
Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter.
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
7 Pin Configuration and Functions
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Figure 7-1. D or P Package, 8-Pin SOIC or PDIP
(Top View)
Table 7-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
6
Bus input and output
Driver output or receiver input (complementary to B)
B
7
Bus input and output
Driver output or receiver input (complementary to A)
D
4
Digital input
Driver data input
DE
3
Digital input
Driver enable, active high
GND
5
Reference potential
Local device ground
R
1
Digital output
Receive data output
RE
2
Digital input
VCC
8
Supply
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Receiver enable, active low
4.5-V to 5.5-V supply
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage(2)
Voltage at any bus I/O terminal
Voltage input, transient pulse
A, B
Voltage input
D, DE, RE
(through 100 Ω, see Figure 9-16)
Receiver output current
MIN
MAX
UNIT
–0.5
7
V
–27
27
V
–60
60
V
–0.5
VCC + 0.5
V
–10
10
mA
See Power Dissipation
Ratings
Continuous total power dissipation
Junction temperature, TJ
150
°C
Storage temperature, Tstg
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
8.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
All pins except 5, 6, and 7
±5000
Pins 5, 6, and 7
±16000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
Machine Model (MM) (3)
±200
UNIT
V
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
Tested in accordance with JEDEC Standard 22, Test Method A115-A
8.3 Recommended Operating Conditions
VCC
MIN
NOM
MAX
Supply voltage
4.5
5
5.5
V
Voltage at any bus I/O terminal A, B
–20
25
V
2
VCC
V
0
0.8
V
V
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
Output current
6
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D, DE, RE
A with respect to B
Driver
Receiver
–25
25
–110
110
–8
8
UNIT
mA
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
8.3 Recommended Operating Conditions (continued)
MIN
Driver enabled (DE at VCC),
Receiver enabled (RE at 0 V), No load,
VI = 0 V or VCC
ICC
Supply current
Driver enabled (DE at VCC),
Receiver disabled (RE at VCC), No load,
VI = 0 V or VCC
Driver disabled (DE at 0 V),
Receiver enabled (RE at 0 V), No load
Driver disabled (DE at 0 V), Receiver
disabled (RE at VCC) D open
NOM
MAX
SN65HVD20
6
9
SN65HVD21
8
12
SN65HVD22
6
9
SN65HVD23
7
11
SN65HVD24
10
14
SN65HVD20
5
8
SN65HVD21
7
11
SN65HVD22
5
8
SN65HVD23
5
9
SN65HVD24
8
12
SN65HVD20
4
7
SN65HVD21
5
8
SN65HVD22
4
7
SN65HVD23
4.5
9
SN65HVD24
5.5
10
All SN65HVD2x
UNIT
mA
1
µA
TA
Operating free-air temperature(1)
–40
85
°C
TJ
Junction temperature
–40
130
°C
(1)
Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded.
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SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
8.4 Thermal Information
SN65HVD2x
THERMAL
METRIC(1)
D (SOIC)
P (PDIP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
110.7
52.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
49.9
57.6
°C/W
RθJB
Junction-to-board thermal resistance
56.7
38.6
°C/W
ψJT
Junction-to-top characterization parameter
6.0
19.1
°C/W
ψJB
Junction-to-board characterization parameter
55.9
31.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted).(1)
PARAMETER
Input clamp voltage
II = –18 mA
VO
Open-circuit output voltage
A or B, No load
|VOD(SS)|
Steady-state differential output voltage
MIN
TYP
–1.5
0.75
0
3.3
4.2
RL = 54 Ω, See Figure 9-1
1.8
2.5
With common-mode loading, See Figure 9-2
1.8
Change in steady-state differential output voltage
between logic states
See Figure 9-1 and Figure 9-3
VOC(SS)
Steady-state common-mode output voltage
See Figure 9-1
∆VOC(SS)
Change in steady-state common-mode output
voltage, VOC(H) – VOC(L)
See Figure 9-1 and Figure 9-4
–0.1
VOC(PP)
Peak-to-peak common-mode output voltage,
VOC(MAX) – VOC(MIN)
RL = 54 Ω, CL = 50 pF, See Figure 9-1 and Figure
9-4
0.35
VOD(RING)
Differential output voltage over and under shoot
RL = 54 Ω, CL = 50 pF, See Figure 9-5
II
Input current
D, DE
IO
Output current with power off.
High impedance state output current.
IOS
Short-circuit output current
COD
Differential output capacitance
–0.1
2.1
MAX
2.5
V
0.1
V
2.9
V
0.1
V
V
10%
100
VO = –7 V to 12 V,
Other input = 0 V
SN65HVD2[0,3]
–400
500
SN65HVD2[1,2,4]
–100
125
VO = –20 V to 25 V,
Other input = 0 V
SN65HVD2[0,3]
–800
1000
SN65HVD2[1,2,4]
V
VCC
–100
VO = –20 V to 25 V, See Figure 9-9
UNIT
V
VCC
No load (open circuit)
Δ|VOD(SS)|
(1)
8
TEST CONDITIONS
VIK
µA
µA
–200
250
–250
250
mA
20
pF
All typical values are at VCC = 5 V and 25°C.
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8.6 Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VIT(+)
Positive-going differential input voltage threshold
VIT(–)
Negative-going differential input voltage threshold
VHYS
Hysteresis voltage (VIT+ – VIT–)
VIT(F+)
Positive-going differential input failsafe voltage
threshold
See Figure 9-15
VIT(F–)
Negative-going differential input failsafe voltage
threshold
See Figure 9-15
VIK
Input clamp voltage
II = –18 mA
VOH
High-level output voltage
VID = 200 mV, IOH = –8 mA, See Figure 9-11
VOL
Low-level output voltage
VID = –200 mV, IOL = 8 mA, See Figure 9-11
II(BUS)
Bus input current (power on or power off)
II
Input current
VO = 0.4 V, IO = 8 mA
VCM = –7 V to 12 V
Input resistance
CID
Differential input capacitance
TYP
MAX
60
200
–200
–60
100
130
40
120
200
120
250
–40
VCM = –20 V to 25 V
VCM = –7 V to 12 V
–200
–120
VCM = –20 V to 25 V
–250
–120
4
SN65HVD2[0,3]
–400
SN65HVD2[1,2,4]
–100
125
VI = –20 to 25 V,
Other input = 0 V
SN65HVD2[0,3]
–800
1000
–200
250
100
SN65HVD2[1,2,4]
96
VID = 0.5 + 0.4 sine (2π × 1.5 × 106t)
mV
V
500
–100
24
mV
V
0.4
SN65HVD2[0,3]
mV
V
VI = –7 to 12 V,
Other input = 0 V
SN65HVD2[1,2,4]
UNIT
mV
–1.5
RE
RI
(1)
See Figure 9-10
MIN
VO = 2.4 V, IO = –8 mA
µA
µA
kΩ
20
pF
All typical values are at VCC = 5 V and 25°C.
8.7 Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
SN65HVD2[0,3]
tPLH, tPHL
Differential output propagation delay,
low-to-high and high-to-low
RL = 54 Ω, CL = 50 pF,
See Figure 9-3
SN65HVD2[1,4]
SN65HVD22
tr, tf
Differential output rise time and fall time
RL = 54 Ω, CL = 50 pF,
See Figure 9-3
tPZH, tPHZ
tPZL, tPLZ
RE at 0 V, See Figure
9-6
Propagation delay time,
high-impedance-to-high-level output and
high-level output-to-high-impedance
RE at 0 V, See Figure
9-7
td(standby)
Time from an active differential output to standby
td(wake)
Wake-up time from standby to an active differential
output
tsk(p)
Pulse skew | tPLH – tPHL|
TYP
MAX
6
10
20
20
32
60
160
280
500
12
SN65HVD2[0,3]
2
6
SN65HVD2[1,4]
20
40
60
175
400
600
SN65HVD22
Propagation delay time,
high-impedance-to-high-level output and
high-level output-to-high-impedance
MIN
SN65HVD2[0,3]
40
SN65HVD2[1,4]
100
SN65HVD22
300
SN65HVD2[0,3]
40
SN65HVD2[1,4]
100
SN65HVD22
300
RE at VCC, See Figure 9-8
SN65HVD2[0,3]
ns
ns
ns
ns
2
µs
8
µs
2
SN65HVD2[1,4]
6
SN65HVD22
(1)
UNIT
ns
50
All typical values are at VCC = 5 V and 25°C
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8.8 Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
SN65HVD2[0,3]
MIN
16
35
SN65HVD2[1,2,4]
25
50
2
4
90
120
16
35
90
120
16
35
UNIT
Propagation delay time,
low-to-high level output and
high-to low level output
See Figure 9-11
Receiver output rise time
Receiver output fall time
See Figure 9-11
Receiver output enable time to high level and
disable time from high level
See Figure 9-12
tPLZ
Receiver output enable time to low level and
disable time from low level
See Figure 9-13
tr(standby)
Time from an active receiver output to standby
See Figure 9-14, DE at 0 V
2
µs
tr(wake)
Wake-up time from standby to an active receiver
output
See Figure 9-14, DE at 0 V
8
µs
tsk(p)
Pulse skew |tPLH – tPHL|
tp(set)
Delay time, bus fail to failsafe set
See Figure 9-15, pulse rate = 1 kHz
250
tp(reset)
Delay time, bus recovery to failsafe reset
See Figure 9-15, pulse rate = 1 kHz
50
tPLH
tPHL
tr
tf
tPZH
tPHZ
tPZL
ns
ns
ns
ns
5
ns
350
µs
ns
8.9 Receiver Equalization Characteristics
over recommended operating conditions (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
0m
100 m
25 Mbps
150 m
200 m
200 m
tj(pp)
Peudo-random NRZ code with
a bit pattern length of 216 – 1,
Peak-to-peak eye-pattern jitter
Beldon 3105A cable,
See Figure 10-2
10 Mbps
300 m
5 Mbps
3 Mbps
1 Mbps
(1)
(2)
10
250 m
500 m
500 m
1000 m
TYP
SN65HVD23
2
SN65HVD20
6
SN65HVD23
3
SN65HVD20
15
SN65HVD23
4
SN65HVD20
27
SN65HVD23
8
SN65HVD20
22
SN65HVD23
8
SN65HVD20
34
SN65HVD23
15
SN65HVD20
49
SN65HVD23
27
SN65HVD21
128
SN65HVD24
18
SN65HVD20
93
SN65HVD21
103
SN65HVD23
90
SN65HVD24
16
SN65HVD21
216
SN65HVD24
62
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The SN65HVD20 and SN65HVD21 do not have receiver equalization, but are specified for comparison.
All typical values are at VCC = 5 V, and temperature = 25°C.
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8.10 Power Dissipation
PARAMETERS
TEST CONDITIONS
Typical
PD
Device power dissipation
Worst
case
TSD
VALUE
SN65HVD20: 25 Mbps
VCC = 5 V, TJ = 25°C,
SN65HVD21: 5 Mbps
RL = 54 Ω, CL = 50 pF (driver),
CL = 15 pF (receiver),
SN65HVD22: 500 kbps
50% Duty cycle square-wave signal,
SN65HVD23: 25 Mbps
Driver and receiver enabled
SN65HVD24: 5 Mbps
295
SN65HVD20: 25 Mbps
408
VCC = 5.5 V, TJ = 125°C,
SN65HVD21: 5 Mbps
RL = 54 Ω, CL = 50 pF,
SN65HVD22: 500 kbps
CL = 15 pF (receiver),
50% Duty cycle square-wave signal,
SN65HVD23: 25 Mbps
Driver and receiver enabled
SN65HVD24: 5 Mbps
Thermal shut down junction
temperature
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UNIT
260
233
mW
302
267
342
300
mW
417
352
170
°C
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8.11 Typical Characteristics
150
600
DE = 0 V
DE = 0 V
100
Bus Pin Current - m A
Bus Pin Current - m A
400
200
VCC = 0 V
0
VCC = 5 V
200
50
VCC = 0 V
0
VCC = 5 V
50
100
400
600
-30
-20
0
-10
10
150
-30
30
20
-20
5
ICC - Supply Current - mA
HVD20
VOD - Driver Differential Output Voltage - V
VCC = 5 V,
DE = RE = VCC,
LOAD = 54 Ω, 50 pF
70
65
HVD22
HVD21
60
55
50
45
4.5
VCC = 5.5 V
4
3.5
VCC = 5 V
3
2.5
2
VCC = 4.5 V
1.5
1
0.5
0
40
0.1
10
1
Signaling Rate - Mbps
0
100
Figure 8-3. Supply Current vs Signaling Rate
10
20
30
40
50
60
IL - Driver Load Current - mA
70
80
Figure 8-4. Driver Differential Output Voltage vs Driver Load
Current
30
6
VIT(-)
5
VIT(+)
25
VCM = 25 V
VCM = 25 V
4
VCM = 0 V
3
VCM = 0 V
VCM = 20 V
VCM = 20 V
1
VCC = 5 V,
TA = 25°C,
VIC = 2.5 V,
Cable: Belden 3105A
HVD20 = 25 Mbps
20
15
10
HVD23 = 25 Mbps
5
0
1
-0.2
Peak-to-Peak Jitter - ns
VO - Receiver Output Voltage - V
30
Figure 8-2. SN65HVD2[1,2,4] Bus Pin Current vs Bus Pin
Voltage
75
0
-0.1
0.1
VID - Differential Input Voltage - V
0.2
Figure 8-5. Receiver Output Voltage vs Differential Input Voltage
12
20
10
Bus Pin Voltage - V
Figure 8-1. SN65HVD2[0,3] Bus Pin Current vs Bus Pin Voltage
2
0
-10
Bus Pin Voltage - V
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0
100
120
140
160
Cable Length - m
180
200
Figure 8-6. SN65HVD2[0,3] Peak-to-Peak Jitter vs Cable Length
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8.11 Typical Characteristics (continued)
130
70
HVD21: 500 m Cable
HVD21 = 10 Mbps
110
50
40
HVD20 = 10 Mbps
30
HVD23 = 10 Mbps
20
Peak-to-Peak Jitter - ns
Peak-to-Peak Jitter - ns
60
VCC = 5 V,
TA = 25°C,
VIC = 2.5 V,
Cable: Belden 3105A
90
VCC = 5 V,
TA = 25°C,
VIC = 2.5 V,
Cable: Belden 3105A
70
50
30
10
HVD24: 500 m Cable
HVD24 = 10 Mbps
0
200
220
240
260
Cable Length - m
280
300
Figure 8-7. SN65HVD2[0,1,3,4] Peak-to-Peak Jitter vs Cable
Length
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10
3
3.5
4
4.5
Signaling Rate - Mbps
5
Figure 8-8. SN65HVD2[1,4] Peak-to-Peak Jitter vs Signaling
Rate
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9 Parameter Measurement Information
Note
Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal
generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, ZO = 50
Ω (unless otherwise specified).
IO
II
27 Ω
VOD
0 V or 3 V
50 pF
27 Ω
IO
VOC
Figure 9-1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
IO
VOD
0 V or 3 V
60 Ω
IO
375 Ω
VTEST = -20 V to 25 V
VTEST
Figure 9-2. Driver Test Circuit, VOD With Common-Mode Loading
3V
INPUT
VOD
RL = 54 Ω
Signal
Generator
1.5 V
90%
0V
tPHL
VOD(H)
10%
VOD(L)
tPLH
CL = 50 pF
50 Ω
1.5 V
0V
OUTPUT
tr
tf
Figure 9-3. Driver Switching Test Circuit and Waveforms
27 Ω
A
VA
D
Signal
Generator
50 Ω
B
27 Ω
≈ -3.25 V
VB
50 pF
≈ -1.75 V
VOC(PP)
VOC
∆VOC(SS)
VOC
Figure 9-4. Driver VOC Test Circuit and Waveforms
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VOD(SS)
VOD(RING)
VOD(PP)
0 V Differential
VOD(RING)
VOD(SS)
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L)
steady state values.
Figure 9-5. VOD(RING) Waveform and Definitions
A
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
DE
Signal
Generator
S1
3V
Output
B
1.5 V
DE
CL = 50 pF
1.5 V
0.5 V
tPZH
RL = 110 Ω
0V
VOH
Output
2.5 V
50 Ω
tPHZ
VOff 0
Figure 9-6. Driver Enable and Disable Test, High Output
5V
S1
D
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
DE
RL = 110 Ω
3V
Output
1.5 V
DE
0V
CL = 50 pF
tPZL
Output
Signal
Generator
1.5 V
tPLZ
5V
2.5 V
50 Ω
VOL
0.5 V
Figure 9-7. Driver Enable and Disable Test, Low Output
A
0 V or 3 V
D
RL = 54 Ω
B
DE
Signal
Generator
CL = 50 pF
VOD
3V
DE 1.5 V
0V
td(Wake)
td(Standby)
1.5 V
V OD
0.2 V
50 Ω
Figure 9-8. Driver Standby and Wake Test Circuit and Waveforms
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IOS
VO
Voltage
Source
Figure 9-9. Driver Short-Circuit Test
IO
VID
VO
Figure 9-10. Receiver DC Parameter Definitions
Signal
Generator
50 Ω
Input B
VID
A
B
Signal
Generator
50 Ω
IO
R
CL = 15 pF
1.5 V
50%
Input A
VO
tPLH
Output
90%
1.5 V
tr
0V
tPHL
VOH
10% V
OL
tf
Figure 9-11. Receiver Switching Test Circuit and Waveforms
VCC
VCC
D
DE
A
54 Ω
B
R
RE
Signal
Generator
1 kΩ
3V
0V
RE
1.5 V
0V
CL = 15 pF
tPZH
tPHZ
VOH
VOH -0.5 V
50 Ω
R
1.5 V
GND
Figure 9-12. Receiver Enable Test Circuit and Waveforms, Data Output High
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0V
D
DE
VCC
A
54 Ω
B
RE
5V
1.5 V
0V
CL = 15 pF
RE
Signal
Generator
3V
1 kΩ
R
tPZL
tPLZ
VCC
50 Ω
1.5 V
R
VOL +0.5 V
VOL
Figure 9-13. Receiver Enable Test Circuit and Waveforms, Data Output Low
VCC
Switch Down for V(A) = 1.5 V,
Switch Up for V(A) = -1.5 V
A
1.5 V or
-1.5 V
R
3V
B
1 kΩ
RE
CL = 15 pF
1.5 V
0V
RE
Signal
Generator
tr(Standby)
tr(Wake)
50 Ω
5V
R
1.5 V
VOH
VOH 0.5 V
VOL +0.5 V
VOL
0V
Figure 9-14. Receiver Standby and Wake Test Circuit and Waveforms
200 mV
-40 mV
VID -200 mV
-1.5 V
Bus Data Valid Region
Bus Data
Transition Region
Bus Data Valid Region
tp(SET)
tp(RESET)
VOH
R
1.5 V
VOL
Figure 9-15. Receiver Active Failsafe Definitions and Waveforms
100 Ω
VTEST
0V
Pulse Generator,
15 ms Duration,
1% Duty Cycle
15 ms
1.5 ms
V TEST
Figure 9-16. Test Circuit and Waveforms, Transient Overvoltage Test
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10 Detailed Description
10.1 Overview
The SN65HVD2x family of devices are RS-485 compliant half-duplex transceivers designed for communication
rates up to 500 kbps (SN65HVD22), 3 Mbps (SN65HVD24), 5 Mbps (SN65HVD21), or 25 Mpbs (SN65HVD20
and SN65HVD23). The devices feature extended common-mode range support, which provides immunity to
larger ground potential differences that can occur between nodes that communicate over longer distances.
The SN65HVD23 and the SN65HVD24 devices feature receiver equalization, which reduces the amount of
data-dependent jitter that is introduced by the high-frequency losses associated with long cables.
10.2 Functional Block Diagram
(V A-V B ) : Not High
+
-
Bus Input
Invalid
(VA-V B) : Not Low
Timer
250 Ps
R
RE
1
120 mV
+
120 mV
Active
Filters
2
STANDBY
3
DE
6
D
Slew
Rate
Control
4
7
A
B
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10.3 Feature Description
The SN65HVD2x family of devices integrates a differential receiver and differential driver with additional features
for improved performance in electrically-noisy, long-cable, or other fault-intolerant applications.
The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps
reject spurious noise signals which would otherwise cause false changes in the receiver output state.
Slew rate limiting on the driver outputs (SN65HVD2[1,2,4]) reduces the high-frequency content of signal edges.
This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and the
main bus line. Designers must consider the maximum signaling rate and cable length required for a specific
application, and choose the transceiver best matching those requirements.
When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When
DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D
inputs.
When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance
state. When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential
bus inputs on the A and B pins.
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If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including
auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This
reduces power consumption to less than 5 µW. When either enable input is asserted, the circuitry again
becomes active.
In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to
implement an active receiver failsafe feature. These components determine whether the differential bus signal
is valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the
differential input remains within the transition range for more than 250 µs, the timer expires and set the receiver
output to the high state. If a valid bus input (high or low) is received at any time, the receiver output reflects the
valid bus state, and the timer is reset.
Figure 10-1. SN65HVD22 Receiver Operation With 20-V Offset on Input Signal
k0
(DC
loss)
p1
(MHz)
k1
p2
(MHz)
k2
p3
(MHz)
k3
Similar to 160m of Belden 3105A
0.95
0.25
0.3
3.5
0.5
15
1
Similar to 250m of Belden 3105A
0.9
0.25
0.4
3.5
0.7
12
1
Similar to 500m of Belden 3105A
0.8
0.25
0.6
2.2
1
8
1
Similar to 1000m of Belden 3105A
0.6
0.3
1
3
1
6
1
H(s) = k0
(1–k1) +
k1p1
(s + p1)
(1–k2) +
k p
2 2
(s + p2)
(1–k3) +
Signal
Generator
k p
3 3
(s + p3)
H(s)
Figure 10-2. Cable Attenuation Model for Jitter Measurements
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10.4 Device Functional Modes
The driver and receiver behavior for different input conditions are shown in Table 10-1 and Table 10-2,
respectively.
Table 10-1. Driver Function Table(1)
DEVICE
SN65HVD2[0,1,2]
SN65HVD2[3,4]
(1)
INPUT
ENABLE
D
DE
A
OUTPUTS
H
H
H
L
L
H
L
H
X
L
Z
Z
X
OPEN
Z
Z
OPEN
H
H
L
H
H
H
L
B
L
H
L
H
X
L
Z
Z
X
OPEN
Z
Z
OPEN
H
L
H
Legend: H = high level, L = low level, X = don’t care, Z = high impedance (off), ? = indeterminate
Table 10-2. Receiver Function Table(1)
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
RE
OUTPUT
R
0.2 V ≤ VID
L
H
–0.2 V < VID < 0.2 V
L
H(2)
VID ≤ –0.2 V
L
L
X
H
Z
X
OPEN
Z
Open circuit
L
H
Short Circuit
L
H
Idle (terminated) bus
L
H
(1)
(2)
H = high level, L = low level, Z = high impedance (off)
If the differential input VID remains within the transition range
for more than 250 µs, the integrated failsafe circuitry detects a
bus fault, and set the receiver output to a high state. See Figure
9-15.
R
RE
DE
D
1
2
3
6 A
7
B
4
Figure 10-3. Logic Diagram
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10.4.1 Test Mode Driver Disable
If the input signal to the D pin is such that:
1. the signal has signaling rate above 4 Mbps (for the SN65HVD21 and SN65HVD24),
2. the signal has signaling rate above 6 Mbps (for the SN65HVD20 and SN65HVD23),
3. the signal has average amplitude from 1.2 V to 1.6 V (1.4 V ± 200 mV), or
4. the average signal amplitude remains in this range for 100 µs or longer,
then the driver may activate a test-mode during which the driver outputs are temporarily disabled. This can
cause loss of transmission of data during the period that the device is in the test-mode. The driver is re-enabled
and resumes normal operation whenever the above conditions are not true. The device is not damaged by this
test mode.
Although rare, there are combinations of specific voltage levels and input data patterns within the operating
conditions of the SN65HVD2x family which may lead to a temporary state where the driver outputs are disabled
for a period of time.
Observations:
1. The conditions for inadvertently entering the test mode are dependent on the levels, duration, and duty cycle
of the logic signal input to the D pin. Operating input levels are specified as greater than 2 V for a logic HIGH
input, and less than 0.8 V for a logic LOW input. Therefore, a valid steady-state logic input does not cause
the device to activate the test mode
2. Only input signals with frequency content above 2 MHz (4 Mbps) have a possibility of activating the test
mode. Therefore, this issue should not affect the normal operation of the SN65HVD22 (500 kbps).
3. For operating signaling rates of 4 Mbps (or above), the conditions stated above must remain true over a
period of: 4 Mbps ×100 µs = 400 bits. Therefore, a normal short message does not inadvertently activate the
test model.
4. One example of an input signal which may cause the test mode to activate is a clock signal with frequency
3 MHz and 50% duty cycle (symmetric HIGH and LOW half-cycles) with logic HIGH levels of 2.4 V and logic
LOW levels of 0.4 V. This signal applied to the D pin as a driver input would meet the criteria listed above,
and may cause the test-mode to activate, which would disable the driver. This example situation may occur if
the clock signal is generated from a microcontroller or logic chip with a 2.7-V supply.
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10.4.2 Equivalent Input and Output Schematic Diagrams
RE Inputs
DE Input
D Inputs (HVD20, 21, 22)
D Inputs (HVD23, 24)
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
R1
R3
R1
R3
Input
Input
29 V
R2
R2
29 V
29 V
A and B Outputs
R Output
VCC
VCC
5Ω
Output
Output
9V
29 V
Figure 10-4. Equivalent Input and Output Schematic Diagrams
Table 10-3. Input and Output Resistor Values
DEVICE
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R1, R2
R3
SN65HVD2[0,3]
9 kΩ
45 kΩ
SN65HVD2[1,2,4]
36 kΩ
180 kΩ
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11 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
11.1 Application Information
The SN65HVD2x devices are half-duplex RS-485 transceivers that can be used for bidirectional, multipoint
communication at various data rates over differential transmission lines. These devices support a wide commonmode range, allowing for robust communication even in the presence of voltage differences between the
reference potentials of different nodes on a network.
11.2 Typical Application
Figure 11-1 shows a typical RS-485 application. Transceivers of different nodes are connected to one another
over a shared bus. Twisted-pair cabling with a controlled differential impedance is used, and termination
resistances are placed at the two ends of the cable to match the transmission line impedance and minimize
signal reflections.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
D
D
D
D
Copyright © 2016, Texas Instruments Incorporated
Figure 11-1. Half-Duplex Transceiver Configurations
11.2.1 Design Requirements
As the distances between nodes in an RS-485 network become greater and greater, it becomes more of a
challenge to ensure reliable communication. The increased distance often means that the reference (ground)
potentials has more of a difference between nodes. These ground potential differences give rise to differences
in the common-mode voltages seen by the various transceivers on the bus. Standard RS-485 transceivers are
typically specified to operate over a common-mode voltage from –7 V to 12 V, which may be insufficient for
larger distances. The SN65HVD2x family of devices extends this range to –20 V to 25 V, allowing for greater
communication distances between nodes.
Increased cable lengths can lead to increased jitter, especially in links operating at high data rates. This
increased jitter is due to the attenuation of the cable, which tends to increase with frequency. Having unequal
loss between higher and lower frequencies causes the RS-485 signal to distort, adding some timing deviation
(jitter) to the edge crossings of the RS-485 data. If the jitter amplitude exceeds the jitter tolerance of the receiving
MCU or UART, then bit errors are likely to result in the link. However, jitter can be reduced for a given link
through the use of receiver equalization.
11.2.2 Detailed Design Procedure
11.2.2.1 Noise Considerations for Equalized Receivers
The simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. If
the maximum attenuation of frequencies of interest is 20 dB, increasing the receiver gain by a factor of ten
compensates for the cable. However, this means that signal and noise are amplified. Therefore, the receiver with
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higher gain is more sensitive to noise and it is important to minimize differential noise coupling to the equalized
receiver.
Differential noise is crated when conducted or radiated noise energy generates more voltage on one line of
the differential pair than the other. For this to occur from conducted or electric far-field noise, the impedance to
ground of the lines must differ.
For noise frequency out to 50 MHz, the input traces can be treated as a lumped capacitance if the receiver is
approximately 10 inches or less from the connector. Therefore, matching impedance of the lines is accomplished
by matching the lumped capacitance of each.
The primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material,
distance from the signal return path, stray capacitance, and proximity to other conductors. It is difficult to match
each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines
balanced and less susceptible to differential noise coupling.
Another source of differential noise is from near-field coupling. In this situation, an assumption of equal noisesource impedance cannot be made as in the far-field. Familiarly known as crosstalk, more energy from a nearby
signal is coupled to one line of the differential pair. Minimization of this differential noise is accomplished by
keeping the signal pair close together and physical separation from high-voltage, high-current, or high-frequency
signals.
In summary, follow these guidelines in board layout for keeping differential noise to a minimum.
•
•
•
•
•
Keep the differential input traces short.
Match the length, physical dimensions, and routing of each line of the pair.
Keep the lines close together.
Match components connected to each line.
Separate the inputs from high-voltage, high-frequency, or high-current signals.
11.2.3 Application Curves
Figure 11-2 illustrates the benefits of integrated receiver equalization as implemented in the SN65HVD23
transceiver. In this test setup, a differential signal generator applied a signal voltage at one end of the cable,
which was Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS)
of nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the differential voltage at the receiver
inputs (after the cable attenuation). Channel 2 (bottom) shows the output of the receiver.
Figure 11-3 illustrates the benefits of integrated receiver equalization as implemented in the SN65HVD24
transceiver. In this test setup, a differential signal generator applied a signal voltage at one end of the cable,
which was Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS)
of nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle)
shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel 3
(bottom) shows the output of the receiver.
24
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Product Folder Links: SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21, SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
Figure 11-2. SN65HVD23 Receiver Performance at
25 Mbps Over 150 Meter Cable
Figure 11-3. SN65HVD24 Receiver Performance at
5 Mbps Over 500 Meter Cable
12 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply must be decoupled with a 100-nF
ceramic capacitor placed as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
Copyright © 2022 Texas Instruments Incorporated
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25
SN65HVD20, SN65HVD21, SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
13 Layout
13.1 Layout Guidelines
In addition to the guidelines on differential trace matching given in Section 11.2.2, the layout guidelines below
must be followed:
•
•
•
Route power and ground nets as planes rather than traces, and keep their widths as large as possible to
minimize resistance and inductance while maximizing parasitic capacitance.
If external components (like transient voltage suppression diodes) are used for transient protection, place
them close to the connector port and within the path of the signal lines. Make sure component capacitances
are small enough not to impact the RS-485 signaling at the chosen data rate.
Small-valued series pulse-proof resistances can be used to provide additional immunity to transients. This
is needed to limit input currents if the clamping voltages of external transient protection devices exceed the
absolute maximum ratings of the transceiver. These resistances must be less than 10 Ω so that the RS-485
signal is not overly attenuated.
13.2 Layout Example
Via to ground
Via to VCC
C
R
R
MCU
JMP
R
R
R
R
TVS
SN65HVD2x
Figure 13-1. SN65HVD2x Layout Example
26
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Product Folder Links: SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
SN65HVD20, SN65HVD21, SN65HVD22, SN65HVD23, SN65HVD24
www.ti.com
SLLS552G – DECEMBER 2002 – REVISED SEPTEMBER 2022
14 Device and Documentation Support
14.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
14.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: SN65HVD20 SN65HVD21 SN65HVD22 SN65HVD23 SN65HVD24
27
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65HVD20D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP20
SN65HVD20DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP20
Samples
SN65HVD20P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65HVD20
Samples
SN65HVD21D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP21
SN65HVD21DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP21
Samples
SN65HVD21P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65HVD21
Samples
SN65HVD22D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP22
SN65HVD22DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP22
Samples
SN65HVD22DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP22
Samples
SN65HVD22P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65HVD22
Samples
SN65HVD23D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP23
SN65HVD23DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP23
Samples
SN65HVD23P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
65HVD23
Samples
SN65HVD24D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP24
SN65HVD24DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
VP24
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2022
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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