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SN65HVD233-HT
SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
SN65HVD233-HT 3.3-V CAN Transceiver
1 Features
3 Description
•
•
The SN65HVD233 is used in applications employing
the
controller
area
network
(CAN)
serial
communication physical layer in accordance with the
ISO 11898 standard, with the exception that the
thermal shutdown is removed. As a CAN transceiver,
the device provides transmit and receive capability
between the differential CAN bus and a CAN
controller, with signaling rates up to 1 Mbps.
1
•
•
•
•
•
•
•
•
•
•
•
(1)
Bus-Pin Fault Protection Exceeds ±36 V
Bus-Pin ESD Protection Exceeds 16-kV Human
Body Model (HBM)
Compatible With ISO 11898
Signaling Rates(1) up to 1 Mbps
Extended –7-V to 12-V Common-Mode Range
High-Input Impedance Allows for 120 Nodes
LVTTL I/Os Are 5-V Tolerant
Adjustable Driver Transition Times for Improved
Signal Quality
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode: 200 µA Typical
Power-Up and Power-Down Glitch-Free Bus
Inputs and Outputs
– High-Input Impedance With Low VCC
– Monolithic Output During Power Cycling
Loopback for Diagnostic Functions Available
DeviceNet™ Vendor ID #806
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Down-Hole Drilling
High-Temperature Environments
Industrial Automation
– DeviceNet Data Buses
– Smart Distributed Systems (SDS™)
SAE J1939 Data Bus Interfaces
NMEA 2000 Data Bus Interfaces
ISO 11783 Data Bus Interfaces
CAN Data Bus Interfaces
Controlled Baseline
One Assembly or Test Site
One Fabrication Site
Available in Extreme (–55°C to 210°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments high-temperature products use
highly optimized silicon (die) solutions with design
and process enhancements to maximize
performance over extended temperatures.
Designed for operation in especially harsh
environments, the device features cross wire,
overvoltage, and loss-of-ground protection to ±36 V,
with common-mode transient protection of ±100 V.
This device operates over a –7-V to 12-V commonmode range with a maximum of 60 nodes on a bus.
If the common-mode range is restricted to the ISO
11898 standard range of –2 V to 7 V, up to 120
nodes may be connected on a bus. This transceiver
interfaces the single-ended CAN controller with the
differential CAN bus found in industrial, building
automation, and automotive applications.
Device Information(1)
PART NUMBER
SN65HVD233-HT
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm x 3.91 mm
CFP-HKJ (8)
6.90 mm x 5.65 mm
CFP-HKQ (8)
6.90 mm x 5.65 mm
CDIP SB (8)
40.64 mm x 10.04 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
RS
D
R
LBK
8
7
1
6
CANH
CANL
4
5
Custom temperature ranges available
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD233-HT
SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
3
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Driver Electrical Characteristics ................................ 8
Receiver Electrical Characteristics ........................... 9
Driver Switching Characteristics ............................. 10
Receiver Switching Characteristics......................... 11
Device Switching Characteristics............................ 11
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 15
9
Detailed Description ............................................ 20
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
20
22
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
11 Power Supply Recommendations ..................... 26
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 27
13 Device and Documentation Support ................. 28
13.1 Trademarks ........................................................... 28
13.2 Electrostatic Discharge Caution ............................ 28
13.3 Glossary ................................................................ 28
14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision F (August 2012) to Revision G
•
2
Page
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 6
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5 Description (Continued)
RS (pin 8) provides for three modes of operation: high-speed, slope control, or low-power standby mode. The
high-speed mode of operation is selected by connecting RS directly to ground, thus allowing the driver output
transistors to switch on and off as fast as possible with no limitation on the rise and fall slope. The rise and fall
slope can be adjusted by connecting a resistor to ground at RS, because the slope is proportional to the output
current of the pin. Slope control is implemented with a resistor value of 10 kΩ to achieve a slew rate of
≉ 15 V/μs, and a value of 100 kΩ to achieve ≉ 2 V/μs slew rate. For more information about slope control, refer
to the Application and Implementation section.
The SN65HVD233 enters a low-current standby mode, during which the driver is switched off and the receiver
remains active if a high logic level is applied to RS. The local protocol controller reverses this low-current standby
mode when it needs to transmit to the bus.
A logic high on the loopback (LBK, pin 5) of the SN65HVD233 places the bus output and bus input in a highimpedance state. The remaining circuit remains active and available for the driver to receiver loopback, selfdiagnostic node functions without disturbing the bus.
6 Pin Configuration and Functions
D, JDJ, and HKJ Packages
8-Pin SOIC, CDIP SB, and CFP
Top View
HKQ Package
8-Pin CFP
Top View
D
1
8
RS
GND
2
7
CANH
RS
GND
VCC
1
8
VCC
3
6
CANL
CANH
R
4
5
LBK
CANL
D
LBK
R
5
4
HKQ as formed or HKJ mounted dead bug.
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
D
I
CAN Transmit Data input (Low for dominant and HIGH for recessive bus states)
2
GND
Power
Ground connection
3
VCC
Power
VCC
4
R
O
CAN Receive data output
LoopBack (Active high to enable controller loopback mode)
5
LBK
I
6
CFANL
I/O
Low level CAN bus line
7
CANH
I/O
High level CAN bus line
8
Rs
I
High Speed, Slope control, and standby enable mode input.
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SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
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Bare Die Information
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
15 mils.
Silicon with backgrind
GND
Al-Si-Cu (0.5%)
Origin
a
c
b
d
Bond Pad Coordinates In Microns - Rev A
4
DESCRIPTION
PAD NUMBER
A
B
C
D
D
1
86.40
157.85
203.40
274.85
GND
2
1035.05
69.75
1150.05
184.75
GND
3
1168.15
69.75
1283.15
184.75
VCC
4
1572.05
51.85
1687.05
166.85
VCC
5
1711.95
51.85
1826.95
166.85
R
6
2758.85
237.65
2873.85
352.65
LBK
7
2774.25
1429.985
2889.25
1544.95
CANL
8
1549.90
1544.95
1664.90
1659.95
CANH
9
1351.45
1544.95
1466.45
1659.95
RS
10
83.50
1429.95
198.50
1544.95
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SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
1711 um
Origin
PAD #1
GND
GND
RS
62.5 um
CANH
CANL
2963 um
VCC
VCC
62.5 um
D
HVD233
R
LBK
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SLLS933G – NOVEMBER 2008 – REVISED JANUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Supply voltage range
–0.3
7
V
Voltage range at any bus terminal (CANH or CANL)
–36
36
V
Voltage input range, transient pulse (CANH and CANL) through 100 Ω
(see Figure 19)
–100
100
V
VI
Input voltage range (D, R, RS, LBK)
–0.5
7
V
IO
Receiver output current
–10
10
mA
Tstg
Storage temperature
–65
150
°C
VCC
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins (1)
CANH, CANL, and GND
±16000
All pins
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
UNIT
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
TA = –55°C to 210°C
VCC
Supply voltage
MIN
MAX
UNIT
3
3.6
V
Voltage at any bus terminal (separately or common mode)
–7
12
V
VIH
High-level input voltage
D, LBK
2
5.5
V
VIL
Low-level input voltage
D, LBK
0
0.8
V
VID
Differential input voltage
–6
6
V
Resistance from RS to ground
0
100
kΩ
VI(Rs)
Input voltage at RS for standby
0.75 VCC
5.5
V
IOH
High-level output current
IOL
Low-level output current
TJ
Operating junction temperature
TA
Operating free-air temperature (1)
(1)
6
Driver
–50
Receiver
–10
mA
Driver
50
Receiver
10
–55
mA
212
°C
210
°C
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
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7.4 Thermal Information
SN65HVD233-HT
THERMAL METRIC (1)
D
HJK/HKQ
JDJ
8 PINS
8 PINS
8 PINS
146.1
72.7
RθJA
Junction-to-ambient thermal resistance
106.4
RθJC(top)
Junction-to-case (top) thermal resistance
55.8
23.7
3.1
RθJB
Junction-to-board thermal resistance
46.5
152.0
38.3
ψJT
Junction-to-top characterization parameter
10.7
20.7
6.0
ψJB
Junction-to-board characterization parameter
45.9
93.1
26.9
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Driver Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Bus output
voltage
(dominant)
CANH
VO(D)
Bus output
voltage
(recessive)
CANH
VO
VOD(D)
CANL
CANL
Differential output
voltage (Dominant)
Differential output
voltage (Recessive)
VOD
D = 0 V, RS = 0 V,
See Figure 13 and
Figure 14
TA = 175°C (1)
TA = –55°C to 125°C
MIN
MAX
MIN
2.45
VCC
0.5
1.25
D = 3 V, RS = 0 V,
See Figure 13 and
Figure 14
TYP
TYP
TA = 210°C (2)
MAX
MIN
TYP
2.45
VCC
2.45
VCC
0.5
1.25
0.5
1.25
2.3
2.3
2.3
2.3
2.3
2.3
MAX
UNIT
V
V
D = 0 V, RS = 0 V,
See Figure 13 and
Figure 14
1.5
2
3
1.4
1.75
3
1.4
1.75
3
D = 0 V, RS = 0 V,
See Figure 14 and
Figure 15
1.1
2
3
1.1
1.47
3
1.1
1.47
3
D = 3 V, RS = 0 V,
See Figure 13 and
Figure 14
–120
12
–120
12
–120
12
mV
D = 3 V, RS = 0 V, No
load
–0.5
0.05
–0.5
0.8
–0.5
1.2
V
V
VOC(pp)
Peak-to-peak
common-mode output
voltage
See Figure 21
IIH
High-level
D, LBK
input current
D=2V
–30
30
–30
30
–30
30
μA
IIL
Low-level
D, LBK
input current
D = 0.8 V
–30
30
–30
30
–30
30
μA
VCANH = –7 V,
CANL open,
See Figure 24
–250
Short-circuit output
current
IOS
1
VCANH = 12 V,
CANL open,
See Figure 24
–1
–1
1
–1
250
See receiver input
capacitance
IIRs(s)
RS input current for
standby
RS = 0.75 VCC
8
1
mA
VCANL = –7 V,
CANH open,
See Figure 24
Output capacitance
(1)
(2)
V
–250
1
CO
Supply
current
1
–250
VCANL = 12 V,
CANH open,
See Figure 24
ICC
1
–10
250
–10
250
μA
–10
Standby
RS = VCC, D = VCC,
LBK = 0 V
Dominant
D = 0 V, No load,
LBK = 0 V, RS = 0 V
6
6
6
Recessive
D =t VCC, No load,
LBK = 0 V, RS = 0 V
6
6
6
200
600
400
600
400
600
μA
mA
Minimum and maximum parameters are characterized for operation at TA = 175°C and production tested at TA = 125°C.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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7.6 Receiver Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input
threshold voltage
VIT–
Negative-going
input threshold
voltage
Vhys
Hysteresis voltage
(VIT+ – VIT–)
VOH
High-level output
voltage
IO = –4 mA, See Figure 18
VOL
Low-level output
voltage
IO = 4 mA, See Figure 18
LBK = 0 V, See Table 1
Bus input current
MIN
500
TYP
MAX
620
900
715
MIN
500
100
CANH or
CANL = 12 V
II
TA = 175°C (1)
TA = –55°C to 125°C
CANH or
CANL = 12 V,
VCC = 0 V
CANH or
CANL = –7 V
Other bus
pin = 0 V,
D = 3 V,
LBK = 0 V,
RS = 0 V,
CANH or
CANL = –7 V,
VCC = 0 V
TYP
MAX
600
900
725
TA = 210°C (2)
MIN
500
140
2.4
2.4
TYP
MAX
600
900
mV
725
mV
140
mV
2.4
0.4
UNIT
V
0.4
0.4
140
500
140
500
140
500
200
600
200
700
200
800
–610
–150
–610
–150 –610
–150
–450
–130
–450
–130 –450
–130
V
μA
CI
Input capacitance
(CANH or CANL)
Pin to ground,
VI = 0.4 sin (4E6πt) + 0.5 V,
D = 3 V, LBK = 0 V
45
55
55
pF
CID
Differential input
capacitance
Pin to pin,
VI = 0.4 sin (4E6πt) + 0.5 V,
D = 3 V, LBK = 0 V
15
15
15
pF
RID
Differential input
resistance
RIN
ICC
(1)
(2)
Input resistance
(CANH or CANL)
Supply
current
40
110
40
110
40
110
kΩ
20
51
19
51
18
51
kΩ
600
μA
D = 3 V, LBK = 0 V
Standby
RS = VCC, D = VCC, LBK = 0 V
Dominant
D = 0 V, No load, RS = 0 V,
LBK = 0 V
200
600
400
600
400
6
6
6
Recessive
D = VCC, No load, RS = 0 V,
LBK = 0 V
6
6
6
mA
Minimum and maximum parameters are characterized for operation at TA = 210°C and are not chacterized or production tested at
TA = 175°C.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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7.7 Driver Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Propagation delay
time,
low-to-high-level
output
tPLH
Propagation delay
time,
high-to-low-level
output
tPHL
tsk(p)
Pulse skew
(|tPHL – tPLH|)
Differential output
signal rise time
tr
tf
Differential output
signal fall time
tr
Differential output
signal rise time
tf
Differential output
signal fall time
tr
Differential output
signal rise time
tf
Differential output
signal fall time
ten(s)
Enable time from
standby to
dominant
(1)
(2)
10
TEST CONDITIONS
TA = 175°C (1)
TA = –55°C to 125°C
MIN
MIN
TYP
MAX
TA = 210°C (2)
TYP
MAX
MIN
TYP
RS = 0 V, See Figure 16
35
85
50
50
RS with 10 kΩ to ground,
See Figure 16
70
125
75
75
RS with 100 kΩ to ground,
See Figure 16
500
870
500
500
RS = 0 V,
See Figure 16
70
120
70
70
RS with 10 kΩ to ground,
See Figure 16
130
180
130
130
RS with 100 kΩ to ground,
See Figure 16
870
1200
870
870
RS = 0 V,
See Figure 16
35
9
9
RS with 10 kΩ to ground,
See Figure 16
60
35
35
RS with 100 kΩ to ground,
See Figure 16
370
475
475
MAX
ns
ns
ns
20
70
20
75
20
75
18
70
20
75
20
75
30
135
30
140
30
140
30
135
30
140
30
140
250
1400
250
1400
250
1400
350
1400
350
1400
350
1400
RS = 0 V, See Figure 16
RS with 10 kΩ to ground,
See Figure 16
RS with 100 kΩ to ground,
See Figure 16
See Figure 20
UNIT
ns
ns
ns
0.6
1.5
0.6
1.5
0.6
1.5
μs
Minimum and maximum parameters are characterized for operation at TA = 210°C but not production tested at TA = 175°C or 210°C.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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7.8 Receiver Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-tohigh-level output
tPHL
Propagation delay time, highto-low-level output
TA = 175°C (1)
TA = –55°C to 125°C
MIN
TYP
MAX
35
35
MIN
TYP
MAX
60
50
60
45
TA = 210°C (2)
MIN
UNIT
TYP
MAX
60
50
60
ns
60
45
60
ns
See Figure 18
tsk(p)
Pulse skew (|tPHL – tPLH|)
7
tr
Output signal rise time
2
6.5
6.5
8
6.5
8
ns
tf
Output signal fall time
2
6.5
6.5
9
6.5
9
ns
(1)
(2)
5
5
ns
Minimum and maximum parameters are characterized for operation at TA = 210°C but not production tested at TA = 175°C or 210°C.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
7.9 Device Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
t(LBK)
Loopback delay,
driver input to
receiver output
t(loop1)
Total loop delay,
driver input to
receiver output,
recessive to
dominant
t(loop2)
(1)
(2)
Total loop delay,
driver input to
receiver output,
dominant to
recessive
TEST CONDITIONS
TA = –55°C to 125°C
MIN
TYP
MAX
See Figure 23
7.5
RS = 0 V, See Figure 22
RS with 10 kΩ to ground,
See Figure 22
TA = 175°C (1)
MIN
TYP
MAX
15
12
70
135
105
RS with 100 kΩ to ground,
See Figure 22
TA = 210°C (2)
MIN
TYP
MAX
15
12
15
90
135
90
135
190
115
190
115
190
535
1000
430
1000
430
1000
RS = 0 V, See Figure 22
70
135
98
135
98
135
RS with 10 kΩ to ground,
See Figure 22
105
190
150
190
150
190
RS with 100 kΩ to ground,
See Figure 22
535
1100
880
1200
880
1200
UNIT
ns
ns
ns
Minimum and maximum parameters are characterized for operation at TA = 210°C but not production tested at TA = 175°C or 210°C.
Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
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1000
Estimated Life (Years)
100
Electromigration Fail Mode
10
1
110
130
150
170
190
210
230
Continuous TJ (C)
A.
See the Specifications for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. Operating Life Derating Chart
SN65HVD233HD, SN65HVD233SJD, SN65HVD233SKGDA, SN65HVD233SHKJ, SN65HVD233SHKQ
12
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7.10 Typical Characteristics
Figure 2. Recessive-to-Dominant Loop Time vs Free-Air
Temperature
Figure 3. Dominant-to-Recessive Loop Time vs Free-Air
Temperature
160
VCC = 3.3 V,
Rs, LBK = 0 V,
TA = 25°C,
60- Load
19
VCC = 3.3 V,
Rs, LBK = 0 V,
TA = 25°C
140
I OL - Driver Output Current - mA
I CC - Suppl y Current - mA
20
18
17
16
120
100
80
60
40
20
15
200
300
500
700
1000
0
0
f - Frequenc y - kbps
Figure 4. Supply Current vs Frequency
I OH - Driver High-Le vel Output Current - mA
0.12
1
2
3
VOL - Lo w-Level Output Voltage - V
4
Figure 5. Driver Low-Level Output Current vs Low-Level
Output Voltage
VCC = 3.3 V,
Rs, LBK = 0 V,
TA = 25°C
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
3
VOH - High-Le vel Output Voltage - V
3.5
Figure 6. Driver High-Level Output Current vs High-Level
Output Voltage
Figure 7. Differential Output Voltage vs Free-Air
Temperature
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Typical Characteristics (continued)
Figure 8. Receiver Low-to-High Propagation Delay vs FreeAir Temperature
Figure 9. Receiver High-to-Low Propagation Delay vs FreeAir Temperature
Figure 10. Driver Low-to-High Propagation Delay
vs Free-Air Temperature
Figure 11. Driver High-to-Low Propagation Delay
vs Free-Air Temperature
35
Rs, LBK = 0 V,
TA = 25°C,
RL = 60 Ω
I O - Driver Output Current - mA
30
25
20
15
10
5
0
-5
0
0.6
1.2
1.8
2.4
VCC - Supply Voltage - V
3
3.6
Figure 12. Driver Output Current vs Supply Voltage
14
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8 Parameter Measurement Information
IO(CANH)
II
D
60 Ω ±1%
VO(CANH)
VOD
VI
VO(CANH) + VO(CANL)
IIRs
RS
2
VOC
IO(CANL)
+
VO(CANL)
VI(Rs)
-
Figure 13. Driver Voltage, Current, and Test Definition
Dominant
Recessive
≈3V
VO(CANH)
≈ 2.3 V
≈1V
VO(CANL)
Figure 14. Bus Logic State Voltage Definitions
VI
D
CANH
330 Ω ±1%
VOD
60 Ω ±1%
+
_
RS
CANL
-7 V ≤ VTEST ≤ 12 V
330 Ω ±1%
Figure 15. Driver VOD
CANH
CL = 50 pF ±20%
(see Note B)
D
VI
RL = 60 Ω ±1%
VCC/2
VI
VO
0V
tPLH
tPHL
RS +
(see Note A)
VI(Rs)
-
VCC
VCC/2
VO
VO(D)
90%
0.9 V
0.5 V
10%
CANL
tr
VO(R)
tf
A.
The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes fixture and instrumentation capacitance.
Figure 16. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
CANH
R
VIC =
VI(CANH)
VI(CANH + VI(CANL)
IO
VID
2
VO
CANL
VI(CANL)
Figure 17. Receiver Voltage and Current Definitions
2.9 V
CANH
2.2 V
VI
R
1.5 V
IO
VI
(see Note A)
1.5 V
tPLH
CL = 15 pF ±20%
(see Note B)
CANL
2.2 V
tPHL
VO
50%
10%
VO
90%
90%
tr
VOH
50%
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz,
50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes fixture and instrumentation capacitance.
Figure 18. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
–6.1 V
–7 V
L
12 V
11.1 V
L
–1 V
–7 V
L
MEASURED
R
|VID|
900 mV
900 mV
VOL
6V
12 V
6V
L
6V
–6.5 V
–7 V
H
500 mV
12 V
11.5 V
H
500 mV
–7 V
–1 V
H
6V
12 V
H
6V
Open
Open
H
X
VOH
6V
CANH
R
100 Ω
Pulse Generator
15 µs Duration
1% Duty Cycle
tr, tf ≤ 100 ns
CANL
D at 0 V or V CC
Rs, LBK, at 0 V or V
CC
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 19. Test Circuit, Transient Overvoltage Test
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VI
0V
RS
VCC
CANH
D
60 Ω ±1%
50%
VI
0V
LBK
VOH
CANL
VO
R
-
VOL
t en(s)
VO
+
50%
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 20. Ten(s) Test Circuit and Voltage Waveforms
CANH
27 Ω ±1%
VOC(PP)
D
VI
VOC
RS
CANL
27 Ω ±1%
VOC
50 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 21. VOC(pp) Test Circuit and Voltage Waveforms
0Ω, 10 kΩ,
or 100 kΩ ±5%
RS
DUT
CANH
D
VI
60 Ω ±1%
VCC
50%
VI
50%
0V
LBK
t(loop2)
CANL
VCC
VO
t(loop1)
50%
VOH
50%
VOL
VO
+
-
15 pF ±20%
NOTE: All VI input pulses are supplied by a generator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 22. T(loop) Test Circuit and Voltage Waveforms
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RS
+
VOD
-
LBK
VCC
VCC
CANH
D
VI
www.ti.com
50%
VI
50%
0V
60 Ω ±1%
t(LBK1)
CANL
t(LBK2)
50%
VO
R
VO
+
-
VOH
50%
VOL
t(LBK) = t(LBK1) = t(LBK2)
VOD
≈ 2.3 V
15 pF ±20%
NOTE: All VI input pulses are supplied by agenerator having the following characteristics:
tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 23. T(LBK) Test Circuit and Voltage Waveforms
IOS
IOS
D
0 V or VCC
15 s
CANH
IOS
+
_
0V
VI
12 V
CANL
0V
0V
VI
10 µs
and
VI
-7 V
Figure 24. IOS Test Circuit and Waveforms
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3.3 V
R2 ± 1%
R1 ± 1%
TA = 25°C
VCC = 3.3 V
CANH
+
VID
CANL -
R
R2 ± 1%
Vac
R1 ± 1%
VI
The R Output State Does Not Change During
Application of the Input Waveform.
VID
500 mV
900 mV
R1
50 Ω
50 Ω
R2
280 Ω
130 Ω
12 V
VI
-7 V
NOTE: All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 25. Common-Mode Voltage Rejection
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9 Detailed Description
9.1 Overview
Controller Area Network (CAN) is a robust multi master-master, differential signaling, serial communications bus
specified by the ISO 11898 family of standards. TI's SSN65HVD23x family of transceivers solve specialized
networking requirements for various applications.
Table 2. Available Options
ORDERABLE PART
NUMBER
LOW-POWER MODE
SLOPE
CONTROL
DIAGNOSTIC
LOOPBACK
AUTOBAUD
LOOPBACK
200-μA standby mode
Adjustable
Yes
No
SN65HVD233HD
SN65HVD233SJD
SN65HVD233SKGDA
SN65HVD233SHKJ
SN65HVD233SHKQ
9.2 Functional Block Diagram
RS
D
R
LBK
8
7
1
6
CANH
CANL
4
5
9.3 Feature Description
9.3.1 ISO 11898 Compliance of SN65HVD23x Family of 3.3-V CAN Transceivers
Many users value the low power consumption of operating CAN transceivers from a 3.3-V supply. However,
some are concerned about the interoperability with 5-V supplied transceivers on the same bus. This section
analyzes this situation to address those concerns.
9.3.1.1 Differential Signal
CAN is a differential bus where complementary signals are sent over two wires, and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single-ended output signal.
20
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Feature Description (continued)
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
Figure 26. Typical SN65HVD23x Differential Output Voltage Waveform
The CAN driver creates the difference voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN65HVD23x is greater than 1.5 V and less than 3 V across a 60-Ω load. The minimum
required by ISO 11898 is 1.5 V and the maximum is 3 V. These are the same limiting values for 5-V supplied
CAN transceivers. The bus termination resistors drive the recessive bus state and not the CAN driver.
A CAN receiver is required to output a recessive state with less than 500 mV and a dominant state with more
than 900-mV difference voltage on its bus inputs. The CAN receiver must do this with common-mode input
voltages from –2 V to 7 V. The SN65HVD23x family receivers meet these same input specifications as 5-V
supplied receivers.
9.3.1.1.1 Common-Mode Signal
A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The
common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Obviously, the supply
voltage of the CAN transceiver has nothing to do with noise. The SN65HVD23x family driver lowers the commonmode output in a dominant bit by a couple hundred millivolts from that of most 5-V drivers. While this does not
fully comply with ISO 11898, this small variation in the driver common-mode output is rejected by differential
receivers and does not affect data, signal noise margins, or error rates.
9.3.1.2 Interoperability Of 3.3-V CAN in 5-V CAN Systems
The 3.3-V–supplied SN65HVD23x family of CAN transceivers are electrically interchangeable with 5-V CAN
transceivers. The differential output is the same. The recessive common-mode output is the same. The dominant
common-mode output voltage is a couple hundred millivolts lower than 5-V–supplied drivers, while the receivers
exhibit identical specifications as 5-V devices.
Electrical interoperability does not assure interchangeability however. Most implementers of CAN buses
recognize that ISO 11898 does not sufficiently specify the electrical layer and that strict standard compliance
alone does not ensure interchangeability. This comes only with thorough equipment testing.
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9.4 Device Functional Modes
9.4.1 Function Tables
Table 3. Function Table (Driver) (1)
DRIVER
INPUTS
D
(1)
OUTPUTS
LBK
Rs
X
X
>0.75 VCC
L
L or open
H or open
X
X
H
CANH
CANL
BUS STATE
Recessive
≤0.33 VCC
≤0.33 VCC
Z
Z
H
L
Dominant
Z
Z
Recessive
Z
Z
Recessive
H = high level, L = low level, Z = high impedance, X = irrelevant, ? = indeterminate
Table 4. Function Table (Receiver)
RECEIVER
INPUTS
OUTPUT
BUS STATE
VID = V(CANH) – V(CANL)
LBK
D
Dominant
VID ≥ 0.9 V
L or open
X
L
Recessive
VID ≤ 0.5 V or open
L or open
H or open
H
?
0.5 V < VID < 0.9 V
L or open
H or open
X
X
X
X
H
R
L
L
H
H
9.4.2 Equivalent Input and Output Schematic Diagrams
V CC
V CC
100 kΩ
1 kΩ
INPUT
9V
+
_
Figure 27. D Input
INPUT
Figure 28. RS Input
V CC
110 kΩ
V CC
9 kΩ
110 kΩ
45 kΩ
INPUT
45 kΩ
INPUT
40 V
9 kΩ
40 V
Figure 29. CANH Input
22
9 kΩ
9 kΩ
Figure 30. CANL Input
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V CC
V CC
5Ω
OUTPUT
OUTPUT
9V
40 V
Figure 31. CANH and CANL Outputs
Figure 32. R Output
V CC
1 kΩ
INPUT
9V
100 kΩ
Figure 33. LBK Input
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Diagnostic Loopback
The loopback (LBK) function of the SN65HVD233 is enabled with a high-level input to pin 5. This forces the
driver into a recessive state and redirects the data (D) input at pin 1 to the received-data (R) output at pin 4. This
allows the host controller to input and read back a bit sequence to perform diagnostic routines without disturbing
the CAN bus. A typical CAN bus application is displayed in Figure 34.
If the LBK pin is not used, it may be tied to ground (GND). However, it is pulled low internally (defaults to a lowlevel input) and may be left open if not in use.
10.2 Typical Application
CANH
Bus Lines -- 40 m max
120 Ω
120 Ω
Stub Lines -- 0.3 m max
CANL
5V
Vref
Vcc
Rs
0.1µ F
SN65HVD251
Rs
3.3 V
Vcc
D
CANTX
0.1µ F
SN65HVD233
GND
3.3 V
Vref
SN65HVD230
Rs
GND
R
D
LBK
CANRX
GPIO
CANTX
Vcc
R
D
CANTX
CANRX
0.1µ F
GND
R
CANRX
TMS320LF243
TMS320F2812
TMS320LF2407A
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Figure 34. Typical SN65HVD233 Application
10.2.1 Design Requirements
The High-Speed ISO 11898 Standard specifications are given for a maximum signaling rate of 1 Mbps with a bus
length of 40 m and a maximum of 30 nodes. It also recommends a maximum un-terminated stub length of 0.3 m.
The cable is specified to be a shielded or unshielded twisted-pair with a 120-W characteristic impedance (ZO).
The Standard defines a single line of twisted-pair cable with the network topology as shown in Figure 34. It is
terminated at both ends with 120-W resistors, which match the characteristic impedance of the line to prevent
signal reflections. According to ISO 11898, placing RL on a node should be avoided because the bus lines lose
termination if the node is disconnected from the bus.
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Typical Application (continued)
10.2.2 Detailed Design Procedure
Table 5. Suggested Cable Length vs Signaling Rate
BUS LENGTH (m)
SIGNALING RATE (Mbps)
40
1
100
0.5
200
0.25
500
0.10
1000
0.05
Basically, the maximum bus length is determined by, or rather is a trade-off with the selected signaling rate as
listed in Table 5.
A signaling rate decreases as transmission distance increases. While steady-state losses may become a factor
at the longest transmission distances, the major factors limiting signaling rate as distance is increased are time
varying. Cable bandwidth limitations, which degrade the signal transition time and introduce inter-symbol
interference (ISI), are primary factors reducing the achievable signaling rate when transmission distance is
increased.
For a CAN bus, the signaling rate is also determined from the total system delay – down and back between the
two most distant nodes of a system and the sum of the delays into and out of the nodes on a bus with the typical
5ns/m prop delay of a twisted-pair cable. Also, consideration must be given the signal amplitude loss due to
resistance of the cable and the input resistance of the transceivers. Under strict analysis, skin effects, proximity
to other circuitry, dielectric loss, and radiation loss effects all act to influence the primary line parameters and
degrade the signal.
A conservative rule of thumb for bus lengths over 100 m is derived from the product of the signaling rate in Mbps
and the bus length in meters, which should be less than or equal to 50.
Signaling Rate (Mbps) × Bus Length (m) 0.75 VCC) is applied to Rs, the circuit enters a low-current, listen-only standby mode, during
which the driver is switched off and the receiver remains active. The local controller can reverse this low-power
standby mode when the rising edge of a dominant state (bus differential voltage >900 mV typical) occurs on the
bus.
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10.2.3 Application Curves
25
Rs = 0 Ω
Slope (V/us)
20
15
Rs = 10 k Ω
10
5
Rs = 100 k Ω
0
0
4.7 6.8
10
15
22
33
47
68
100
Slope Control Resistance - kΩ
Figure 36. SN65HVD233 Driver Output Signal Slope vs
Slope Control Resistance Value
Figure 37. Typical SN65HVD233 250-kbps Output Pulse
Waveforms With Slope Control
11 Power Supply Recommendations
TI recommend to have localized capacitive decoupling near device VCC pin to GND. Values of 4.7 µF at VCC
pin and 10 µF, 1µF, and 0.1 µF at supply have tested well on evaluation modules.
12 Layout
12.1 Layout Guidelines
Minimize stub length from node insertion to bus.
26
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12.2 Layout Example
Figure 38. Layout Example
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13 Device and Documentation Support
13.1 Trademarks
SDS is a trademark of Texas Instruments.
DeviceNet is a trademark of Open DeviceNet Vendor Association.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65HVD233HD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 175
233S
Samples
SN65HVD233SHKJ
ACTIVE
CFP
HKJ
8
25
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
SN65HVD233S
HKJ
Samples
SN65HVD233SHKQ
ACTIVE
CFP
HKQ
8
25
RoHS & Green
AU
N / A for Pkg Type
-55 to 210
HVD233S
HKQ
Samples
SN65HVD233SJD
ACTIVE
CDIP SB
JDJ
8
37
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
SN65HVD233SJD
Samples
SN65HVD233SKGDA
ACTIVE
XCEPT
KGD
0
130
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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