SN65HVD251-Q1
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SLLS788 – APRIL 2007
CAN TRANSCEIVER
FEATURES
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(1)
DESCRIPTION
Qualified for Automotive Applications
Drop-In Improved Replacement for the
PCA82C250 and PCA82C251
Bus-Fault Protection of ±36 V
Meets or Exceeds ISO 11898
Signaling Rates(1) up to 1 Mbps
High Input Impedance Allows up to 120
SN65HVD251 Nodes on a Bus
Bus Pins ESD Protection Exceeds 9 kV (HBM)
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode: 200 μA Typical
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down Bus
Protection for Hot Plugging
DeviceNet™ Vendor ID #806
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in bps (bits
per second).
APPLICATIONS
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CAN Data Buses
Industrial Automation
– DeviceNet Data Buses
– Smart Distributed Systems (SDS™)
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
The SN65HVD251 is intended for use in applications
employing the Controller Area Network (CAN) serial
communication physical layer in accordance with the
ISO 11898 Standard. The SN65HVD251 provides
differential transmit capability to the bus and
differential receive capability to a CAN controller at
speeds up to 1 megabit per second (Mbps).
Designed for operation in harsh environments, the
device features crosswire, overvoltage, and loss of
ground protection to ±36 V. Also featured are
overtemperature protection as well as –7-V to 12-V
common-mode range, and tolerance to transients of
±200 V. The transceiver interfaces the single-ended
CAN controller with the differential CAN bus found in
industrial, building automation, and automotive
applications.
Rs, pin 8, selects one of three different modes of
operation: high-speed, slope control, or low-power
mode. The high-speed mode of operation is selected
by connecting pin 8 to ground, allowing the
transmitter output transistors to switch as fast as
possible with no limitation on the rise and fall slope.
The rise and fall slope can be adjusted by
connecting a resistor to ground at pin 8; the slope is
proportional to the pin's output current. Slope control
with an external resistor value of 10 kΩ gives
~15 V/μs slew rate; 100 kΩ gives ~2 V/μs slew rate.
If a high logic level is applied to the Rs pin 8, the
device enters a low-current standby mode where the
driver is switched off and the receiver remains active.
The local protocol controller returns the device to the
normal mode when it transmits to the bus.
function diagram
(positive logic)
D
GND
1
8
Rs
2
7
Vcc
3
4
6
5
CANH
CANL
Vref
R
VCC
3
1
D
RS 8
R
4
5 V
ref
7
CANH
6 CANL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN65HVD251-Q1
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SLLS788 – APRIL 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
PART NUMBER
PACKAGE
MARKED AS
SN65HVD251QDRQ1
8-pin SOIC (Tape and Reel)
251Q1
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
SN65HVD251
Supply voltage range, VCC
–0.3 V to 7 V
Voltage range at any bus terminal
CANH, CANL
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b
CANH, CANL
Input voltage range, VI
D, Rs, R
–36 V to 36 V
±200 V
–0.3 V to VCC + 0.5
Receiver output current, IO
–10 mA to 10 mA
Human-Body Model
Electrostatic discharge
(3)
Charged-Device Model
Machine Model
(4)
CANH, CANL, GND
9 kV
All pins
6 kV
All pins
1 kV
All pins
200 V
Continuous total power dissipation
(1)
(2)
(3)
(4)
See Dissipation Rating Table
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A
Tested in accordance with JEDEC Standard 22, Test Method C101
ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS
PACKAGE
SOIC (D)
(1)
(2)
(3)
2
DERATING FACTOR
ABOVE TA = 25°C
(1)
CIRCUIT BOARD
MODEL
TA = 25°C
POWER RATING
TA = 85°C POWER
RATING
Low-K (2)
576 mW
4.8 mW/°C
288 mW
96 mW
High-K (3)
924 mW
7.7 mW/°C
462 mW
154 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3
In accordance with the High-K thermal metric definitions of EIA/JESD51-7
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TA = 125°C POWER
RATING
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THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
MIN
TYP
UNIT
MAX
θJB
Junction-to-board thermal resistance
78.7
°C/W
θJC
Junction-to-case thermal resistance
44.6
°C/W
PD
TSD
Device power dissipation
VCC = 5 V, TJ = 27°C, RL = 60 Ω,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
97.7
mW
VCC = 5.5 V, TJ = 130°C, RL = 60 Ω,
RS at 0 V, Input to D a 500-kHz 50%
duty cycle square wave
142
mW
Thermal shutdown junction temperature
°C
165
RECOMMENDED OPERATING CONDITIONS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
D input
Low-level input voltage, VIL
D input
Differential input voltage, VID
Input voltage to Rs, VI(Rs)
Input voltage at Rs for standby, VI(Rs)
Rs wave-shaping resistance
High-level output current, IOH
Low-level output current, IOL
Driver
Receiver
(1)
UNIT
V
(1)
12
V
–7
0.7 VCC
V
0.3 VCC
V
–6
6
V
0
VCC
V
0.75 VCC
VCC
V
0
100
kΩ
–50
mA
–4
50
Receiver
4
–40
Junction temperature, Tj
MAX
5.5
Driver
Operating free-air temperature, TA
NOM
4.5
mA
125
°C
145
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
2.75
3.5
4.5
VO(D)
Bus output voltage
(Dominant)
CANH
VO(R)
Bus output voltage
(Recessive)
CANH
VOD(D)
Differential output voltage (Dominant)
Figure 1, D at 0 V, Rs at 0 V
VOD(D)
Differential output voltage (Dominant)
Figure 2 and Figure 3, D at 0 V,
Rs at 0 V
1.2
VOD(R)
Differential output voltage (Recessive)
Figure 1 and Figure 2, D at 0.7 VCC
VOD(R)
Differential output voltage (Recessive)
D at 0.7 VCC, No load
VOC(pp)
Peak-to-peak common-mode output
voltage
Figure 9, Rs at 0 V
IIH
High-level input current, D input
D at 0.7 VCC
IIL
Low-level input current, D input
D at 0.3 VCC
CANL
CANL
Figure 1 and Figure 2, D at 0 V,
Rs at 0 V
Figure 1 and Figure 2, D at 0.7 VCC,
Rs at 0 V
Figure 11, VCANH at –7 V, CANL open
0.5
2
Short-circuit steady-state output current
CO
Output capacitance
See receiver input capacitance
IOZ
High-impedance output current
See receiver input current
IIRs(s)
Rs input current for standby
Rs at 0.75 VCC
IIRs(f)
Rs input current for full-speed operation
Rs at 0 V
Figure 11, VCANL at –7 V, CANH open
2.5
3
2
2.5
3
1.5
2
3
V
2
3.1
V
–120
12
mV
–0.5
0.05
600
(1)
Supply current
V
mV
–40
0
μA
–60
0
μA
–200
2.5
–2
Figure 11, VCANL at 12 V, CANH open
ICC
V
2
Figure 11, VCANH at 12 V, CANL open
IOS(SS)
UNIT
mA
200
μA
–10
–550
0
μA
275
μA
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60-Ω load, Rs at 0 V
65
Recessive
D at VCC, No load, Rs at 0 V
14
mA
All typical values are at 25°C and with a 5-V supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
40
70
Figure 4, Rs with 10 kΩ to ground
90
125
Figure 4, Rs with 100 kΩ to ground
500
800
85
125
Figure 4, Rs at 0 V
tpLH
Propagation delay time, low-to-high-level output
Figure 4, Rs at 0 V
tpHL
Propagation delay time, high-to-low-level output
Figure 4, Rs with 10 kΩ to ground
200
260
Figure 4, Rs with 100 kΩ to ground
1150
1450
Figure 4, Rs at 0 V
tsk(p)
Pulse skew (|tpHL – tpLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from standby to dominant
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
4
Figure 4, Rs at 0 V
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
Figure 8
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45
85
110
180
650
900
UNIT
ns
ns
ns
35
100
ns
35
100
ns
100
250
ns
100
250
ns
600
1550
ns
600
1550
ns
0.5
μs
SN65HVD251-Q1
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage
Figure 6, IO = –4 mA
VOL
Low-level output voltage
Figure 6, IO = 4 mA
MIN
TYP
750
Rs at 0 V, (See Table 1)
500
0.8 VCC
V
0.2 VCC
CANH or CANL at –7 V
Other bus pin at
0 V, Rs at 0 V,
D at 0.7 VCC
715
A
–460
–340
CI
Input capacitance (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V,
D at 0.7 VCC
20
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V,
D at 0.7 VCC
10
RID
Differential input resistance
D at 0.7 VCC, Rs at 0 V
40
RIN
Input resistance (CANH or CANL)
D at 0.7 VCC, Rs at 0 V
20
Supply current
V
600
CANH or CANL at –7 V,
VCC at 0 V
ICC
mV
100
CANH or CANL at 12 V,
VCC at 0 V
Bus input current
900
650
CANH or CANL at 12 V
II
MAX UNIT
pF
pF
100
kΩ
50
kΩ
275
A
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60-Ω load, Rs at 0 V
65
Recessive
D at VCC, No load, Rs at 0 V
14
mA
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TYP
MAX
tpLH
Propagation delay time, low-to-high-level output
PARAMETER
TEST CONDITIONS
MIN
35
50
ns
tpHL
Propagation delay time, high-to-low-level output
35
50
ns
tsk(p)
Pulse skew (|tpHL – tpLH|)
20
ns
tr
Output signal rise time
2
4
ns
tf
Output signal fall time
2
4
ns
tp(sb)
Propagation delay time in standby
500
ns
UNIT
Figure 6
Figure 12, Rs at VCC
UNIT
VREF PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VO
Reference output voltage
TEST CONDITIONS
–5 μA < IO < 5 μA
–50 μA < IO < 50 μA
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MIN
MAX
0.45 VCC
0.55 VCC
0.4 VCC
0.6 VCC
V
5
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DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
60
100
Figure 10, Rs with 10 kΩ to ground
100
150
Figure 10, Rs with 100 kΩ to ground
440
800
Figure 10, Rs at 0 V
115
150
Figure 10, Rs with 10 kΩ to ground
235
290
Figure 10, Rs with 100 kΩ to ground
1070
1450
105
145
Figure 10, Rs at 0 V
tloop1
6
Total loop delay, driver input to receiver
output, recessive to dominant
tloop2
Total loop delay, driver input to receiver
output, dominant to recessive
tloop2
Total loop delay, driver input to receiver
output, dominant to recessive
Figure 10, Rs at 0 V, VCC from 4.5 V to 5.1 V
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MIN
UNIT
ns
ns
ns
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PARAMETER MEASUREMENT INFORMATION
IO(CANH)
VO(CANH)
D
VOD
II
IIRs
Rs
VI
60 W + 1%
+
VO(CANH) + VO(CANL)
2
VOC
IO(CANL)
VI(Rs)
_
VO(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
Dominant
Recessive
93.5 V
VO(CANH)
92.5 V
91.5 V
VO(CANL)
Figure 2. Bus Logic State Voltage Definitions
CANH
VI
D
VOD
330 W 1%
60 W 1%
+
_
RS
CANL
–7 V VTEST 12 V
330 W 1%
Figure 3. Driver VOD
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PARAMETER MEASUREMENT INFORMATION (continued)
CANH
D
VI
RL =
60 +1%
+
VI(Rs)
_
Rs
(see Note A)
CL =
50 pF +20%
(see Note B)
VO
CANH
VCC
VCC/2
VI
VCC/2
0V
tPHL
tPLH
0.9V
VO
90%
0.5V
10%
tr
VO(D)
VO(R)
tf
Figure 4. Driver Test Circuit and Voltage Waveforms
CANH
R
VI(CANH)
VI(CANH) + VI(CANL)
VIC =
2
VI(CANL)
IO
VID
VO
CANL
Figure 5. Receiver Voltage and Current Definitions
CANH
R
VI
CANL
(see Note A)
1.5 V
IO
CL = 15 pF
+20% (see Note B)
VO
3.5 V
VI
2.4 V
2V
1.5 V
tPLH
VO
tPHL
0.7 VCC
10%
90%
tr
VOH
0.3 VCC
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
CANH
R
CANL
100 W
Pulse Generator
15 ms Duration
1% Duty Cycle
tr, tr 3 100 ns
D at 0 V
or VCC
RS at 0 V or VCC
A.
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 7. Test Circuit, Transient Overvoltage Test
Table 1. Receiver Characteristics Over Common Mode Voltage
MEASURED
OUTPUT
VCANH
INPUT
VCANL
|VID|
R
12 V
11.1 V
900 mV
L
–6.1 V
–7 V
900 mV
L
–1 V
–7 V
6V
L
12 V
6V
6V
L
–6.5 V
–7 V
500 mV
H
12 V
11.5 V
500 mV
H
–7 V
–1 V
6V
H
6V
12 V
6V
H
open
open
X
H
VOL
VOH
DUT
CANH
0V
VI
D
60 W 1%
Rs
CANL
R
+
VO
_
15 pF 20%
VCC
0.7 VCC
VI
0V
VOH
0.3 VCC
VO
ten
0.3 VCC
VOL
Figure 8. ten Test Circuit and Voltage Waveforms
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CANH
27 W 1%
D
VI
CANL
27 W 1%
VOC
RS
50 pF 20%
VOC(PP)
VOC
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 9. Peak-to-Peak Common Mode Output Voltage
DUT
CANH
VI
D
60 W + 1%
10 kW or 100 kW + 5%
_
RS
CANL
VRs +
R
+
VO
_
15 pF + 20%
VCC
50%
D Input
0V
tLoop2
tLoop1
VOH
0.7 Vcc
R Output
0.3 Vcc
VOL
Figure 10. tLOOP Test Circuit and Voltage Waveforms
10
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IOS
0 V or VCC
CANH
D
CANL
Rs
Vin –7 V or 12 V
JIOS(SS)J
JIOS(P)J
15 s
0V
12 V
Vin
0V
10 ms
or
0V
Vin
–7 V
Figure 11. Driver Short-Circuit Test
CANH
R
VI
(see Note A)
CANL
CL = 15 pF
1.5 V
VO
(see Note B)
3.5 V
2.4 V
VI
1.5 V
tp(sb)
VOH
VO
0.3 VCC
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 12. Receiver Propagation Delay in Standby Test Circuit and Waveforms
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DEVICE INFORMATION
5V
R2+1%
R1+1%
CANH
+
R
VID
–
CANL
Vac
R1+1%
VI
R2+1%
VID
R1
R2
500 mV
50 W
450 W
900 mV
50 W
227 W
12 V
VI
–7 V
A.
All input pulses are supplied by a generator having the following characteristics: f < 1.5 MHz, TA = 25°C, VCC = 5 V.
Figure 13. Common-Mode Input Voltage Rejection Test
FUNCTION TABLES
Table 2. DRIVER
INPUTS
D
OUTPUTS
Voltage at Rs, VRs
CANH
BUS STATE
CANL
L
VRs < 1.2 V
H
L
Dominant
H
VRs < 1.2 V
Z
Z
Recessive
Open
X
Z
Z
Recessive
X
VRs > 0.75 VCC
Z
Z
Recessive
Table 3. RECEIVER
(1)
12
DIFFERENTIAL INPUTS [VID = V(CANH) – V(CANL)]
OUTPUT R (1)
VID ≥ 0.9 V
L
0.5V < VID < 0.9 V
?
VID ≤ 0.5 V
H
Open
H
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
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R Output
D Input
Vcc
Vcc
100 kW
1 kW
15 W
Input
Output
9V
9V
CANH Input
CANL Input
Vcc
110 kW
Vcc
110 kW
9 kW
45 kW
9 kW
45 kW
Input
Input
40 V
9 kW
40 V
CANH and CANL Outputs
9 kW
Rs Input
Vcc
Vcc
Output
40 V
+
Input
Figure 14. Equivalent Input and Output Schematic Diagrams
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TYPICAL CHARACTERISTICS
tLOOP1 – LOOP TIME
vs
FREE-AIR TEMPERATURE
tLOOP2 – LOOP TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
150
33
72
tLOOP2 – Loop Time – ns
VCC = 4.5 V
VCC = 5 V
70
68
66
VCC = 5.5 V
VCC = 5.5 V
VCC = 5 V
140
135
130
VCC = 4.5 V
64
125
62
–40 –25 –10 5
120
–40 –25 –10 5
20 35 50 65 80 95 110 125
31
30
29
28
27
26
25
0
35 50 65 80 95 110 125
250 500 750 1000 1250 1500 1750 2000
Signaling Rate – kbps
Figure 15.
Figure 16.
Figure 17.
DRIVER LOW-LEVEL OUTPUT
CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
DRIVER HIGH-LEVEL OUTPUT
CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
DOMINANT DIFFERENTIAL
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
140
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
120
100
80
60
40
20
0
VCC = 5 V,
TA = 25°C,
RS = 0 V,
RL = 60 Ω,
CL = 50 pF
32
TA – Free-Air Temperature – C
IOH – Driver High-Level Output Current – mA
IOL – Driver Low-Level Output Current – mA
TA – Free-Air Temperature – C
20
0
1
2
3
4
5
80
VOD(D) – Dominant Differential Output Voltage – V
tLOOP1 – Loop Time – ns
145
ICC – RMS Supply Current – mA
RS = 0 V
RS = 0 V
74
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
70
60
50
40
30
20
10
0
0
1
2
3
4
5
VOCANH – High-Level Output Voltage – V
VOCANL – Low-Level Output Voltage – V
3
VCC = 5.5 V
2.5
2
VCC = 4.5 V
VCC = 5 V
1.5
1
RS = 0 V,
D at 0V,
RL = 60 Ω
0.5
0
–55
–40
0
25
70
85
125
TA – Free-Air Temperature – C
Figure 18.
Figure 19.
Figure 20.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT
FALL TIME
vs
SLOPE RESISTANCE (Rs)
INPUT RESISTANCE MATCHING
vs
FREE-AIR TEMPERATURE
40
30
20
10
TA = 25°C
900
800
VCC = 5.5 V
VCC = 5 V
700
600
VCC = 4.5 V
500
400
300
200
2
3
4
VCC – Supply Voltage – V
Figure 21.
5
6
−0.50
VCC = 5.5 V
−1
−1.50
VCC = 5 V
−2
VCC = 4.5 V
−2.50
100
−3
0
1
Input Resistance Matching − %
50
tf - Differential Output Fall Time - ns
IO – Driver Output Current – mA
TA = 25°C,
RS = 0 V,
D at 0V,
RL = 60 Ω
0
14
0
1000
60
0
10 20 30 40 50 60 70 80 90 100
RS - Slope Resistance - kW
Figure 22.
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−50
0
50
100
TA − Free-Air Temperature − °C
Figure 23.
150
SN65HVD251-Q1
www.ti.com
SLLS788 – APRIL 2007
APPLICATION INFORMATION
The basics of bus arbitration require that the receiver
at the sending node designate the first bit as
dominant or recessive after the initial wave of the
first bit of a message travels to the most remote
node on a network and back again. Typically, this
sample is made at 75% of the bit width, and within
this limitation, the maximum allowable signal
distortion in a CAN network is determined by network
electrical parameters.
Factors to be considered in network design include
the 5 ns/m propagation delay of typical twisted-pair
bus cable; signal amplitude loss due to the loss
mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network.
Under strict analysis, variations among the different
oscillators in a system must also be accounted for
with adjustments in signaling rate and stub and bus
length. Table 4 lists the maximum signaling rates
achieved with the SN65HVD251 in high-speed mode
with several bus lengths of category 5, shielded
twisted-pair (CAT 5 STP) cable.
Table 4. Maximum Signaling Rates for Various
Cable Lengths
BUS LENGTH (m)
SIGNALING RATE (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A bus
with a large number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the ISO 11898 standard, should have as little effect as possible on standard
operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the –2-V to 7-V common-mode range of tolerable
ground noise specified in the standard, helps to ensure data integrity. The HVD251 extends data integrity
beyond that of the standard with an extended –7-V to 12-V range of common-mode operation.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
Figure 24. Typical CAN Differential Signal Eye Pattern
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15
SN65HVD251-Q1
www.ti.com
SLLS788 – APRIL 2007
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of
systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces and cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground
bounce, and electromagnetic interference from nearby electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help ensure data integrity.
Typical Application
Bus Lines – 40 m max
CANH
120 W
120 W
Stub Lines –– 0.3 m max
CANL
Vref
RS
VCC
5V
SN65HVD251
0.1 µF
Vref
RS
VCC
CANTX
R
CANRX
0.1 µF
SN65HVD251
GND
D
5V
RS
VCC
SN65HVD251
GND
D
CANTX
R
CANRX
GND
D
CANTX
R
CANRX
TMS470R1x MCU
TMS470R1x MCU
TMS470R1x MCU
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Figure 25. Typical HVD251 Application
16
Vref
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3.3 V
0.1 µF
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65HVD251QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
251Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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