SN65LBC176AQDRG4

  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 D Designed for Signaling Rates† Up to 30 D D D D D D D D D D D D D SN65LBC176AQD (Marked as B176AQ) SN65LBC176AD (Marked as BL176A) SN65LBC176AP (Marked as 65LBC176A) SN75LBC176AD (Marked as LB176A) SN75LBC176AP (Marked as 75LBC176A) (TOP VIEW) Mbps Bus-Pin ESD Protection Exceeds 12 kV HBM Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987(E) Low Skew Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments Very Low Disabled Supply-Current Requirements . . . 700 µA Maximum Common Mode Voltage Range of −7 V to 12 V Thermal-Shutdown Protection Driver Positive and Negative Current Limiting Open-Circuit Failsafe Receiver Design Receiver Input Sensitivity . . . ± 200 mV Max Receiver Input Hysteresis . . . 50 mV Typ Glitch-Free Power-Up and Power-Down Protection Available in Q-Temp Automotive High Reliability Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND logic diagram (positive logic) DE 3 4 D RE R 2 6 1 7 A Bus B Function Tables DRIVER INPUT D H L X Open description The SN65LBC176A, SN65LBC176AQ, and SN75LBC176A differential bus transceivers are monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. They are designed for balanced transmission lines and are compatible with ANSI standard TIA/EIA-485-A and ISO 8482. The A version offers improved switching performance over its predecessors without sacrificing significantly more power. ENABLE DE H H L H OUTPUTS A B H L L H Z Z H L RECEIVER DIFFERENTIAL INPUTS VA −VB VID ≥ 0.2 V −0.2 V < VID < 0.2 V VID ≤ − 0.2 V X Open H = high level, X = irrelevant, ENABLE RE L L L H L OUTPUT R H ? L Z H L = low level, ? = indeterminate, Z = high impedance (off) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit duration, and much higher signaling rates may be achieved using a different criteria (see TYPICAL CHARACTERISTICS section). Copyright  2000−2008, Texas Instruments Incorporated       !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 1 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 description (continued) The SN65LBC176A, SN65LBC176AQ, and SN75LBC176A combine a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Very low device supply current can be achieved by disabling the driver and the receiver. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) PLASTIC DUAL-IN-LINE 0°C to 70°C SN75LBC176AD SN75LBC176AP −40°C to 85°C SN65LBC176AD SN65LBC176AP −40°C to 125°C SN65LBC176AQD — schematics of inputs and outputs A Input VCC D, DE, and RE Inputs VCC 16 V 100 kΩ 100 kΩ Input Input 8V 16 V 4 kΩ B Input A and B Outputs VCC R Output VCC 16 V 40 Ω 4 kΩ Output 8V VCC 16 V 18 kΩ Output Input 100 kΩ 2 4 kΩ 18 kΩ 1 kΩ 16 V 4 kΩ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 16 V 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 absolute maximum ratings† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V Input voltage, VI (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.5 V Electrostatic discharge: Bus terminals and GND, Class 3, A: (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 12 kV Bus terminals and GND, Class 3, B: (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 400 V All terminals, Class 3, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV All terminals, Class 3, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V Continuous total power dissipation (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. 2. Tested in accordance with MIL−STD−883C, Method 3015.7 3. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature. PACKAGE TA ≤ 25°C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR‡ TA = 70°C POWER RATING ABOVE TA = 25°C TA = 85°C POWER RATING TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW P 1000 mW 8.0 mW/°C 640 mW 520 mW — ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions Supply voltage, VCC Voltage at any bus terminal (separately or common mode), VI or VIC MIN NOM MAX UNIT 4.75 5 5.25 V −7 12 V VCC 0.8 V 12 V High-level input voltage, VIH D, DE, and RE 2 Low-level input voltage, VIL D, DE, and RE 0 −12§ Differential input voltage, VID (see Note 4) Driver High-level output current, IOH Receiver −60 Operating free-air temperature, TA mA −8 Driver Low-level output current, IOL V 60 Receiver 8 SN65LBC176AQ −40 125 SN65LBC176A −40 85 SN75LBC176A 0 70 mA °C C § The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet. NOTE 4: Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIK Input clamp voltage TEST CONDITIONS II = − 18 mA SN65LBC176AQ IO = 0 | VOD | Differential output voltage TYP† −1.5 −0.8 1.5 4 SN65LBC176A, SN75LBC176A See Figure 1 Vtest = − 7 V to 12 V, See Figure 2 6 1.5 3 SN75LBC176A 1.1 1.5 3 SN65LBC176AQ 0.9 1.5 6 SN65LBC176A 1 1.5 3 V SN75LBC176A 1.1 1.5 3 V 0.2 V ∆ VOC(SS) Change in steady-state common-mode output voltage IOZ High-impedance output current See receiver input currents IIH High-level enable input current VI = 2 V −100 VI = 0.8 V −7 V ≤ VO ≤ 12 V −100 ICC Supply current See Figures 1 and 2 VI = 0 or VCC, No load V 1.5 Steady-state common-mode output voltage Short-circuit output current 6 1 VOC(SS) Low-level enable input current V 0.9 Change in magnitude of differential output voltage −0.2 See Figure 1 UNIT SN65LBC176A ∆| VOD | IIL IOS MAX 4 SN65LBC176AQ RL = 54 Ω, MIN SN65LBC176AQ 1.8 2.4 3 SN65LBC176A, SN75LBC176A 1.8 2.4 2.8 SN65LBC176AQ −0.2 0.2 SN65LBC176A, SN75LBC176A −0.1 0.1 V V V µA µA −250 250 Receiver disabled and driver enabled 5 9 Receiver disabled and driver disabled 0.4 0.7 Receiver enabled and driver enabled 8.5 15 mA mA † All typical values are at VCC = 5 V, TA = 25°C. driver switching characteristics over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER SN65LBC176A SN75LBC176A SN65LBC176AQ MIN TYP† UNIT MAX MIN TYP† MAX tPLH tPHL Propagation delay time, low-to-high-level output 2 12 2 6 12 ns Propagation delay time, high-to-low-level output 2 12 2 6 12 ns tsk(p) tr Pulse skew ( | tPLH − tPHL | ) 0.3 1 ns tf Differential output signal fall time tPZH Propagation delay time, high-impedance-to-highlevel output RL = 110 Ω, See Figure 4 tPZL Propagation delay time, high-impedance-to-lowlevel output tPHZ tPLZ Differential output signal rise time RL = 54 Ω, CL = 50 pF, See Figure 3 2 1.2 11 4 7.5 11 ns 1.2 11 4 7.5 11 ns 22 12 22 ns RL = 110 Ω, See Figure 5 25 12 22 ns Propagation delay time, high-level-to-highimpedance output RL = 110 Ω, See Figure 4 22 12 22 ns Propagation delay time, low-level-to-highimpedance output RL = 110 Ω, See Figure 5 22 12 22 ns † All typical values are at VCC = 5 V, TA = 25°C. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIT + Positive-going input threshold voltage VIT − Negative-going input threshold voltage TEST CONDITIONS −0.2 IO = 8 mA VOH VOL High-level output voltage II = − 18 mA VID = 200 mV, Low-level output voltage VID = −200 mV, High-impedance-state output current II Bus input current IIH IIL High-level enable-input current ICC Supply current Low-level enable-input current MAX 0.2 Hysteresis voltage (VIT + − VIT −) IOZ TYP† IO = −8 mA Vhys VIK Enable-input clamp voltage MIN VO = 0 to VCC VIH = 12 V, VIH = 12 V, VCC = 5 V VCC = 0 VIH = − 7 V, VIH = − 7 V, VCC = 5 V VCC = 0 See Figure 6 −0.8 V 4 4.9 V 0.1 0.8 SN65LBC176AQ −10 10 SN65LBC176A, SN75LBC176A −1 1 VIH = 2 V VIL = 0.8 V VI = 0 or VCC, No load mV −1.5 See Figure 6 Other input at 0 V V V 50 IOH = − 8 mA, IOL = 8 mA, UNIT 0.4 1 0.5 1 −0.8 −0.4 −0.8 −0.3 V µA mA −100 µA −100 µA Receiver enabled and driver disabled 4 7 Receiver disabled and driver disabled 0.4 0.7 Receiver enabled and driver enabled 8.5 15 mA † All typical values are at VCC = 5 V, TA = 25°C. receiver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS SN65LBC176A SN75LBC176A SN65LBC176AQ TYP† UNIT MAX MIN TYP† MAX 7 30 7 13 20 ns 7 30 7 MIN tPLH tPHL Propagation delay time, output↑ 13 20 ns tsk(p) tr Pulse skew ( | tPHL − tPLH | ) 6 0.5 1.5 ns Rise time, output 5 2.1 3.3 ns tf Fall time, output 5 2.1 3.3 ns tPZH tPZL Output enable time to high level 50 30 45 ns 50 30 45 ns 60 20 40 ns 40 20 40 ns VID = − 1.5 V to 1.5 V, See Figure 7 Propagation delay time, output↓ See Figure 7 Output enable time to low level tPHZ Output disable time from high level tPLZ Output disable time from low level † All typical values are at VCC = 5 V, TA = 25°C. CL = 10 pF, See Figure 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION Vtest R1 375 Ω Y 27 Ω VOD 0 or 3 V D RL = 60 Ω 0 V or 3 V VOD 27 Ω VOC Z Figure 1. Driver VOD and VOC R2 375 Ω −7 V < Vtest < 12 V Vtest Figure 2. Driver VOD3 3V Input Generator (see Note A) 50 Ω RL = 54 Ω CL = 50 pF (see Note B) VO 1.5 V 1.5 V 0V tPLH Output TEST CIRCUIT tPHL 90% 50% ≈ 1.5 V 10% ≈ − 1.5 V tr tf VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms Output 3V S1 Input 1.5 V 1.5 V 3V Generator (see Note A) 50 Ω CL = 50 pF (see Note B) tPZH RL = 110 Ω 0V 0.5 V VOH Output TEST CIRCUIT 2.3 V tPHZ Voff ≈ 0 V VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION 5V S1 0V Generator (see Note A) 3V Input RL = 110 Ω 1.5 V 1.5 V 0V tPZL Output tPLZ CL = 50 pF (see Note B) 50 Ω 5V 0.5 V 2.3 V Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 5. Driver Test Circuit and Voltage Waveforms IO VID VO Figure 6. Receiver VOH and VOL 3V Input Generator (see Note A) 1.5 V 1.5 V Output 50 Ω 1.5 V 0V tPHL tPLH CL = 10 pF (see Note B) Output 0V 1.3 V 10% 1.3 V tR TEST CIRCUIT VOH 90% VOL tF VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 PARAMETER MEASUREMENT INFORMATION S1 1.5 V 2 kΩ −1.5 V S2 5V CL = 10 pF (see Note B) Generator (see Note A) 5 kΩ 50 Ω S3 TEST CIRCUIT Input 1.5 V 3V S1 to 1.5 V S2 Open S3 Closed 0V Input 1.5 V tPZH 3V S1 to −1.5 V S2 Closed S3 Open 0V tPZL VOH ≈ 4.5 V 1.5 V Output Output 1.5 V 0V VOL 1.5 V Input 3V S1 to 1.5 V S2 Closed S3 Closed 0V Input tPHZ 3V S1 to −1.5 V S2 Closed S3 Closed 0V 1.5 V tPLZ ≈ 1.3 V VOH Output 0.5 V Output 0.5 V ≈ 1.3 V VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 8. Receiver Test Circuit and Voltage Waveforms 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS Receiver Output Driver Input 120 Ω 120 Ω Driver Input Receiver Output Figure 9. Typical Waveform of Non-Return-To-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at 100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition of a logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length perform quite well even though they do not meet the standard definition. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS RMS SUPPLY CURRENT vs FREQUENCY LOGIC INPUT CURRENT vs INPUT VOLTAGE 40 −30 TA = 25°C, VCC = 5 V Driver 35 I I − Input Current − µ A I CC − RMS Supply Current − mA −25 30 TA = 25°C, VCC = 5 V, 50% Duty Cycle Square Wave 25 20 15 10 −20 −15 −10 Receiver −5 5 0 0.05 0.5 1 2 5 10 20 0 30 0 1 f − Frequency − MHz Figure 10 VOL − Low-Level Output voltage − V I I − Input Current − µ A 2.00 TA = 25°C, VCC = 5 V 400 200 0 −200 Bus Input Current −400 1.75 1.50 TA = 25°C, VCC = 5 1.25 1.00 0.75 0.50 0.25 0.00 −6 −4 −2 0 2 4 6 8 10 12 0 VI − Input Voltage − V 10 20 30 40 50 60 70 IOL − Low-Level Output Current − mA Figure 12 10 5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 800 −600 −8 4 3 Figure 11 INPUT CURRENT vs INPUT VOLTAGE 600 2 VI − Input Voltage − V Figure 13 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 80 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs CASE TEMPERATURE 5 VOD − Average Differential Output Voltage − V 2 VOH − High-Level Output Voltage − V 4.5 4 VCC = 5.25 V 3.5 3 2.5 VCC = 5 V 2 VCC = 4.75 V 1.5 TA = 25°C 1 0.5 0 1.5 VCC = 5 V, RL = 54 Ω, VIH = 3 V 1 0.5 0 0 −10 −20 −30 −40 −50 −60 −70 −80 −40 Figure 14 85 7.4 VCC = 5 V, See Figure 7 7.2 Propagation Delay Time − ns 13.6 TPHL Receiver (ns) 70 DRIVER PROPAGATION DELAY TIME vs CASE TEMPERATURE 13.8 13.5 13.4 13.3 13.2 13.1 13 12.9 −40 25 Figure 15 RECEIVER PROPAGATION TIME vs CASE TEMPERATURE 13.7 0 Case Temperature − °C I OH − High-Level Output Current − (mA) VCC = 5 V, See Figure 3 7 6.8 6.6 6.4 6.2 6 5.8 0 70 25 5.6 80 −40 Case Temperature ° C 0 25 70 85 Case Temperature − ° C Figure 16 Figure 17 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 11 
  
      
 
 
  SLLS376D− MAY 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 90 TA = 25°C, VOH = ?, VOL = ? I O − Output Current − mA 65 40 15 IOH −10 −35 −60 −85 IOL −110 −135 −160 −185 −210 0 3 5 4 VCC − Supply Voltage − V 6 Figure 18 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65LBC176AD LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BL176A SN65LBC176ADR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 BL176A Samples SN65LBC176AP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65LBC176A Samples SN65LBC176AQD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 B176AQ Samples SN65LBC176AQDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM B176AQ Samples SN65LBC176AQDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM B176AQ Samples SN65LBC176AQDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM B176AQ Samples SN75LBC176AD LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LB176A SN75LBC176ADG4 LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LB176A SN75LBC176ADR LIFEBUY SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LB176A SN75LBC176ADRG4 LIFEBUY SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LB176A SN75LBC176AP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75LBC176A -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of