SN65LVCP1414
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SLLSEC5A – AUGUST 2012 – REVISED JANUARY 2014
14.2-Gbps Quad Channel, Dual Mode Linear Equalizer
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FEATURES
DESCRIPTION
•
The SN65LVCP1414 is an asynchronous, protocolagnostic, low latency, four-channel linear equalizer
optimized for use up to 14.2Gbps and compensates
for losses in backplane or active cable applications.
The architecture of the SN65LVCP1414 is designed
to work with an ASIC or FPGA with digital
equalization employing Decision Feedback Equalizers
(DFE). The SN65LVCP1414 linear equalizer
preserves the shape of the transmitted signal
ensuring
optimum
DFE
performance.
The
SN65LVCP1414 provides a low power solution while
at the same time extending the effectiveness of DFE.
1
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
Quad Channel, Uni-Directional, Multi-Rate,
Dual-Mode Linear Equalizer with Operation up
to 14.2Gbps Serial Data Rate for Backplane
and Cable Interconnects
Linear Equalization Increases Link Margin for
Systems Implementing Decision Feedback
Equalizers (DFE)
17dB Analog Equalization at 7.1GHz with 1dB
Step Control for Backplane Mode or Cable
Mode
Output Linear Dynamic Range: 1200mV
Bandwidth: >20GHz – Typical
Better than 15dB Return Loss at 7.1GHz
Supports Out-of-Band (OOB) Signaling
Low Power, Typically 80mW per Channel at
2.5V VCC
38-Terminal QFN (Quad Flatpack, No-Lead) 5
mm x 7 mm x 0.75 mm, 0.5 mm Terminal Pitch
Excellent Impedance Matching to 100Ω
Differential PCB Transmission Lines
GPIO or I2C Control
2.5V and 3.3V±5% Single Power Supply
2kV ESD (HBM)
Flow-Through Pin-Out Provides Ease of
Routing
Small Package Size Saves Board Space
Low Power
The SN65LVCP1414 is configurable via I2C or GPIO
interface. Using the I2C interface of the
SN65LVCP1414 enables the user to control
independently the Equalization, Path Gain, and
Output Dynamic Range for each individual channel.
In GPIO mode, Equalization, Path Gain, and Output
Dynamic Range can be set for all channels using the
GPIO Input pins.
The SN65LVCP1414
independently via I2C.
outputs
can
be
disabled
The SN65LVCP1414 operates from a single 2.5V or
3.3V power supply.
The package for the SN65LVCP1414 is a 38 pin 5mm x 7-mm x 0.75-mm QFN (Quad Flat-pack Nolead) lead-free package with 0.5mm pitch and is
characterized for operation from –40°C to 85°C.
APPLICATIONS
•
•
High Speed Links in Telecommunication and
Data Communication
Backplane and Cable Interconnects for 10GbE,
16GFC,10G SONET, SAS, SATA, CPRI, OBSAI,
Infiniband, 10GBase-KR, and XFI/SFI
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2014, Texas Instruments Incorporated
SN65LVCP1414
SLLSEC5A – AUGUST 2012 – REVISED JANUARY 2014
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Backplane Application
TX
ASP
Serdes
ASIC
RX
LVCP1414
RX
ASP
Serdes
TX ASIC
LVCP1414
Figure 1. Typical Backplane Application – Trace Mode
Cable Application
Active Cable
SN65LVCP1414
TX
RX
SN65LVCP1414
ASP
Serdes
ASIC
RX
TX
ASP
Serdes
ASIC
Figure 2. Typical Cable Application – Cable Mode
2
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Block Diagram (GPIO or I2C Mode)
A simplified block diagram of the SN65LVCP1414 is shown in Figure 3 for GPIO or I2C input control mode. This
compact, low power, 14.2Gbps quad-channel dual-mode linear analog equalizer consists of four high-speed data
paths and an input GPIO pin logic-control block and a two-wire interface with a control-logic block.
VCC
GND
VBB
50
VCC
50
Input Buffer
with
Selectable
Equalizer
Output
Driver
50
50
IN[3:0]_P
OUT[3:0]_P
IN[3:0]_N
OUT[3:0]_N
Power-On
Reset
Band-Gap Voltage
Reference and Bias
Current Generation
REXT
1.2 k
VCC
200 k
200 k
DRV_PK#/SCL
DRV_PK#/SCL
SDA
SDA
PWD#
VOD/CS
6 Bit Register
General Setting
3 Bit Register
EQ Control
4 Bit Register
Channel Enable
1 Bit Register
VOD Swing
1 Bit Register
DC Gain
2 Bit Register
AC Gain
PWD#
EQ0/ADD0
EQ0/ADD0
VOD/CS
EQ1/ADD1
EQ1/ADD1
2-Wire Interface & Control Logic
200 k
EQ_MODE/ADD2
EQ_MODE/ADD2
GAIN
GAIN
I2C_EN
I2C_EN
200 k
200 k
Figure 3. Simplified Block Diagram of the SN65LVCP1414
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Package
VCC
PWD#
GAIN
EQ_MODE/ADD2
EQ1/ADD1
EQ0/ADD0
VCC
38
37
36
35
34
33
32
The package pin locations and assignments are shown in Figure 4. The SN65LVCP1414 is packaged in a 5mm
x 7mm x 0.75mm, 38 pin, 0.5mm pitch lead-free QFN.
IN0_P
1
31
OUT0_P
IN0_N
2
30
OUT0_N
VCC
3
29
VCC
IN1_P
4
28
OUT1_P
IN1_N
5
27
OUT1_N
VCC
6
26
VCC
VCC
7
25
VCC
IN2_P
8
24
OUT2_P
IN2_N
9
23
OUT2_N
VCC
10
22
VCC
IN3_P
11
21
OUT3_P
IN3_N
12
20
OUT3_N
SN65LVCP1414 Pinout
38 pin QFN (RLJ) Package
5mm x 7mm with 0.5mm pitch
15
16
17
18
DRV_PK#/SCL
I2C_EN
VOD/CS
REXT
19
14
SDA
VCC
13
VCC
It is required for thermal pad to be soldered to ground
for better thermal performance
Figure 4. Package Drawing (Top View)
4
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Pin Descriptions
PINS
NAME
NO.
DIRECTION TYPE
SUPPLY
DESCRIPTION
DIFFERENTIAL HIGH-SPEED I/O
IN0_P
IN0_N
1
2
Input, (with 50 Ω
termination to input
common mode)
Differential input, lane 0
IN1_P
IN1_N
4
5
Input, (with 50 Ω
termination to input
common mode)
Differential input, lane 1
IN2_P
IN2_N
8
9
Input, (with 50 Ω
termination to input
common mode)
Differential input, lane 2
IN3_P
IN3_N
11
12
Input, (with 50 Ω
termination to input
common mode)
Differential input, lane 3
OUT0_P
OUT0_N
31
30
Output
Differential output, lane 0
OUT1_P
OUT1_N
28
27
Output
Differential output, lane 1
OUT2_P
OUT2_N
24
23
Output
Differential output, lane 2
OUT3_P
OUT3_N
21
20
Output
Differential output, lane 3
CONTROL SIGNALS
SDA
14
Input Output, Open
drain
GPIO mode
No action needed
I2C mode
I2C data. Connect a 10kΩ pull-up resistor externally
DRV_PK#/SCL
15
Input. (with 200kΩ
pull-up)
GPIO mode
HIGH: disable Driver peaking
LOW: enables Driver 6dB AC
peaking
I2C mode
I2C clock. Connect a 10kΩ pull-up resistor externally
I2C_EN
16
Input, (wtih 200kΩ
pull-down)
2.5V/3.3V CMOS
Configures the device operation for I2C or GPIO mode:
HIGH: enables I2C mode
LOW: enables GPIO mode
VOD/CS
17
Input, (with 200kΩ
pull-down)
2.5V/3.3V CMOS
GPIO mode
HIGH: set high VOD range
LOW: set low VOD range
REXT
18
Input, Analog
External Bias Resistor:
1,200 Ω to GND
EQ0/ADD0
33
Input, 2.5V/3.3V
CMOS - 3-state
GPIO mode
Working with EQ1 to determine input
EQ gain.
I2C mode
HIGH: acts as Chip Select
LOW: disables I2C interface
I2C mode
ADD0 along with pins ADD1 and ADD2 comprise the three bits of
I2C slave address.
ADD2:ADD1:ADD0:XXX
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Pin Descriptions (continued)
PINS
NAME
EQ1/ADD1
NO.
34
DIRECTION TYPE
SUPPLY
Input, 2.5V/3.3V
CMOS - 3-state
DESCRIPTION
GPIO mode
Working with EQ0 to determine input
EQ gain steps of approximately 2dB
EQ1
EQ0
EQ
GAIN
GND
GND
000
GND
HiZ
000
GND
VCC
001
HiZ
GND
010
HiZ
HiZ
011
HiZ
VCC
100
VCC
GND
101
VCC
HiZ
110
VCC
VCC
111
I2C mode
ADD1 along with pins ADD0 and ADD2 comprise the three bits of
I2C slave address
ADD2:ADD1:ADD0:XXX
EQ1 and EQ0 works with AC_GAIN and DC_GAIN to determine final EQ gain as this:
EQ1/
EQ0
GAIN
DC
GAIN
(dB)
EQ GAIN
(dB)
000 ~ 111
LOW
-6
1~9
000 ~ 111
HiZ
-6
7 ~ 17
000 ~ 111
HiGH
0
1~9
EQ_MODE/
ADD2
35
Input, (with 200kΩ
pull-down),
2.5V/3.3V CMOS
GPIO mode
HIGH: Trace mode
LOW: Cable mode
I2C mode
ADD2 along with pins ADD1 and ADD0 comprise the three bits of
I2C slave address.
ADD2:ADD1:ADD0:XXX
GAIN
36
Input, 2.5V/3.3V
CMOS - 3-state
GPIO mode
Work with EQ1/EQ0 to set total EQ
Gain. See table above.
I2C mode
No action needed
PWD#
37
Input, (with 200kΩ
pull-up),
2.5V/3.3V CMOS
HIGH: Normal Operation
LOW: Power downs the device, inputs off and outputs disabled, resets I2C
Power
Power supply 2.5V±5%, 3.3V±5%
Ground
The ground center pad is the metal contact at the bottom of the package. This pad must be connected to
the GND plane. At least 15 PCB vias are recommended to minimize inductance and provide a solid
ground. Refer to the package drawing (RLJ-package) for the via placement.
POWER SUPPLY
VCC
3, 6, 7,
10, 13,
19, 22,
25, 26,
29, 32,
38
GND Center
Pad
6
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Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VALUES
UNIT
–0.3 to 4
V
±2.5
V
VCC
Supply voltage range
VIN,DIFF
Differential voltage between INx_P and INx_N
VIN+, IN–
Voltage at Inx_P and fINx_N
–0.5 V to VCC+0.5
V
VIO
Voltage on control IO pins
–0.5 V to VCC+0.5
V
IIN+ IIN–
Continuous current at high speed differential data inputs (differential)
–25 to 25
mA
IOUT+ IOUT–
Continuous current at high speed differential data outputs
–25 to 25
mA
2.0
kV
500
V
ESD
Human Body Model (3) (All Pins)
Charged-Device Model
(4)
(All Pins)
Moisture sensitivity level
3
Reflow temperature package soldering, 4 sec
(1)
(2)
(3)
(4)
260
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
Thermal Information
THERMAL METRIC (1)
Junction-to-ambient thermal resistance (2)
θJA
SN65LVCP1414
RLJ (38 PINS)
36.9
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
10.7
ψJT
Junction-to-top characterization parameter (5)
0.3
ψJB
Junction-to-board characterization parameter (6)
θJCbot
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Junction-to-case (bottom) thermal resistance
UNITS
22.3
(7)
°C/W
10.6
1.9
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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Recommended Operating Conditions
MIN
dR
Operating data rate
VCC
Supply voltage
2.375
VCC
Supply voltage
3.135
TC
Junction temperature
TB
Maximum board temperature
NOM
MAX
UNIT
14.2
Gbps
2.5
2.625
V
3.3
3.465
V
125
°C
85
°C
–10
CMOS DC SPECIFICATIONS
VIH
High-level input voltage
0.8×VCC
VMID
Mid-level input voltage
VCC×0.4
VCC×0.6
V
V
VIL
Low-level input voltage
–0.5
0.2×VCC
V
PSNR BG
Bandgap circuit PSNR
20
dB
Electrical Characteristics (VCC 2.5V ±5%)
over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
POWER CONSUMPTION
PDL
Device power dissipation
VOD = LOW at 2.5V VCC with all 4 channels active
317
475
mW
PDH
Device power dissipation
VOD = HIGH, at 2.5V VCC with all 4 channels active
485
675
mW
PDOFF
Device power with all 4 channels
switched off
Refer to I2C section for device configuration. 2.5V VCC
(1)
10
mW
All typical values are at 25°C and with 2.5V supply unless otherwise noted.
Electrical Characteristics (VCC 3.3V ±5%)
over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
POWER CONSUMPTION
PDL
Device power dissipation
VOD = LOW at 3.3V VCC with all 4 channels active
450
625
mW
PDH
Device power dissipation
VOD = HIGH, at 3.3V VCC with all 4 channels active
697
925
mW
PDOFF
(1)
Device power with all 4 channels
switched off
2
Refer to I C section for device configuration, 3.3V
VCC
10
mW
All typical values are at 25°C and with 2.5V supply unless otherwise noted.
Electrical Characteristics (VCC 2.5V ±5%, 3.3V ±5%)
over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
CMOS DC SPECIFICATIONS
IIH
High level input current
VIN = 0.9 × VCC
-40
17
40
µA
IIL
Low level input current
VIN = 0.1 × VCC
-40
17
40
µA
CML INPUTS (IN[3:0]_P, IN[3:0]_N)
rIN
Differential input resistance
INx_P to INx_N
VIN
Input linear dynamic range
Gain = 0.5
VICM
Input common mode voltage
Internally biased
SCD11
Input differential to common mode
conversion
SDD11
Differential input return loss
(1)
8
100
Ω
1200
mVpp
VCC–0.8
V
100MHz to 7.1GHz
–20
dB
100MHz to 7.1GHz
–15
dB
All typical values are at 25°C and with 2.5V and 3.3V supply unless otherwise noted.
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Electrical Characteristics (VCC 2.5V ±5%, 3.3V ±5%) (continued)
over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
RL = 100 Ω, VOD = HIGH
1200
mVpp
RL = 100 Ω, VOD = LOW
600
mVpp
10
mVpp
VOD
Output linear dynamic range
VOS
Output offset voltage
RL = 100 Ω, 0 V applied at inputs
VOCM
Output common mode voltage
See Figure 5
VCM,RIP
Common mode output ripple
K28.5 pattern at 14.2Gbps on all 4 channels,
No interconnect loss, VOD = HIGH
VOD,RIP
Differential path output ripple
K28.5 pattern at 14.2Gbps on all channels,
No interconnect loss, VIN = 1200mVpp.
VOC(SS)
Change in steady-state commonmode output voltage between logic
states
tR
Rise time (2)
tF
Fall time (2)
SDD22
Differential output return loss
SCC22
Common-mode output return loss
tPLH
Low-to-high propagation delay
tPHL
High-to-low propagation delay
tSK(O)
Inter-Pair (lane to lane) output skew (3)
All outputs terminated with 100 Ω, See Figure 8
tSK(PP)
Part-to-part skew (4)
All outputs terminated with 100 Ω
rOT
Single ended output resistance
Single ended on-chip termination to VCC, Outputs will be AC
coupled
rOM
Output termination mismatch at 1MHz
Drom = 2 ´
Chiso
Channel-to-channel isolation
Frequency at 7.1GHz
OUTNOISE
Output referred noise (5)
VCC-0.4
10
V
20
mVRMS
20
mVpp
±10
mV
Input signal with 30ps rise time, 20% to 80%, See Figure 7
31
ps
Input signal with 30ps fall time, 20% to 80%, See Figure 7
32
ps
100MHz to 7.1GHz
–15
dB
100MHz to 7.1GHz
–5
dB
65
ps
65
ps
See Figure 6
8
ps
50
rp - rn
´ 100
rp + rn
35
ps
50
Ω
5
%
45
dB
10MHz to 7.1GHz, No other noise source present, VOD = LOW
400
µVRMS
10MHz to 7.1GHz, No other noise source present, VOD = HIGH
500
µVRMS
17
dB
3.75
dB
12
dB
EQUALIZATION
EQGain
At 7.1GHz input signal
Equalization Gain, EQ = MAX
Vpre
Output pre-cursor pre-emphasis
Input signal with 3.75 pre-cursor and measure it on the output
signal,
Refer Figure 9. Vpre = 20log(V3/V2)
Vpst
Output post-cursor pre-emphasis
Input signal with 12dB post-cursor and measure it on the output
signal,
Refer Figure 9, Vpst = 20log(V1/V2)
DJ1
Transmit Side application
Residual deterministic jitter at 10.3125 Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain =
Gbps
Low and VOD = High, Trace Mode Test Channel -> 0”, See
Figure 11
DJ2
Receive Side Application
Residual deterministic jitter at 10.3125 Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High
Gbps
and DCGain = High, Trace Mode Test Channel -> 12” (9dB loss
at 5GHz), See Figure 10
DJ3
Residual deterministic jitter at 14.2
Gbps
Transmit Side Application
Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain =
Low and VOD = High, Trace Mode Test Channel -> 0”, See
Figure 11
DJ4
Residual deterministic jitter at 14.2
Gbps
Receive Side Application
Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High
and DCGain = High, Trace Mode Test Channel -> 8” (9dB loss
at 7GHz), See Figure 10
(2)
(3)
(4)
(5)
15
0.016
UIp-p
0.11
UIp-p
0.041
UIp-p
0.13
UIp-p
Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 10 and Figure 11.
tSK(O) is the magnitude of the time difference between the channels.
tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
All noise sources added.
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Parameter Measurement Information
OUT+
OUT-
49.9
. W
VOCM
49.9 W
1 pF
Figure 5. Common Mode Output Voltage Test Circuit
VID = 0 V
IN
tPLH
tPHL
VOD = 0 V
OUT
Figure 6. Propagation Delay Input to Output
Figure 7. Output Rise and Fall Times
OUTx
tSK(0)
OUTy
Figure 8. Output Inter-Pair Skew
10
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V1
V3
V2
0V
V5
Not drawn to scale
V6
V4
Figure 9. Vpre and Vpost (test pattern is 1111111100000000 (8-1s, 8-0s))
TEST
CHANNEL
CHARACTERIZATION
BOARD
SN65LVCP1414
PATTERN
GENERATOR
L = 2"
RX
+
EQ
OUT
L = 2"
OSCILLOSCOPE
Figure 10. Receive Side Performance Test Circuit
TEST
CHANNEL
CHARACTERIZATION
BOARD
SN65LVCP1414
PATTERN
GENERATOR
L = 2"
RX
+
EQ
OUT
OSCILLOSCOPE
L = 2"
Figure 11. Transmit Side Performance Test Circuit
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Equivalent Input and Output Schematic Diagrams
VCC
IN+
RT(SE)
= 50 W
Gain
Stage
+EQ
VCC
RBBDC
RT(SE)
= 50 W
INLineEndTermination
VBB
ESD
Self-Biasing Network
Figure 12. Equivalent Input Circuit Design
VCC
VCC
48 kW
ESD
IN
ESD
48 kW
Figure 13. 3-Level Input Biasing Network
12
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Typical Characteristics
Typical operating condition is at VCC = 2.5V and TA = 25°C, no interconnect line at the output, and with default device settings
(unless otherwise noted).
20
EQ=7, DCGAIN=LOW, ACGAIN=HIGH, VDD=HIGH
EQ=0, ACGAIN=LOW, DCGAIN=LOW, VDD=LOW
EQ=3, ACGAIN=LOW, DCGAIN=LOW, VDD=LOW
EQ=7, ACGAIN=LOW, DCGAIN=LOW, VDD=LOW
EQ=0, ACGAIN=HIGH, DCGAIN=LOW, VDD=LOW
EQ=3, ACGAIN=HIGH, DCGAIN=LOW, VDD=LOW
EQ=7, ACGAIN=HIGH, DCGAIN=LOW, VDD=LOW
18
16
14
12
Amplitude (dB)
10
8
6
4
2
0
−2
−4
−6
−8
0.1
1
10
100
Frequency (GHz)
G001
Figure 14. Typical EQ Gain Profile Curve
0
0
−5
−10
−10
−20
Amplitude (dB)
Amplitude (dB)
−15
−20
−25
−30
−40
−30
−50
−35
−60
−40
−45
0
2
4
6
8
Frequency (GHz)
10
12
14
−70
0
2
4
6
8
Frequency (GHz)
10
12
G002
Figure 15. Differential Input Return Loss
14
G003
Figure 16. Differential to Common Mode Conversion
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5V and TA = 25°C, no interconnect line at the output, and with default device settings
(unless otherwise noted).
0
0
−5
−5
−10
−10
Amplitude (dB)
Amplitude (dB)
−15
−15
−20
−25
−20
−25
−30
−30
−35
−35
−40
−40
0
2
4
6
8
Frequency (GHz)
10
12
−45
14
0
2
4
6
8
Frequency (GHz)
10
12
14
G004
G005
Figure 17. Differential Output Return Loss
Figure 18. Common Mode Output Return Loss
0
0.25
3 meter
6 meter
6 meter (See Note A)
3 meter
6 meter
6 meter (See Note A)
−5
0.2
−10
Magnitude (dB)
Amplitude (mV)
−15
0.15
0.1
−20
−25
−30
−35
0.05
−40
0
0
200
400
600
800 1k 1.2k 1.4k 1.6k 1.8k
Time (ps)
2k
−45
0
2
4
6
Frequency (GHz)
8
G006
A. With SN65LVCP1414 -> EQ = 4, VOD = High, ACGain = HiZ,
DCGain = Low
Figure 19. Cable Mode – Symbol Response
14
10
G007
A. With SN65LVCP1414 -> EQ = 4, VOD = High, ACGain = HiZ,
DCGain = Low
Figure 20. Cable Mode – Frequency Domain
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5V and TA = 25°C, no interconnect line at the output, and with default device settings
(unless otherwise noted).
0.35
0
3 meter
6 meter
6 meter (See Note A)
0.3
3 meter
6 meter
6 meter (See Note A)
−5
−10
−15
Magnitude (dB)
Amplitude (mV)
0.25
0.2
0.15
−20
−25
−30
−35
0.1
−40
0.05
−45
0
0
200
400
600
800 1k
1k
Time (ps)
1k
2k
2k
−50
2k
0
2
4
6
Frequency (GHz)
8
10
G008
G009
A. With SN65LVCP1414 -> EQ = 7, VOD = High, ACGain = High,
DCGain = Low
Figure 21. Trace Mode – Symbol Response
A. With SN65LVCP1414 -> EQ = 7, VOD = High, ACGain = High,
DCGain = Low
Figure 22. Trace Mode - Frequency Domain
Table 1. Control Settings Descriptions
MODE
DCGAIN
ACGAIN
EQ
DC GAIN (dB)
EQ GAIN
(dB)
0
0
0
000 to 111
–6
1 to 9
Short Input Trace; Large Input
Swing
0
0
11
000 to 111
–6
7 to 17
Long Input Trace; Large Input
Swing
0
1
1
000 to 111
0
1 to 9
Short Input Trace; Small Input
Swing
0
1
11
000 to 111
0
2 to 10
Short Input Trace; Small Input
Swing
1
0
0
000 to 111
–6
1 to 9
Short Input Cable; Large Input
Swing
1
0
11
000 to 111
–6
7 to 17
Long Input Cable; Large Input
Swing
1
1
1
000 to 111
0
1 to 9
Short Input Cable; Small Input
Swing
1
1
11
000 to 111
0
2 to 10
Short Input Cable; Small Input
Swing
APPLICATION
Table 2. Control Settings Descriptions
GAIN
DC GAIN
ACGAIN
Low
0
00
HighZ
0
11
High
1
01
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Two-Wire Serial Interface and Control Logic
The SN65LVCP1414 uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are
driven, respectively, by the serial data and serial clock from a microcontroller, for example. The SDA and SCK
pins require external 10kΩ pull-ups to VCC.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out control and status signals. The SN65LVCP1414 is a slave device only which means that it cannot
initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the
transmission. The master device provides the clock signal as well as the START and STOP commands. The
protocol for a data transmission is as follows:
1. START command
2. 7 bit slave address (0000ADD[2:0]) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ. The ADD[2:0] address bits change with the status of the
ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7 bit slave
address is 0000000.
3. 8 bit register address
4. 8 bit register data word
5. STOP command
Regarding timing, the SN65LVCP1414 is I2C compatible. The typical timing is shown in Figure 9 and a complete
data transfer is shown in Figure 10. Parameters for Figure 9 are defined in Table 3.
Bus Idle: Both SDA and SCL lines remain HIGH
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still
wishes to communicate on the bus, it can generate a repeated START condition and address another slave
without first generating a STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The
transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t
acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time
later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by
the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the
master generates the STOP condition.
Figure 23. Two-Wire Serial Interface Timing Diagram
16
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Table 3. Two-Wire Serial Interface Timing Diagram Definitions
SYMBOL
PARAMETER
MIN
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
tBUF
Bus free time between START and STOP conditions
1.3
μs
tHDSTA
Hold time after repeated START condition. After this period, the first clock pulse is generated
0.6
μs
tLOW
Low period of the SCL clock
1.3
μs
tHIGH
High period of the SCL clock
0.6
μs
tSUSTA
Setup time for a repeated START condition
0.6
μs
tHDDAT
Data HOLD time
0
μs
tSUDAT
Data setup time
100
ns
tR
Rise time of both SDA and SCL signals
300
tF
Fall time of both SDA and SCL signals
300
tSUSTO
Setup time for STOP condition
0.6
ns
ns
μs
Figure 24. Two-Wire Serial Interface Data Transfer
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Register Mapping
The register mapping for read/write register addresses 0 (0x00) through 22 (0x18) are shown in Table 4. Table 5
describes the circuit functionality based on the register settings.
Table 4. SN65LVCP1414 Register Mapping Information
Register 0x00 (General Device Settings) R/W
bit 7
bit 6
bit 5
SW_GPIO
PWRDOWN
SYNC_01
bit 4
SYNC_ 23
bit 3
SYNC_ALL
bit 2
EQ_MODE
bit 1
bit 0
RSVD
bit 4
bit 3
LN_EN_CH3
bit 2
LN_EN_CH2
bit 1
LN_EN_CH1
bit 0
LN_EN_CH0
Register 0x02 (Channel 0 Control Settings) R/W
bit 7
bit 6
bit 5
RSVD
EQ2
EQ1
bit 4
EQ0
bit 3
VOD_CTRL
bit 2
DC_GAIN
bit 1
AC_GAIN1
bit 0
AC_GAIN0
Register 0x03 (Channel 0 Enable Settings) R/W
bit 7
bit 6
bit 5
bit 4
bit 3
Register 0x01 (Channel Enable) R/W
bit 7
bit 6
bit 5
bit 2
bit 1
bit 0
DRV_PEAK
EQ_EN
DRV_EN
Register 0x05 (Channel 1 Control Settings) R/W
bit 7
bit 6
bit 5
RSVD
EQ2
EQ1
bit 4
EQ0
bit 3
VOD_CTRL
bit 2
DC_GAIN
bit 1
AC_GAIN1
bit 0
AC_GAIN0
Register 0x06 (Channel 1 Enable Settings) R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
DRV_PEAK
bit 1
EQ_EN
bit 0
DRV_EN
Register 0x08 (Channel 2 Control Settings) R/W
bit 7
bit 6
bit 5
RSVD
EQ2
EQ1
bit 4
EQ0
bit 3
VOD_CTRL
bit 2
DC_GAIN
bit 1
AC_GAIN1
bit 0
AC_GAIN0
Register 0x09 (Channel 2 Enable Settings) R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
DRV_PEAK
bit 1
EQ_EN
bit 0
DRV_EN
Register 0x0B (Channel 3 Control Settings) R/W
bit 7
bit 6
bit 5
RSVD
EQ2
EQ1
bit 4
EQ0
bit 3
VOD_CTRL
bit 2
DC_GAIN
bit 1
AC_GAIN1
bit 0
AC_GAIN0
Register 0x0C (Channel 3 Enable Settings) R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
DRV_PEAK
bit 1
EQ_EN
bit 0
DRV_EN
bit 5
RSVD
bit 4
RSVD
bit 3
RSVD
bit 2
RSVD
bit 1
RSVD
bit 0
RSVD
bit 6
RSVD
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Register 0x0F Read Only
bit 7
bit 6
RSVD
RSVD
Register 0x11 R/W
bit 7
Register 0x12 R/W
bit 7
RSVD
18
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Table 5. SN65LVCP1414 Register Description
REGISTER
0x00
BIT
SYMBOL
FUNCTION
DEFAULT
7
SW_GPIO
Switching logic is controlled by GPIO or I2C:
0 = I2C control
1 = GPIO control
6
PWRDOWN
Power down the device:
0 = Normal operation
1 = Powerdown
5
SYNC_01
All settings from channel 1 will be used for channel 0 and 1:
0 = Channel 0 tracking channel 1 settings
1 = No tracking tracking
4
SYNC_23
All settings from channel 2 will be used for channel 2 and 3:
0 = Channel 3 tracking channel 2 settings
1 = No channel tracking
3
SYNC_ALL
All settings from channel 1 will be used on all channels:
0 = All channels tracking channel 1
1 = No channel tracking
Overwrites SYNC_01 and SYNC_23
2
EQ_MD
Set EQ mode:
0 = Cable mode
1 = Trace mode
RSVD
For TI use only
3
LN_EN_CH3
Channel 3 enable:
0 = Enable
1 = Disable
2
LN_EN_CH2
Channel 2 enable:
0 = Enable
1 = Disable
1
LN_EN_CH1
Channel 1 enable:
0 = Enable
1 = Disable
0
LN_EN_CH0
Channel 0 enable:
0 = Enable
1 = Disable
7
RSVD
6
EQ2
5
EQ1
4
EQ0
3
VOD_CTRL
Channel [x] VOD control:
0 = Low VOD range
1 = High VOD range
2
DC_GAIN_CTRL
Channel [x] EQ DC gain:
0 = Set EQ DC gain to 0.5x
1 = Set EQ DC gain to 1x
1
AC_GAIN_CTRL1
0
AC_GAIN_CTRL0
00000000
1
0
7
6
5
4
0x01
0x02
0x05
0x08
0x0B
00000000
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
00000000
AC Gain Control:
00 = Low
01 = HiZ
11 = High
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Table 5. SN65LVCP1414 Register Description (continued)
REGISTER
BIT
SYMBOL
FUNCTION
DEFAULT
7
6
5
4
3
0x03
0x06
0x09
0x0C
0x0F
2
DRV_PEAK
Channel [x] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6db AC Peaking
1
EQ_EN
Channel [x] EQ stage enable:
0 = Enable
1 = Disable
0
DRV_EN
Channel [x] driver stage enable:
0 = Enable
1 = Disable
7
RSVD
For TI use only
6
RSVD
For TI use only
5
RSVD
For TI use only
4
RSVD
For TI use only
3
RSVD
For TI use only
2
RSVD
For TI use only
1
RSVD
For TI use only
0
RSVD
For TI use only
RSVD
For TI use only
00000000
00110000
7
6
5
0x11
4
00000000
3
2
1
0
7
RSVD
For TI use only
6
5
0x12
4
00000000
3
2
1
0
20
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REVISION HISTORY
Changes from Original (August 2012) to Revision A
Page
•
Changed OUT2_P pin number from 23 to 24 ....................................................................................................................... 5
•
Changed OUT2_N pin number from 24 to 23 ...................................................................................................................... 5
•
Changed OUT3_P pin number from 20 to 21 ....................................................................................................................... 5
•
Changed OUT3_N pin number from 21 to 20 ...................................................................................................................... 5
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65LVCP1414RLJR
ACTIVE
WQFN
RLJ
38
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LVCP
1414
SN65LVCP1414RLJT
ACTIVE
WQFN
RLJ
38
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LVCP
1414
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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