SN65LVCP202RGET

SN65LVCP202 www.ti.com ................................................................................................................................................................................................... SLLS914 – MARCH 2009 Gigabit 2 × 2 CROSSPOINT SWITCH FEATURES 1 • • • • • • • • • • • • Up to 2.5-Gbps Operation Nonblocking Architecture Allows Each Output to Be Connected to Any Input 30 ps of Deterministic Jitter Selectable Transmit Preemphasis Per Lane Receive Equalization Available Packaging: 24-Pin QFN Propagation Delay Times: 500 ps Typical Inputs Electrically Compatible With CML Signal Levels Operates From a Single 3.3-V Supply Outputs Can Be Driven to Hi-Z State Low Power: 290 mW (typ) Integrated Termination Resistors DESCRIPTION The SN65LVCP202 is a 2 × 2 nonblocking crosspoint switch in a flow-through pinout allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 2:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve high signaling speeds while maintaining low signal skews. The SN65LVCP202 incorporates 100-Ω termination resistors for those applications where board space is at a premium. Transmit preemphasis and receive equalization are built in for superior signal integrity performance. The SN65LVCP202 is characterized for operation from –40°C to 85°C. Clock Buffering/Clock MUXing Wireless Base Stations High-Speed Network Routing Telecom/Datacom EQ • • • • 1DE APPLICATIONS 2DE SN65LVCP202 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN65LVCP202 SLLS914 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC DIAGRAM VBB RT EQ P11 P12 S1 1A RT EQ 2 0 1B 1Y 1Z 1 1DE P21 P22 S2 VBB RT 2A 2x1 MUX EQ 2 0 2Y 2Z RT EQ 1 2B 2x1 MUX 2DE e -W -W TERMINAL FUNCTIONS TERMINAL NAME TYPE NO. DESCRIPTION High Speed I/O Differential Inputs (with 50-Ω termination to VBB) xA = P; xB = N Line-side differential inputs, CML compatible 17, 14 16, 13 Differential output xY = P; xZ = N Switch-side differential outputs, VML xDE 24, 7 Input Data enable; active-low; LVTTL; when not enabled, the output is in high-impedance state for power savings. S1, S2 1, 18 Input; S1 = channel 1 Switching selection; LVTTL 22, 21, 9, 10 Input; P11 = channel 1 bit 1 Output preemphasis control; LVTTL 23 Input: Selection for receive equalization setting EQ = 1 (default) is for the 5-dB setting; EQ = 0 is for the 12-dB setting. Power Power supply, 3.3 V ±5% xA xB 2, 5 3, 6 xY xZ Control Signals P11–P22 EQ Power Supply VCC 8, 12, 19 GND 11, 15, 20 Thermal pad VBB 2 Ground The ground center pad of the package must be connected to GND plane with thermal vias. Thermal pad 4 Input Receiver input biasing voltage Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 SN65LVCP202 www.ti.com ................................................................................................................................................................................................... SLLS914 – MARCH 2009 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC IN+ RT(SE) = 50 W Gain Stage + EQ VCC RBBDC RT(SE) = 50 W IN– VBB ESD Line-End Termination Self-Biasing Network Figure 1. Equivalent Input Circuit Design OUT+ 49.9 W OUT– 49.9 W VOCM 1 pF Figure 2. Common-Mode Output Voltage Test Circuit Table 1. CROSSPOINT LOGIC TABLE OUTPUT CHANNEL 1 (1Y/1Z) OUTPUT CHANNEL 2 (2Y/2Z) CONTROL PINS, S1x INPUT SELECTED CONTROL PINS, S2x INPUT SELECTED 0 1A/1B 0 1A/1B 1 2A/2B 1 2A/2B AVAILABLE OPTIONS (1) (2) TA DESCRIPTION –40°C to 85°C Serial multiplexer PACKAGED DEVICE (1) (2) RGE (24-Pin) (Orderable) SN65LVCP202RGE The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP202RGER). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 3 SN65LVCP202 SLLS914 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com DISSIPATION RATINGS PACKAGE THERMAL CHARACTERISTICS (1) Parameter Conditions θJA (junction-to-ambient) Four-layer JEDEC board (JESD51-7) using four thermal vias of 0,3-mm diameter each, airflow = 0 ft/min (0 m/s) (1) NOM 55.4 C/W See the IC Package Thermal Metrics application report (SPRA953) for a detailed explanation of thermal parameters. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC VI Supply voltage range –0.5 V to 6 V Control inputs, all outputs Voltage range ESD TJ (2) Receiver inputs Human-body model (3) Charged-device model (4) 4 kV All pins 500 V See Package Thermal Characteristics table Maximum junction temperature 2 Reflow temperature package soldering, 4 seconds (2) (3) (4) 4 –0.5 V to 4 V All pins Moisture sensitivity level (1) –0.5 V to (VCC + 0.5 V) 260°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to the ground terminals. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 SN65LVCP202 www.ti.com ................................................................................................................................................................................................... SLLS914 – MARCH 2009 RECOMMENDED OPERATING CONDITIONS dR Operating data rate VCC Supply voltage VCC(N) Supply-voltage noise amplitude TJ Junction temperature TA Operating free-air temperature (1) MIN NOM MAX UNIT 2.5 Gbps 3.135 3.3 3.465 10 Hz to 1.25 GHz V 20 mV 125 °C –40 85 °C 1750 DIFFERENTIAL INPUTS VID Receiver peak-to-peak differential input voltage (2) dR(in) ≤ 1.25 Gbps 100 VICM Receiver common-mode input voltage Note: for best jitter performance, ac coupling is recommended. 1.5 mVPP |V VCC * 1.6 | ID 2 V CONTROL INPUTS VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage –0.3 0.8 V 120 Ω DIFFERENTIAL OUTPUTS RL (1) (2) Differential load resistance 80 100 Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Differential input voltage VID is defined as | IN+ – IN– |. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL INPUTS VIT+ Positive-going differential input high threshold VIT– Negative-going differential input low threshold A(EQ) Equalizer gain RT(D) Termination resistance, differential VBB Open-circuit input voltage (input self-bias voltage) R(BBDC) Biasing network dc impedance R(BBAC) Biasing network ac impedance 50 –50 at 1.25 GHz (EQ = 0) mV 12 80 AC-coupled inputs 375 MHz mV 100 dB 120 Ω 1.6 V 30 kΩ 42 Ω 650 mVPP –650 mVPP DIFFERENTIAL OUTPUTS VODH High-level output voltage VODL Low-level output voltage VODB(PP) Output differential voltage without preemphasis (2) VOCM Output common-mode voltage ΔVOC(SS) Change in steady-state common-mode output voltage between logic states (1) (2) RL = 100 Ω ±1%, Px2 = Px1 = 0; 2.5-Gbps alternating 1010-pattern; Figure 3 1000 1300 1500 1.65 See Figure 2 1 mVPP V mV All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not production tested. Differential output voltage V(ODB) is defined as | OUT+ – OUT– |. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 5 SN65LVCP202 SLLS914 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Output preemphasis voltage ratio, V(PE) V ODB(PP) VODPE(PP) MIN TYP (1) Px2:Px1 = 00 0 Px2:Px1 = 01 RL = 100 Ω ±1%; x = Channel 1 or 2; Px2:Px1 = 10 See Figure 3 Px2:Px1= 11 3 MAX UNIT dB 6 9 t(PRE) Preemphasis duration measurement Output preemphasis is set to 9 dB during test; Pxx = 1; Measured with a 100-MHz clock signal; RL = 100 Ω ±1%, See Figure 4 175 ps RO Output resistance Differential on-chip termination between OUT+ and OUT– 100 Ω CONTROL INPUTS IIH High-level input current VIN = VCC IIL Low-level input current VIN = GND R(PU) Pullup resistance 5 –125 µA –90 µA 35 kΩ POWER CONSUMPTION PD Device power dissipation All outputs terminated 100 Ω PZ Device power dissipation in high-impedance state ICC Device current consumption 290 414 mW All outputs in high-impedance state 331 mW All outputs terminated 100 Ω; PRBS 27 – 1 pattern at 2.5 Gbps 115 mA TYP (1) MAX UNIT 3 6 ns 0.5 0.7 ns 0.5 0.7 ns SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MULTIPLEXER t(SM) Multiplexer switch time Multiplexer to valid output DIFFERENTIAL OUTPUTS tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tr Rise time tf Fall time tsk(p) Pulse skew, | tPHL – tPLH | (2) tsk(o) Output skew (3) tsk(pp) Part-to-part skew (4) tzd Switching time, hi-Z to disable tze RJ (1) (2) (3) (4) 6 Propagation delay, input to output See Figure 6 20% to 80% of VO(DB); test pattern: 100-MHz clock signal; See Figure 5 and Figure 8 110 ps 110 ps 20 ps 100 ps 300 ps Assumes 50 Ω to Vcm and 150-pF load on each output 20 ns Switching time, hi-Z to enable Assumes 50 Ω to Vcm and 150-pF load on each output 10 ns Device random jitter, rms See Figure 8 for test circuit. BERT setting 10–15 Alternating 10-pattern. 2 ps-rms All outputs terminated with 100 Ω 25 0.8 All typical values are at 25°C and with 3.3-V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 SN65LVCP202 www.ti.com ................................................................................................................................................................................................... SLLS914 – MARCH 2009 SWITCHING CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER DJ (5) (6) (7) TEST CONDITIONS MIN 0-dB preemphasis Intrinsic deterministic device (Pxx = 0); jitter (5) (6), peak-to-peak See Figure 8 for the test circuit. PRBS 27 – 1 pattern 2.5 Gbps 0-dB preemphasis Absolute deterministic (Pxx = 0); output jitter (7), peak-to-peak See Figure 8 for the test circuit. PRBS 27 – 1 pattern 1.25 Gbps Over 20-inch (50,8-cm) FR4 trace TYP (1) MAX UNIT 30 7 ps ps Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ(OUT) – DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in PSPP. DJ(IN) is the peak-to-peak deterministic jitter of the pattern generator driving the device. The SN65LVCP202 built-in passive input equalizer compensates for ISI. For a 20-inch (50,8-cm) FR4 transmission line with 8-mil (0,2-mm) trace width, the SN65LVCP202 typically reduces jitter by 60 ps from the device input to the device output. Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP202 output. The value is a real value measured with a bit-error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated over the link: DJ(absolute) = DJ(signal generator) + DJ(transmission line) + DJ[intrinsic(SN65LVCP202)]. Table 2. Preemphasis Controls Settings (1) Px2 (1) Px1 (1) OUTPUT PREEMPHASIS LEVEL IN dB OUTPUT LEVEL IN mVPP DE-EMPHASIZED PREEMPHASIZED TYPICAL FR4 TRACE LENGTH 0 0 0 dB 1200 1200 10 inches (25,4 cm) 0 1 3 dB 850 1200 20 inches (50,8 cm) 1 0 6 dB 600 1200 30 inches (76,2 cm) 1 1 9 dB 425 1200 40 inches (101,6 cm) x = 1 or 2 Table 2. Receive Equalization Settings EQ Equalization Typical Line Trace 1 5 dB 25 inches (63,5 cm) of FR4 0 12 dB 43 inches (109,2 cm) of FR4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 7 SN65LVCP202 SLLS914 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 3−dB Preemphasis VODPE3(pp) 9−dB Preemphasis VOCM VODB(PP) VODPE2(pp) 6−dB Preemphasis VODPE1(pp) 0−dB Preemphasis VOH VOL Figure 3. Preemphasis and Output Voltage Waveforms and Definitions 1−bit VODPE3(pp) 9−dB Preemphasis 1 to N bit VODB(PP) 80% 20% tPRE Figure 4. t(PRE) Preemphasis Duration Measurement 80% 80% VODB 20% 20% tr tf Figure 5. Driver Output Transition Time 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP202 SN65LVCP202 www.ti.com ................................................................................................................................................................................................... SLLS914 – MARCH 2009 PARAMETER MEASUREMENT INFORMATION (continued) VID = 0 V IN t PHLD t PLHD VOD = 0 V OUT Figure 6. Propagation Delay Input to Output VA 0V Clock Input 0V Ideal Output VB VY–VZ 1/fO Period Jitter 1/fO Cycle-to-Cycle Jitter Actual Output Actual Output 0V 0V VY–VZ VY–VZ tc(n) tc(n) tc(n +1) tjit(cc) = | tc(n) - tc(n + 1) | tjit(pp) = | tc(n) - 1/fO | Peak-to-Peak Jitter VY VA PRBS Input 0V PRBS Output 0V VZ VB tjit(pp) A. All input pulses are supplied by an Agilent 81250 Stimulus System. B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software. Figure 7. Driver Jitter Measurement Waveforms DC Block DC Block Pattern D+ Generator Coax SMA DC Block D– Coax SMA 400-mVPP Differential