SN65LVCP40RGZT

SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 DC TO 4-GBPS DUAL 1:2 MULTIPLEXER/REPEATER/EQUALIZER • FEATURES • • • • • • • Receiver Equalization and Selectable Driver Preemphasis to Counteract High-Frequency Transmission Line Losses Integration of Two-Serial Port Selectable Loopback Typical Power Consumption 650 mW 30-ps Deterministic Jitter On-Chip 100-Ω Receiver and Driver Differential Termination Resistors Eliminate External Components and Reflection from Stubs 3.3-V Nominal Power Supply • 48-Terminal QFN (Quad Flatpack) 7 mm × 7 mm × 1 mm, 0.5-mm Terminal Pitch Temperature Range: -40°C to 85°C APPLICATIONS • • • • • Bidirectional Link Replicator Signal Conditioner XAUI 802.3ae Protocol Backplane Redundancy Host Adapter (Applications With Internal and External Connection to SERDES) Signaling Rates DC to 4 Gbps Including XAUI, GbE, FC, HDTV DESCRIPTION The SN65LVCP40 is a signal conditioner and data multiplexer optimized for backplanes. Input equalization and programmable output preemphasis support data rates up to 4 Gbps. Common applications are redundancy switching, signal buffering, or performance improvements on legacy backplane hardware. The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver with a 2:1 input multiplexer. The drivers provide four selectable levels of preemphasis to compensate for transmission line losses. The receivers incorporates receive equalization and compensates for input transmission line loss. This minimizes deterministic jitter in the link. The equalization is optimized to compensate for a FR-4 backplane trace with 5-dB, high-frequency loss between 375 MHz and 1.875 GHz. This corresponds to a 24-inch long FR-4 trace with 6-mil trace width. This device operates from a single 3.3-V supply. The device has integrated 100-Ω line termination and provides self-biasing. The input tolerates most differential signaling levels such as LVDS, LVPECL or CML. The output impedance matches 100-Ω line impedance. The inputs and outputs may be ac coupled for best interconnectivity with other devices such as SERDES I/O or additional XAUI multiplexer buffer. With ac coupling, jitter is the lowest. FUNCTIONAL DIAGRAM Input Equalization Opens up Data Eye EQ Input Data After Long Backplane Trace Programmable Preemphasis out  
Output Data Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65LVCP40 is packaged in a 7 mm × 7 mm × 1 mm QFN (quad flatpack no-lead) lead-free package, and is characterized for operation from -40°C to 85°C. AVAILABLE OPTIONS (1) TA DESCRIPTION -40°C to 85°C Serial multiplexer PACKAGED DEVICE (1) RGZ (48 pin) SN65LVCP40 The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP40RGZR). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) –0.5 V to 6 V Control inputs, all outputs Voltage range ESD TJ (1) (2) (3) (4) Receiver inputs Human Body Model (3) Charged-Device –0.5 V to (VCC + 0.5 V) –0.5 V to 4 V All pins Model (4) 4 kV All pins 500 V See Package Thermal Characteristics Table Maximum junction temperature Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. PACKAGE THERMAL CHARACTERISTICS PACKAGE THERMAL CHARACTERISTICS (1) NOM UNIT θJA (junction-to-ambient) 33 °C/W θJB (junction-to-board) 20 °C/W 23.6 °C/W 0.6 °C/W 19.4 °C/W 5.4 °C/W θJC (junction-to-case) PSI-jt (junction-to-top pseudo) 4-layer JEDEC Board (JESD51-7) using eight GND-vias Ø-0.2 on the center pad as shown in the section: Recommended pcb footprint with boundary and environment conditions of JEDEC Board (JESD51-2) PSI-jb (junction-to-board pseudo) θJP (junction-to-pad) (1) 2 See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 RECOMMENDED OPERATING CONDITIONS dR Operating data rate VCC Supply voltage VCC(N) Supply voltage noise amplitude TJ Junction temperature TA Operating free-air temperature (1) MIN NOM MAX UNIT 4 Gbps 3.135 3.3 3.465 10 Hz to 2 GHz V 20 mV 125 °C -40 85 °C dR(in) ≤ 1.25 Gbps 100 1750 mVpp 1.25 Gbps < dR(in) ≤ 3.125 Gbps 100 1560 mVpp dR(in) > 3.125 Gbps 100 1000 mVpp Note: for best jitter performance ac coupling is recommended. 1.5 |V | ID 1.6 VCC
2 V DIFFERENTIAL INPUTS Receiver peak-to-peak differential input voltage (2) VID VICM Receiver common-mode input voltage CONTROL INPUTS VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage –0.3 0.8 V 120 Ω DIFFERENTIAL OUTPUTS RL (1) (2) Differential load resistance 80 100 Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Differential input voltage VID is defined as | IN+ – IN– |. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL INPUTS VIT+ Positive going differential input high threshold VIT– Negative going differential input low threshold A(EQ) Equalizer gain RT(D) Termination resistance, differential VBB Open-circuit Input voltage (input self-bias voltage) R(BBDC) Biasing network dc impedance R(BBAC) Biasing network ac impedance 50 –50 From 375 MHz to 1.875 GHz mV 5 80 AC-coupled inputs mV 100 dB 120 Ω 1.6 V 30 kΩ 375 MHz 42 1.875 GHz 8.4 RL = 100 Ω±1%, PRES_1 = PRES_0=0; PREL_1 = PREL_0=0; 4 Gbps alternating 1010-pattern; Figure 1 650 mVpp –650 mVpp Ω DIFFERENTIAL OUTPUTS VOH High-level output voltage VOL Low-level output voltage VODB(PP) Output differential voltage without preemphasis (2) VOCM Output common mode voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states (1) (2) 1000 1300 1500 1.65 See Figure 6 1 mVpp V mV All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not production tested. Differential output voltage V(ODB) is defined as | OUT+ – OUT– |. Submit Documentation Feedback 3 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER Output preemphasis voltage ratio, V(PE) V ODB(PP) TEST CONDITIONS RL = 100 Ω ±1%; x = L or S; See Figure 1 VODPE(PP) MIN TYP (1) PREx_1:PREx_0 = 00 0 PREx_1:PREx_0 = 01 3 PREx_1:PREx_0 = 10 6 PREx_1:PREx_0 = 11 9 MAX UNIT dB t(PRE) Preemphasis duration measurement Output preemphasis is set to 9 dB during test PREx_x = 1; Measured with a 100-MHz clock signal; RL = 100 Ω, ±1%, See Figure 2 175 ps ro Output resistance Differential on-chip termination between OUT+ and OUT– 100 Ω CONTROL INPUTS IIH High-level Input current VIN = VCC IIL Low-level Input currentn VIN = GND R(PU) Pullup resistance 5 90 125 35 µA µA kΩ POWER CONSUMPTION PD ICC Device power dissipation All outputs terminated 100 Ω Device current consumption All outputs terminated 100 Ω 650 880 mW 254 mA TYP (1) MAX UNIT 3 6 ns 0.5 1 ns 0.5 1 ns PRBS 27-1 pattern at 4 Gbps SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MULTIPLEXER t(SM) Multiplexer switch time Multiplexer or loopback control to valid output DIFFERENTIAL OUTPUTS tPLH Low-to-high propagation delay tPHL High-to-low propagation delay tr Rise time tf Fall time tsk(p) Pulse skew, | tPHL– tPLH | (2) skew (3) tsk(o) Output tsk(pp) Part-to-part skew (4) RJ (1) (2) (3) (4) 4 Device random jitter, rms Propagation delay input to output See Figure 4 20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal; See Figure 3 and Figure 7 All outputs terminated with 100 Ω See Figure 7for test circuit. BERT setting 10–15 Alternating 10-pattern. 80 ps 80 25 0.8 ps 20 ps 200 ps 500 ps 2 ps-rms All typical values are at 25°C and with 3.3 V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 SWITCHING CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 0 dB preemphasis Intrinsic deterministic device (PREx_x = 0); jitter (5) (6), peak-to-peak See Figure 7 for the test circuit. DJ (5) (6) (7) MIN PRBS 27-1 pattern TYP (1) 4 Gbps 30 1.25 Gbps Over 20-inch FR4 trace 0 dB preemphasis Absolute deterministic (PREx_x = 0); output jitter (7), peak-to-peak See Figure 7 for the test circuit. PRBS 27-1 pattern MAX UNIT ps 7 4 Gbps Over FR4 trace 2-inch to 20 inches long ps 20 Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ(OUT)– DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in pspp. DJ(IN) is the peak-to-peak deterministic jitter of the pattern generator driving the device. The SN65LVCP40 built-in passive input equalizer compensates for ISI. For a 20-inch FR4 transmission line with 8-mil trace width, the LVCP40 typically reduces jitter by 60 ps from the device input to the device output. Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP40 output. The value is a real measured value with a Bit error tester as described in Figure 7. The absolute DJ reflects the sum of all deterministic jitter components accumulated over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP40)). PREL_1 1 VCC 2 SOB_0N 3 SOB_0P 4 GND LB0B LB0A SOA_0P SOA_0N VCC SIB_0P SIB_0N GND SIA_0P SIA_0N VCC MUX_S0 48 47 46 45 44 43 42 41 40 39 38 37 PIN ASSIGNMENTS PRES_0 35 VCC 34 LO_0N 33 LO_0P 5 32 GND LI_0P 6 31 LI_1N LI_0N 7 30 LI_1P VCC 8 29 VCC LO_1P 9 28 SOB_1P LO_1N 10 27 SOB_1N GND 11 26 REXT PREL_0 12 25 PRES_1 +− − + +− 36 +− +− − + + +− − +− + +− − +− 17 18 19 20 21 22 23 24 GND SIB_1N SIB_1P VCC SOA_1N SOA_1P LB1A LB1B 15 SIA_1N 16 14 VCC SIA_1P 13 MUX_S1 +− +− − + +− +− − + Submit Documentation Feedback 5 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 Table 1. Signal Descriptions SIGNAL PIN(S) TYPE SIGNAL TYPE DESCRIPTION LINE SIDE HIGH-SPEED I/O LI_0P LI_0N 6 7 I (w/ 50-Ω termination PECL/CML to VBB) compatible Differential input, port_0 line side LI_1P LI_1N 30 31 I (w/ 50-Ω termination PECL/CML to VBB) compatible Differential input, port_1 line side LO_0P LO_0N 33 34 O VML (1) Differential output, port_0 line side LO_1P LO_1N 9 10 O VML (1) Differential output, port_1 line side SWITCH SIDE HIGH-SPEED I/O SIA_0P SIA_0N 40 39 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_0 switch_A_side SIB_0P SIB_0N 43 42 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_0 switch_B_side SIA_1P SIA_1N 16 15 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_1 switch_A_side SIB_1P SIB_1N 19 18 I (w/ 50-Ω termination CML/PECL to VBB) compatible Differential input, mux_1 switch_B_side SOA_0P SOA_0N 46 45 O VML (1) Differential output, mux_0 switch_A_side SOB_0P SOB_0N 4 3 O VML (1) Differential output, mux_0 switch_B_side SOA_1P SOA_1N 22 21 O VML (1) Differential output, mux_1 switch_A_side SOB_1P SOB_1N 28 27 O VML (1) Differential output, mux_1 switch_B_side CONTROL SIGNALS PREL_0 PREL_1 12 1 I (w/ 35-kΩ pullup) LVTTL Output preemphasis control, line side port_0 and port_1. Has internal pull-up. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for function definition. PRES_0 PRES_1 36 25 I (w/ 35-kΩ pullup) LVTTL Output preemphasis control, switch side port_0 and port_1. See Preemphasis Controls PREL_0, PREL_1, PRES_0 and PRES for function definition. LB0A LB0B 47 48 I (w/ 35-kΩ pullup) LVTTL Loopback control for mux_0 switch side. See Loopback Controls LB0A, LB0B, LB1A and LB1B for function definition.n LB1A LB1B 23 24 I (w/ 35-kΩ pullup) LVTTL Loopback control for mux_1 switch side. See Loopback Controls LB0A, LB0B, LB1A and LB1B for function definition.n MUX_S0 MUX_S1 37 13 I (w/ 35-kΩ pullup) LVTTL Port A and B multiplex control of mux_0 and mux_1. See Multiplex Controls MUX_S0 and MUX_S1 for function definition. REXT 26 N/A No connect. This pin is unused and can be left open or tied to GND with any resistor. POWER SUPPLY VCC 2, 8, 14, 20, 29, 35, 38, 44 GND 5, 11, 17, PWR 32, 41 GND Center Pad (1) 6 PWR PWR Power supply 3.3 V ±5% Power supply return The ground center pad is the metal contact at the bottom of the 48-pin package. It must be connected to the GND plane. At least 4 vias are recommended to minimize inductance and provide a solid ground. See the package drawing for the via placement. VML stands for Voltage Mode logic; VML provides a differential output impedance of 100-Ω. VML offers the benefits of CML and consumes less power. Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL BLOCK DIAGRAM VBB RT EQ LO_0P + +− − +− LO_0N SIA_0P RT SIA_0N RT EQ SIB_0P RT SIB_0N MUX_S0 VBB RT LI_0P RT +− + +− − SOA_0P +− + +− − SOB_0P SOA_0N EQ LI_0N SOB_0N LB0A LB0B PREL_0 Line Side Outputs Preemphasis Control PREL_1 VBB RT EQ RT SIA_1P SIA_1N LO_1P + +− − +− LO_1N RT EQ RT SIB_1P SIB_1N MUX_S1 VBB RT LI_1P RT +− + +− − SOA_1P +− + +− − SOB_1P SOA_1N EQ LI_1N SOB_1N LB1A LB1B PRES_0 Switch Side Outputs Preemphasis Control PRES_1 30 K 1.6 V VBB Note: VBB: Receiver input internal biasing voltage (allows ac coupling) EQ: Input Equalizer (compensates for frequency dependent transmission line loss of backplanes) RT: Internal 50−Ohm receiver termination (100−Ohm differential) Preemphasis: Output precompensation for transmission line losses Submit Documentation Feedback 7 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL DEFINITIONS Table 2. Multiplex Controls MUX_S0 and MUX_S1 (1) MUX_Sn (1) MUX FUNCTION 0 MUX_n select input B 1 MUX_n select input A n = 0 or 1 Table 3. Loopback Controls LB0A, LB0B, LB1A and LB1B (1) LBnx (1) LOOPBACK FUNCTION 0 Enable loopback of SIx input to SOx output 1 Disable loopback of SIx input to SOx output n = 0 or 1, x = A or B Table 4. Multiplexer and Loopback Controls INPUTS / OUTPUTS SOA_0 SOB_0 SOA_1 SOB_1 LO_0 LO_1 SIA_0 LB0A = 0 x x x MUX_S0 = 1 x SIB_0 x LB0B = 0 x x MUX_S0 = 0 x SIA_1 x x LB1A = 0 x x MUX_S1 = 1 SIB_1 x x x LB1B =0 x MUX_S1 = 0 LI_0 LB0A = 1 LB0B = 1 x x x x LI_1 x x LB1A = 1 LB1B = 1 x x Table 5. Preemphasis Controls PREL_0, PREL_1, PRES_0, and PRES_1 PREx_1 (1) PREx_0 (1) OUTPUT PREEMPHASIS LEVEL IN dB DEEMPHASIZED PREEMPHASIZED TYPICAL FR4 TRACE LENGTH 0 0 0 dB 1200 1200 10 inches of FR4 trace 0 1 3 dB 850 1200 20 inches of FR4 trace 1 0 6 dB 600 1200 30 inches of FR4 trace 1 1 9 dB 425 1200 40 inches of FR4 trace (1) OUTPUT LEVEL IN mVpp x = L or S Preemphasis is the primary signal conditioning mechanism. See Figure 1 and Figure 2 for further definition. Equalization is secondary signal conditioning mechanism. The input stage provides 5-dB of fixed equalization gain from 375 MHz to 1.875 GHz (optimized for 3.75-Gbps 8B10B coded data). 8 Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 3−dB Preemphasis VOCM VODB(PP) VODPE2(pp) 9−dB Preemphasis VODPE3(pp) 6−dB Preemphasis VODPE1(pp) 0−dB Preemphasis VOH VOL Figure 1. Preemphasis and Output Voltage Waveforms and Definitions 9−dB Preemphasis 1 to N bit VODPE3(pp) 1−bit VODB(PP) 80% 20% tPRE Figure 2. t(PRE) Preemphasis Duration Measurement Submit Documentation Feedback 9 SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 PARAMETER MEASUREMENT INFORMATION (continued) 80% 80% VODB 20% 20% tr tf Figure 3. Driver Output Transition Time VID = 0 V IN t PHLD t PLHD VOD = 0 V OUT Figure 4. Propagation Delay Input to Output CIRCUIT DIAGRAMS VCC OUT+ 49.9
OUT− 49.9
VOCM IN+ RT(SE) = 50
1 pF Gain Stage + EQ VCC RBBDC RT(SE) = 50
Figure 6. Common-Mode Output Voltage Test Circuit IN− VBB ESD LineEndTermination Self−Biasing Network Figure 5. Equivalent Input Circuit Design 10 Submit Documentation Feedback SN65LVCP40 www.ti.com SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 JITTER TEST CIRCUIT Pattern Generator DC Block D+ Pre-amp Coax SMA 20−inch FR4 DC Block D− Coax 400 mVPP Differential SMA RX + EQ M U X