SN65LVDM31DR

SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 HIGH-SPEED DIFFERENTIAL LINE DRIVER FEATURES • SN65LVDM31D (Marked as LVDM31) (TOP VIEW) Designed for Signaling Rates NOTE: The signaling rate is the number of voltage transitions that can be made per second. • • • • • • • 1A 1Y 1Z G 2Z 2Y 2A GND Up to 150 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 700 mV and a 100-Ω Load Propagation Delay Time of 2.3 ns, Typical Single 3.3-V Supply Operation One Driver's Power Dissipation at 75 MHz, 50 mW, Typical High-Impedance Outputs When Disabled or With VCC < 1.5 V Bus-Pin ESD Protection Exceeds 12 kV Low-Voltage CMOS (LVCMOS) Logic Input Levels Are 5-V Tolerant 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4A 4Y 4Z G 3Z 3Y 3A FUNCTIONAL BLOCK DIAGRAM G G 1A 4 12 2 1 3 DESCRIPTION 6 The SN65LVDM31 incorporates four differential line drivers that implement the electrical characteristics of low-voltage differential signaling. This product offers a low-power alternative to 5-V PECL drivers with similar signal levels. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 540 mV into a 100-Ω load when enabled by either an active-low or active-high enable input. The intended application of this device and signaling technique is for both point-to-point and multiplexed baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDM31 is characterized for operation from –40°C to 85°C. 2A 3A 4A 7 5 10 9 11 1Y 1Z 2Y 2Z 3Y 3Z 14 4Y 13 4Z 15 FUNCTION TABLE INPUT ENABLES OUTPUTS A G G Y Z H H X H L L H X L H H X L H L H L X L L X L H Z Z Open H X L H Open X L L H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2001, Texas Instruments Incorporated SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC G, G or A Input 50 Ω 50 Ω 10 kΩ 7V 300 kΩ Y or Z Output 7V ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range VCC (2) –0.5 V to 4 V Inputs –0.5 V to 6 V Input voltage range Y or Z –0.5 V to 4 V Electrostatic discharge (3): Y, Z, and GND Class 3, A:12 kV, B:600 V Continuous power dissipation See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING D 950 mW 7.6 mW/°C 494 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature 2 MIN NOM MAX 3 3.3 3.6 2.0 40 Submit Documentation Feedback UNIT V V 0.8 V 85 °C SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage MIN TYP (1) 540 700 860 RL = 50 Ω, See Figure 2 270 350 430 –25 0 25 mV 1.14 1.2 1.3 V –30 0 30 70 100 6 10 See Figure 2 See Figure 3 Enabled, RL = 100 Ω Supply current UNIT See Figure 2 Enabled, No load ICC MAX RL = 100 Ω, VIN = 0 or VCC Disabled 35 40 0.5 0.7 mV mV mA IIH High-level input current VIH = 3 V –10 3 10 µA IIL Low-level input current VIL = 0 V –10 µA 0 10 VOY or VOZ = 0 V 7 10 VOD = 0 V 7 10 IOS Short-circuit output current IOZ High-impedance state output current VO = 0 V or VCC IO(OFF) Power-off output current VCC = 1.5 V, (1) VO = 3.6 V mA ±1 µA ±1 µA All typical values are at 25°C and with a 3.3-V supply. SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN TYP MAX tPLH Propagation delay time, low-to-high-level output PARAMETER TEST CONDITIONS 1.8 2.3 2.9 ns tPHL Propagation delay time, high-to-low-level output 1.8 2.3 2.9 ns tr Differential output signal rise time 0.4 0.6 1.0 ns tf Differential output signal fall time 0.4 0.6 1.0 ns tsk(p) Pulse skew (|tPHL– tPLH|) 50 350 ps 200 ps 1 ns 6 15 ns See Figure 4 skew (1) UNIT tsk(o) Channel-to-channel output tsk(pp) Part-to-part skew tPZH Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low level output 6 15 ns tPHz Propagation delay time, high-level-to-high-impedance output 6 15 ns tPLZ Propagation delay time, low-level-to-high-impedance output 6 15 ns (1) (2) (2) See Figure 5 tsk(o) is the maximum delay time difference between drivers on the same device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback 3 SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION Y II IOY A IOZ VOD VOY Z VI VOC (VOY+VOZ)/2 VOZ Figure 1. Driver Voltage and Current Definitions 3.75 kΩ Y RL VOD Input Z + _ 0 V ≤ Vtest ≤ 2.4 V 3.75 kΩ Figure 2. VOD Test Circuit Y Input 49.9 Ω ± 1%(2 Places) 3V A A 0V Z VOC(PP) VOC CL = 10 pF (2 Places) VOC(SS) VOC NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the DUT. The measurement of VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 3V 1.5 V Input Y 0V VOD Input 100 Ω tPLH tPHL Z CL = 10 pF (2 Places) 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the DUT. Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal 4 Submit Documentation Feedback SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION (continued) 49.9 Ω ± 1%(2 Places) Y 0 V or 3 V G Inputs G Z VOY G 3V 1.5 V 0V G 3V 1.5 V 0V VOY or VOZ tPZH 1.2 V ≤ 1.4 V 1.25 V 1.2 V A at 3 V, G at VCC and Input to G or G at GND and Input to G 1.2 V 1.15 V ≤1V A at 0 V, G at VCC and Input to G or G at GND and Input to G tPHZ VOZ or VOY tPZL VOZ CL = 10 pF (2 Places) tPLZ NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the DUT. Figure 5. Enable and Disable Time Circuit and Definitions Submit Documentation Feedback 5 SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY 70 60 I CC − Supply Current − mA VCC = 3.6 V 50 VCC = 3 V 40 VCC = 3.3 V 30 20 10 0 0 50 100 150 200 250 300 f − Frequency − MHz Figure 6. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 VCC = 3.3 V TA = 25°C, Single-Ended No Load 3 V OH− High-Level Output Voltage − V V OL − Low-Level Output Voltage − V 4 2 1 0 3 2.5 2 1.5 1 VCC = 3.3 V TA = 25°C, Single-Ended No Load .5 0 0 2 4 6 8 10 12 0 IOL − Low-Level Output Current − mA Figure 7. 6 −2 −4 Figure 8. Submit Documentation Feedback −6 IOH − High-Level Output Current − mA −8 SN65LVDM31 www.ti.com SLLS417C – MARCH 2000 – REVISED MAY 2001 TYPICAL CHARACTERISTICS (continued) LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.75 2.5 t PLH − High-To-Low Propagation Delay Time − ns t PLH − Low-To-High Propagation Delay Time − ns 2.75 VCC = 3 V VCC = 3.3 V 2.25 VCC = 3.6 V 2 1.75 −50 −30 −10 50 30 70 TA − Free-Air Temperature − °C 10 90 VCC = 3 V 2.5 VCC = 3.3 V 2.25 VCC = 3.6 V 2 1.75 −50 Figure 9. −30 −10 50 30 70 TA − Free-Air Temperature − °C 10 90 Figure 10. Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDM31D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM31 SN65LVDM31DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM31 SN65LVDM31DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM31 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of