SN65LVDS150
www.ti.com
SLLS443 – DECEMBER 2000
MuxIt™ PLL FREQUENCY MULTIPLIER
FEATURES
•
•
•
•
•
•
•
•
•
•
A Member of the MuxIt™ SerializerDeserializer Building-Block Chip Family
Pin Selectable Frequency Multiplier Ratios
Between 4 and 40
Input Clock Frequencies From 5 to 50 MHz
Multiplied Clock Frequencies up to
400 MHz
Internal Loop Filters and Low PLL-Jitter of
20 ps RMS Typical at 200 MHz
LVDS Compatible Differential Inputs and
Outputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644-A
LVTTL Compatible Inputs Are 5 V Tolerant
LVDS Inputs and Outputs ESD Protection
Exceeds 12 kV HBM
Operates From a Single 3.3 V Supply
Packaged in 28-Pin Thin Shrink Small-Outline
Package With 26 mil Terminal Pitch
SN65LVDS150
PW PACKAGE
(Marked as 65LVDS150)
VCC
CRI+
CRI–
VT
GND
M1
M2
M3
M4
M5
BSEL
GND
LCRO–
LCRO+
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
NC
NC
NC
VCC
GND
NC
GND
NC
MCO+
MCO–
GND
EN
LCRO_EN
LVO
NC – No internal connection
DESCRIPTION
The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers
and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of
differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or
LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for
higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS
(TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data
destination.
The MuxIt family initially includes three devices supporting simplex communications; The SN65LVDS150 Phase
Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter, and The SN65LVDS152
Receiver-Deserializer.
The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt
family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of
values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are
needed. A PLL lock indicator output is available which may be used to enable link data transfers.
The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt
serial link. The differential clock reference input (CRI) is driven by the system's parallel data clock when at the
source end of the link, or by the link clock when at the destination end of the link. The differential clock reference
input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For
single-ended use the nonclocked input is biased to the logic threshold voltage. A VCC/2 threshold reference, VT,
is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended
mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MuxIt is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
SN65LVDS150
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SLLS443 – DECEMBER 2000
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in
either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock
reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for
transmission over the link.
An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When VCC is
below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential
outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential
outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN) is
used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize the
VCO performance as a function of M-clock frequencies and M multiplier that is being used: The fmax parameter in
the switching characteristic table includes details on the MCO frequency and choices of BSEL and M.
BLOCK DIAGRAM
CRI+
Frequency
Phase
Detector
CRI–
VCO
LVO
MCO+
MCO–
BSEL
Ref.
Gen.
VT
Divide by M
M1 M2 M3 M4 M5
EN
LCRO+
LCRO–
LCRO_EN
2
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SLLS443 – DECEMBER 2000
Frequency Multiplier Value Table
(1)
(1)
RECOMMENDED fIN
(MHz)
MULTIPLIER
(m)
M1
M2
M3
M4
M5
4
L
L
L
L
L
Reserved
L
L
L
L
H
NA
NA
6
L
L
L
H
L
fIN < 8.33
8.33 ≤ fIN
Reserved
L
L
L
H
H
NA
NA
8
L
L
H
L
L
fIN < 12.50
12.50 ≤ fIN
9
L
L
H
L
H
fIN < 11.11
11.11 ≤ fIN
10
L
L
H
H
L
fIN < 10.00
10.00 ≤ fIN
Reserved
L
L
H
H
H
NA
NA
12
L
H
L
L
L
fIN < 8.3
8.3 ≤ fIN
13
L
H
L
L
H
fIN < 7.7
7.7 ≤ fIN
14
L
H
L
H
L
fIN < 7.14
7.14 ≤ fIN
15
L
H
L
H
H
fIN < 6.67
6.67 ≤ fIN
16
L
H
H
L
L
fIN < 6.25
6.25 ≤ fIN
17
L
H
H
L
H
fIN < 5.88
5.88 ≤ fIN
18
L
H
H
H
L
fIN < 5.56
5.56 ≤ fIN
19
L
H
H
H
H
fIN < 5.26
5.26 ≤ fIN
20
H
L
L
L
L
fIN = 5.00
5.00 ≤ fIN
22
H
L
L
L
H
NA
5.00 ≤ fIN
24
H
L
L
H
L
NA
5.00 ≤ fIN
26
H
L
L
H
H
NA
5.00 ≤ fIN
28
H
L
H
L
L
NA
5.00 ≤ fIN
30
H
L
H
L
H
NA
5.00 ≤ fIN
32
H
L
H
H
L
NA
5.00 ≤ fIN
34
H
L
H
H
H
NA
5.00 ≤ fIN
36
H
H
L
L
L
NA
5.00 ≤ fIN
38
H
H
L
L
H
NA
5.00 ≤ fIN
40
H
H
L
H
L
NA
5.00 ≤ fIN
Reserved
H
H
L
H
H
NA
NA
Reserved
H
H
H
L
L
NA
NA
Reserved
H
H
H
L
H
NA
NA
Reserved
H
H
H
H
L
NA
NA
Reserved
H
H
H
H
H
NA
NA
BSEL = 0
BSEL = 1
fIN < 12.50
12.50 ≤ fIN
H = high level, L= low level
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SN65LVDS150
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SLLS443 – DECEMBER 2000
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
300 kΩ
300 kΩ
50 Ω
10 kΩ
CRI+
Input
CRI–
Input
4V
MCO+, MCO–,
LCRO+, LCRO–
Output
4V
4V
VCC
BSEL,
LCRO_EN
Only
M1–M5,
LCRO_EN,
BSEL, or
EN Input
VCC
300 kΩ
50 Ω
400 Ω
LVO Output
5V
6V
300 kΩ
Mn, EN, Only
4
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SLLS443 – DECEMBER 2000
Terminal Functions
TERMINAL
NAME
NO.
I/O
TYPE
DESCRIPTION
BSEL
11
I
LVTTL
Band select. Used to optimize VCO performance for minimum M-clock jitter: See
recommended fmax in the frequency multiplier value table.
CRI+, CRI–
2, 3
I
LVDS
Clock reference input. This is the reference clock signal for the PLL frequency multiplier.
EN
17
I
LVTTL
Enable input. Used to disable the device to a low power state. A high level input enables the
device, a low level input disables the device.
5, 12, 18,
22, 24
I
NA
13, 14
O
LVDS
Link clock reference output. This is the data block synchronization clock signal from the PLL
frequency multiplier.
LCRO_EN
16
I
LVTTL
LCRO enable. Used to turn off the LCRO outputs when they are not used. A high level input
enables the LCRO output; a low level input disables the LCRO output.
LVO
15
O
LVTTL
Lock/valid output. This is signal required for proper Muxlt system operation. It is to be directly
connected to the LVI inputs of SN65LVDS151 or SN65LVDS152 devices. It is used to inhibit
the operation of those devices until after the PLL has stabilized. It remains at a low level
following a reset until the PLL has become phase locked. A low to high-level transition
indicates phase lock has occurred.
GND
LCRO–,
LCRO+
Circuit ground
M1–M5
6–10
I
LVTTL
Multiplier value selection inputs. These inputs determine the frequency multiplication ratio M.
MCO–, MCO+
19, 20
O
LVDS
M-clock output. This is the high frequency multiplied clock output from the PLL frequency
multiplier. It is used by the companion serializer or deserializer devices to synchronizes the
transmission or reception of data
NC
21, 23,
26–28
NA
These pins are not connected and may be left open.
VCC
1, 25
NA
Supply voltage
4
NA
Voltage reference. A VCC/2 reference supplied for the unused CRI input when operated in a
single-ended mode.
VT
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage
range (2)
Voltage range
–0.5 V to 4 V
EN, BSEL, LCRO_EN, or M1-M5 inputs
–0.5 V to 6 V
CRI input
–0.5 V to 4 V
LCRO±, MCO± outputs
Human body model (CRI±, LCRO±, MCO±,and
Electrostatic discharge
–0.5 V to 4 V
GND (3)
All pins
±2 kV
Charged-device model (all pins) (4)
Continuous total power dissipation
Tstg
(2)
(3)
(4)
±500 V
See Dissipation Rating Table
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
±12 kV
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
Tested in accordance with JEDEC Standard 22, Test method A114-B.
Tested in accordance with JEDEC Standard 22, Test method C101.
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SN65LVDS150
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DISSIPATION RATING TABLE
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PW
1207 mW
9.6 mW/°C
628 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
3.3
3.6
VCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
|VID|
Magnitude of differential input voltage
CRI
VIC
Common-mode input voltage
CRI
TA
Operating free-air temperature
EN, BSEL, LCRO_EN, M1–M5
UNIT
V
V
0.1
|V
|
ID
2
0.8
V
0.6
V
|V
2.4
|
ID
2
V
VCC– 0.8
40
85
°C
TIMING REQUIREMENTS
MIN
tc(1)
Input clock cycle time
tw(1)
High-level input clock pulse width duration
f(clock)
Input clock frequency, CRI
6
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MAX
UNIT
20
TYP
200
ns
0.4 tc(1)
0.6 tc(1)
5
50
MHz
SN65LVDS150
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SLLS443 – DECEMBER 2000
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIT+
Positive-going differential input threshold voltage
VIT–
Negative-going differential input threshold voltage
|VOD(SS)|
Steady-state differential output voltage magnitude
RL = 100 Ω, See Figure 3
247
∆|VOD(SS)|
Change in steady-state differential output voltage
magnitude between logic states
VID = ±100 mV,
See Figure 2 and Figure 3
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
Peak-to-peak change common-mode output voltage
VOH
See Figure 1 and Table 1
TYP (1)
MAX
UNIT
100
mV
–100
mV
454
mV
-50
50
mV
1.125
1.375
See Figure 4
–50
50
mV
150
mV
High-level output voltage (LVO)
IOH = –8 mA
2.4
VOL
Low-level output voltage (LVO)
IOL = 8 mA
V(T)
Threshold reference bias voltage
–100 µA ≤ IO≤ 100 µA
ICC
Supply current
II
Input current (CRI inputs)
I(ID)
Differential input current (IIA - IIB) (CRI inputs)
VIC = 0.05 V or 2.35 V,VID = ±0.1 V
II(OFF)
Power-off input current (CRI inputs)
VCC = 0 V, VI = 3.6 V
M1-M5, EN
IIH
High-level input current
IIL
Low-level input current
IOS
Short-circuit output current
MCO, LCRO
IOZ
High-impedance output
current
MCO, LCRO
IO(OFF)
CI
(1)
BSEL, LCRO_EN
M1-M5, EN
BSEL, LCRO_EN
340
50
V
0.4
V
V
CC 0.15
2
CC 0.15
2
Enabled, RL = 100 Ω, CRI ± open
25
70
Disabled
2.5
6
VI = 0
–20
VI = 2.4 V
–1.2
VIH = 2 V
VIL = 0.8 V
V
–2
–2
V
V
mA
µA
2
µA
20
µA
20
-10
10
–20
µA
µA
VO+ or = VO– = 0 V
–10
10
VOD = 0 V
-10
10
VO = 0 V or VCC
-5
5
µA
Power-off output current
VCC = 1.5 V , VO = 3.6 V
-5
5
µA
Input capacitance (CRI inputs)
VID = [(0.4sin(4E6πt) = 0.5] V
3
mA
pF
All typical values are at TA = 25°C and with VCC = 3.3 V.
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SN65LVDS150
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MCO output clock period jitter (2)
TEST CONDITIONS
p-p
Lock (stabilization time) (3)
tw(2)
Multiplied clock output pulse width
tr
Differential output signal rise time (MCO, LCRO)
tf
Differential output signal fall time (MCO, LCRO)
t(OS)
CRI↑ to MCO↑ offset time
fI = 5 MHz, M = 4
fI = 10 MHz, M = 10
RL = 100 Ω, CL = 10 pF,
See Figure 5
RL = 100 Ω, CL = 10 pF,
See Figure 6
fI = 5 MHz, M = 40
MCO↑ before LCRO↑ , time
delay
fI = 5 MHz, M = 4
fI = 10 MHz, M = 10
RL = 100 Ω, CL = 10 pF,
See Figure 6
fI = 5 MHz, M = 40
fmax
(1)
(2)
(3)
8
Maximum MCO output frequency
MAX
200
EN = 1, BSEL = 1,
LCRO_EN = 1, M = 40,
fI = 5 MHz
rms
t(lock)
td
MIN TYP (1)
ps
20
0.2
0.4tc(2)
1
0.6
1.5
0.3
0.6
1.5
–2.5
0
2.5
–1.5
0
1.5
–1.65
0
1.65
0.5
2.5
6
0.5
2.5
6
0.5
2.5
4.5
200
BSEL =1, M ≠ 4, 6
400
BSEL =0, M = 4, 6
50
BSEL =0, M ≠ 4, 6
100
ms
0.6tc(2)
0.3
BSEL =1, M = 4, 6
UNIT
ns
ns
ns
MHz
All typical values are at TA = 25°C and with VCC = 3.3 V.
Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 10,000 cycles with a source
having less than 10 psec jitter rms.
Lock time is measured from the application of the clock reference input signal to the assertion of a high-level lock/valid output.
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PARAMETER MEASUREMENT INFORMATION
+
VID
–
VI+
(VI+ + VI–)/2
VIC
VI–
Figure 1. Receiver Input Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
APPLIED VOLTAGES
RESULTING COMMONMODE INPUT VOLTAGE
V(IA)
V(IB)
VID
VIC
1.25 V
1.15 V
100 mV
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
IO+
+
IO–
VOD
VO+
–
VOC
VO–
(VO++VO–)/2
Figure 2. Driver Output Voltage and Current Definitions
3.75 kΩ
+
VOD
100 Ω
+
_
0 V ≤ Vtest ≤ 2.4 V
–
3.75 kΩ
Figure 3. VOD Test Circuit
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49.9 Ω ±1% (2 PLCS)
VOC(PP)
+
VOC(SS)
VOC
–
A.
50 pF
VOC
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, Pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 5 GHz.
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
+
Output
VOD
100 Ω ±1%
100%
80%
VOD(H)
0V
–
VOD(L)
CL = 10 pF
(2 PLCS)
20%
0%
tf
A.
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, Pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of
the D.U.T.
Figure 5. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
CRI
0V
t(OS)
0V
MCO
td
LCRO
0V
Figure 6. Output Timing Waveform Definitions
10
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
MCO FREQUENCY
JITTER
vs
MCO FREQUENCY
80
400
M = 20
70
350
M=4
60
M=4
MCO Jitter − psp−p
I CC − Supply Current − mA
M = 10
50
40
M = 40
30
300
250
200
100
10
50
50
100
150
200
250
300
350
400
M = 20
150
20
0
0
M = 10
0
0
MCO Frequency − MHz
Figure 7.
M = 40
50
100 150 200 250 300
MCO Frequency − MHz
350
400
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
BASIC APPLICATIONS EXAMPLES
Parallel data path width between 4 and 10 bits, only one LVDS data link required.
Data and Clock Input
GND
–
+
+
DI0–DI9
CI
LCRI
EN
SN65LVDS151
MuxIt
Serializer-Transmitter
LCO
DO EN EN LCO
–
+
–
LCRO
M5 M4 M3 M2 M1 VT
CI
LVO
LCRO
EN EN
MCO
–
+
–
+
CRI
SN65LVDS150
MuxIt PLL
Frequency Multiplier
MCI LVI
+
–
–
+
BSEL
+
–
VCC
VCC
LVDS Serial Link,
1 Data + Clock
GND
+
CO
–
–
EN CO
EN
+
–
LCI
–
+
+
DI
LCRO
LVI
SN65LVDS150
MuxIt PLL
Frequency Multiplier
LCRO
LVO EN EN MCO BSEL
SN65LVDS152
MuxIt
Receiver-Deserializer
DO0–DO9
DCO
MCI
+
M5 M4 M3 M2 M1 VT
–
–
GND
Data and Clock Output
(a)
12
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+
–
+
CRI
SN65LVDS150
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SLLS443 – DECEMBER 2000
TYPICAL CHARACTERISTICS (continued)
Parallel data path width between 11 and 20 bits, aggregate data rate low enough to allow transmission over one
LVDS data link, sharing of PLL-FM between serializer-transmitter and receiver-deserializer chips at each end.
Data and Clock Input
VCC
GND
–
+
–
LCRI
CI
EN
SN65LVDS151
MuxIt
Serializer-Transmitter
LCO
EN EN LCO
–
+
–
MCI
+
+
DI0–DI9
ST–A
LVI
–
+
LCRI
CI
EN
SN65LVDS151
MuxIt
Serializer-Transmitter
DI0–DI9
DO
+
CI
+
LCO
EN EN LCO
DO
–
–
+
VCC
–
MCI
+
+
LCRO
CI
+
M5 M4 M3 M2 M1 VT
+
CRI
SN65LVDS150
MuxIt PLL
Frequency Multiplier
ST–B
LVI
–
–
–
LVO
LCRO
EN EN
MCO
–
–
GND
BSEL
+
VCC
LVDS Serial Link,
1 Data + Clock
GND
+
VCC
–
–
CO
EN CO
EN
+
–
LCI
DI
SN65LVDS152
MuxIt
Receiver-Deserializer
DO0–DO9
DCO
+
RD–A
MCI
+
LVI
+
CO
–
–
EN CO
EN
+
–
LCI
DI
SN65LVDS152
MuxIt
Receiver-Deserializer
DO0–DO9
DCO
RD–B
MCI
+
–
+
LVI
–
+
+
–
LCRO
M5 M4 M3 M2 M1 VT
CRI
SN65LVDS150
MuxIt PLL
Frequency Multiplier
LCRO
LVO EN EN MCO
BSEL
–
+
–
GND
Data and Clock Output
(b)
Submit Documentation Feedback
13
SN65LVDS150
www.ti.com
SLLS443 – DECEMBER 2000
TYPICAL CHARACTERISTICS (continued)
Parallel data path width between 11 and 20 bits, aggregate data rate requires transmission over two separate
LVDS data links, sharing of PLL-FM between serializer-transceiver and receiver-deserializer chips at each end.
Data and Clock Input
GND
GND
–
+
–
DI0–DI9
CI
LCRI
EN
SN65LVDS151
ST–A
MuxIt
Serializer-Transmitter
LCO
EN EN LCO
DO
–
+
–
MCI LVI
+
+
–
CI
LCRI
EN
SN65LVDS151
ST–B
MuxIt
Serializer-Transmitter
LCO
EN EN LCO
DO
–
+
DI0–DI9
CI
+
+
–
+
GND
–
MCI LVI
+
+
–
LCRO
M5 M4 M3 M2 M1 VT
+
CRI
SN65LVDS150
MuxIt PLL
Frequency Multiplier
LCRO
LVO EN EN
CI
+
–
–
MCO
–
–
VCC
BSEL
+
VCC
LVDS Serial Link,
2 Data + Clock
GND
+
–
CO
GND
–
EN CO
EN
+
–
LCI
DI
SN65LVDS152
MuxIt
Receiver-Deserializer
DO0–DO9
DCO
+
RD–A
MCI
+
LVI
+
–
–
CO
EN CO
EN
+
–
LCI
+
DI
SN65LVDS152
RD–B
MuxIt
Receiver-Deserializer
DO0–DO9
DCO
MCI
+
–
LVI
+
–
–
LCRO
M5 M4 M3 M2 M1 VT
SN65LVDS150
MuxIt PLL
Frequency Multiplier
LCRO
LVO EN EN MCO BSEL
–
–
GND
Data and Clock Output
14
(c)
Submit Documentation Feedback
+
+
CRI
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65LVDS150PW
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65LVDS150
SN65LVDS150PWG4
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65LVDS150
SN65LVDS150PWR
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65LVDS150
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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