SN65LVDS22PWR

SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 DUAL MULTIPLEXED LVDS REPEATERS FEATURES • • • • • • • • • • • • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Designed for Clock Rates up to 200 MHz (400 Mbps) Designed for Data Rates up to 250 Mbps Pin Compatible With SN65LVDS122 and SN65LVDT122, 1.5 Gbps 2x2 Crosspoint Switch From TI ESD Protection Exceeds 12 kV on Bus Pins Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Output Voltages of 350 mV Into: – 100-Ω Load (SN65LVDS22) – 50-Ω Load (SN65LVDM22) Propagation Delay Time; 4 ns Typ Power Dissipation at 400 Mbps of 150 mW Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V LVTTL Levels Are 5 V Tolerant Open-Circuit Fail Safe Receiver DESCRIPTION The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100-Ω load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver. The SN65LVDM22 doubles the output drive current to achieve LVDS levels with a 50-Ω load. SN65LVDS22D and SN65LVDS22PW (Marked as LVDS22) SN65LVDM22D and SN65LVDM22PW (Marked as LVDM22) (TOP VIEW) 1B 1A S0 1DE S1 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC VCC 1Y 1Z 2DE 2Z 2Y GND logic diagram (positive logic) 1A 1B 2 + _ 1 14 0 13 1 1DE 2DE S0 S1 2B 1Z 4 12 3 5 10 0 2A 1Y 6 11 + _ 7 1 2Y 2Z MUX TRUTH TABLE INPUT OUTPUT FUNCTION S1 S0 1Y/1Z 2Y/2Z 0 0 1A/1B 1A/1B Splitter 0 1 2A/2B 2A/2B Splitter 1 0 1A/1B 2A/2B Router 1 1 2A/2B 1A/1B Router Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2002, Texas Instruments Incorporated SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics). The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C. 2 Submit Documentation Feedback SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 300 kΩ 50 Ω S0, S1 Input 50 Ω 1DE, 2DE Input 7V 300 kΩ 7V VCC 300 kΩ VCC 300 kΩ 5Ω 10 kΩ A Input B Input 7V 7V Y or Z Output 7V ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (see Note Voltage range Electrostatic discharge (2)) –0.5 V to 4 V (DE, S0, S1) –0.5 V to 6 V (Y, Z, A, and B) –0.5 V to 4 V A, B, Y, Z and GND (see Note (3)) All pins Class 3, A:5 kV, B:500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) Class 3, A:12 kV, B:600 V 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. Submit Documentation Feedback 3 SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING D 1110 mW 8.9 mW/°C 577 mW PW 839 mW 6.7 mW/°C 437 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH High-level input voltage S0, S1, 1DE, 2DE VIL Low-level input voltage S0, S1, 1DE, 2DE |VID| Magnitude of differential input voltage VIC Common-mode input voltage (see Figure 1) TA Operating free-air temperature MIN NOM MAX 3 3.3 3.6 2 UNIT V V 0.1
V
ID 2 2.4– 0.8 V 0.6 V
V
V ID 2 VCC–0.8 V 85 °C 40 TIMING REQUIREMENTS PARAMETER tsu Input to select setup time th Input to select hold time tswitch Select to switch output MIN NOM MAX UNIT 1.6 ns See Figure 6 1 3.2 COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE VIC – Common-Mode Input Voltage – V 2.5 MAX at VCC > 3.15 V MAX at VCC = 3 V 2 1.5 1 0.5 Min 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VID – Differential Input Voltage – V Figure 1. Common-Mode Input Voltage vs Differential Input Voltage 4 Submit Documentation Feedback ns 5 ns SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold VIT– Negative-going differential input voltage threshold II Input current (A or B inputs) II(OFF Power-off input current (A or B inputs) MIN TYP MAX UNIT 100 mV 100 VI = 0 V mV 2 VI = 2.4 V 20 1.2 VCC = 0 V ) 20 µA µA RECEIVER/DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOD Differential output voltage magnitude ∆VOD Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage 247 See Figure 2 RL = 100 Ω ('LVDS22), RL = 50 Ω ('LVDM22) See Figure 3 No Load ICC Supply current High-level input current IIL Low-level input current DE mV –50 50 mV 1.125 1.37 5 3 DE RL = 50 Ω ('LVDM22) 21 27 20 –10 10 IO(OFF) Power-off output current –10 –10 CIN Input capacitance (1) 0.015 ±1 VO = 0 V or VCC 0.015 ±1 0.015 ±1 VO = 3.6 V µA mA –10 VOD = 600 mV VCC = 0 V, µA –10 VOY or VOZ = 0 V, VOD = 0 V ('LVDM22) High-impedance output current mA 6 –10 Short-circuit output current IOZ mV 20 VOY or VOZ = 0 V, VOD = 0 V ('LVDS22) IOS 150 13 VIL = 0.8 V S0, S1 mV RL = 100 Ω ('LVDS22) 3 V 50 12 VIH = 5 V S0, S1 UNIT 454 –50 340 8 Disabled IIH MIN TYP (1) MAX 3 µA µA pF All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback 5 SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 DIFFERENTIAL RECEIVER TO DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Differential propagation delay time, low-to-high 4 6 ns tPHL Differential propagation delay time, high-to-low 4 6 ns tsk(p) Pulse skew (|tPHL - tPLH|) tr Transition time, low-to-high SN65LVDS22 tr Transition time, low-to-high SN65LVDM22 tf Transition time, high-to-low tf Transition time, high-to-low tPHZ Propagation delay time, high-level-to-high-impedance output tPLZ Propagation delay time, low-level-to-high-impedance output tPZH Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low-level output 0.2 CL = 10 pF, See Figure 4 1.5 ns 0.8 1.3 ns SN65LVDS22 1 1.5 ns SN65LVDM22 0.8 1.3 ns 4 10 ns 5 10 ns 5 10 ns 6 10 ns See Figure 5 tPHL_R1_Dx tPLH_R1_Dx tPHL_R2_Dx 0.2 0.2 Channel-to-channel skew, receiver to driver (2) 0.2 tPLH_R2_Dx fmax (1) (2) ns 1 0.2 Maximum operating frequency All channels switching 200 All typical values are at 25°C and with a 3.3-V supply. These parametric values are measured over supply voltage and temperature ranges recommended for the device. PARAMETER MEASUREMENT INFORMATION DE Y A Pulse Generator B VI(B) 1.4 V VI(A) 1V VOD Z Input (see Note A) RL (see Note B) CL = 10 pF (2 Places) (see Note C) 100% 80% VOD 0 20% 0% tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. B. RL = 100 Ω or 50 Ω ±1% C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 2. Test Circuit and Voltage Definitions for the Differential Output Signal 6 ns Submit Documentation Feedback MHz SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION (continued) DE A Y B Z Pulse Generator RL (see Note B) (2 Places) VI(B) 1.4 V VI(A) 1V VOC(PP) Input (see Note A) VOC CL = 10 pF (2 Places) (see Note C) (see Note D) VOC(SS) VCC A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. B. RL = 100 Ω or 50 Ω ±1% C. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. D. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage DE Y A Pulse Generator R D RL (see Note A) B Z 10 pF 10 pF VIB 1.4 V 0-V Differential 1.2-V CM VIA 1V tPLH tPHL VOZ 1.4 V 0-V Differential 1.2-V CM VOY 1V 80% 0-V Differential 20% VOY – VOZ tr tf A. RL = 100 Ω or 50 Ω ±1% B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time Waveforms Submit Documentation Feedback 7 SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION (continued) DE 1 V or 1.4 V R 1.2 V RL/2 (see Note A) A 1.2 V D B RL/2 (see Note A) 2V DE 1.4 V 0.8 V tPZH tPHZ ≈1.4 V VOY or VOZ 1.25 V 1.2 V tPZL tPLZ 1.2 V 1.15 V VOY or VOZ ≈1 V A. RL = 100 Ω or 50 Ω ±1% B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. Figure 5. Enable and Disable Timing Circuit 8 Submit Documentation Feedback SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION (continued) 1A/B 2A/B tsu th S0/1 Outputs Out 1 or 2 Out 1 or 2 tsu DE NOTE: tsu and th times specify that data must be in a stable state before and after MUX control switches. Figure 6. Input-to-Select for Both Rising and Falling Edge Setup and Hold Times Submit Documentation Feedback 9 SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS SN65LVDS22 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C V OL − Low-Level Output Voltage − V V OH − High-Level Ouptut Voltage − V 3.5 SN65LVDS22 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3 2.5 2 1.5 1 VCC = 3.3 V TA = 25°C 3 2 1 .5 0 0 −4 −3 −2 −1 0 0 IOH − High-Level Output Current − mA Figure 7. Figure 8. SN65LVDM22 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT SN65LVDM22 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C 3 V OL − Low-Level Output Voltage − V V OH − High-Level Output Voltage − V 6 IOL − Low-Level Output Current − mA 3.5 2.5 2 1.5 1 .5 0 3 2 1 0 −8 −6 −4 −2 0 0 IOH − High-Level Output Current − mA Figure 9. 10 4 2 2 4 6 Figure 10. Submit Documentation Feedback 8 10 IOL − Low-Level Output Current − mA 12 SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 APPLICATION INFORMATION FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. However, TI's LVDS receiver is different in how it handles the open-input circuit situation. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 11. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver is valid with less than a 100 mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in Figure 11. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDM22D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM22 SN65LVDM22DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM22 SN65LVDM22PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM22 SN65LVDS22D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS22 SN65LVDS22DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS22 SN65LVDS22PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS22 SN65LVDS22PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS22 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of