SN65LVDS349PWR

SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 QUAD HIGH-SPEED DIFFERENTIAL RECEIVER Check for Samples: SN65LVDS349 FEATURES 1 • • • • • Meets or Exceeds the Requirements of ANSI TIA/EIA-644A Standard Single-Channel Signaling Rates up to 560 Mbps -4 V to 5 V Common-Mode Input Voltage Range Flow-Through Architecture SN65LVDS349 Provides a Wide CommonMode Range Replacement for the SN65LVDS048A or the DS90LV048A • • • The SN65LVDS349 is a high-speed, quadruple differential receiver with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3-V of ground noise or a variety of differential and single-ended logic levels. The '349 is in a 16-pin package to match the industry-standard footprint of the DS90LV048. The '349 offers a flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. The LVDS349 provides 3x the standard's minimum common-mode noise voltage tolerance. The -4 V to 5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for more details on the ECL/PECL to LVDS interface. APPLICATIONS • • DESCRIPTION Logic Level Translator Point-to-Point Baseband Data Transmission Over 100-Ω Media ECL/PECL-to-LVTTL Conversion Wireless Base Stations Central Office or PABX Switches DATA TRANSFER RA TE vs FREE-AIR TEMPERATURE 550 (One of four shown; failsafe circuit does not exist in LVDS349) Data Transfer Rate - Mxfr/s 500 450 400 SN65LVDS349PW 350 300 250 200 -60 215 -1 prbs NRZ, V ID = 0.4 V VIC = 1.2 V, CL = 5.5 pF, 40% Open Eye 4 Receivers Switching, Input Jitter < 45 ps -40 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 100 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated SN65LVDS349 SLLSE23 – SEPTEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full input common-mode voltage range. The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat. The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN65LVDS349 is characterized for operation from -40°C to 85°C. SN65LVDS349 PW PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 RIN1– RIN1+ RIN2+ RIN2– RIN3– RIN3+ RIN4+ RIN4– EN ROUT1 ROUT2 VCC GND ROUT3 ROUT4 EN FUNCTIONAL BLOCK DIAGRAM (one of four receivers shown) EN EN RIN+ To Three Other Receivers RIN– A. Failsafe circuit does not exist in LVDS349 Table 1. AVAILABLE OPTIONS (1) (1) (2) 2 PART NUMBER (2) PACKAGE TYPE PACKAGE MARKING SN65LVDS349PW TSSOP DL349 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on ti.com. Add the R suffix to the device type (e.g., SN65LVDS349PWR) for taped and reeled carrier. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 Table 2. FUNCTION TABLE (1) 349 DEVICE INPUTS VID = VRIN+ - VRIN- EN EN ROUT VID≥ 50 mV H L or OPEN H -50 mV < VID < 50 mV H L or OPEN ? VID≤ -50 mV H L or OPEN Open X (1) (2) (3) OUTPUTS L ? (2) (3) H L or OPEN L or OPEN X Z X H Z This logic table is at dc condition. Outputs can toggle with inputs disconnected. ? indicates state is indeterminate EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 1 pF 6.5 kΩ 60 kΩ Attenuation Network RIN+, A 200 kΩ Attenuation Network RIN–, B 7V 250 kΩ 3 pF 6.5 kΩ 7V 7V 7V Attenuation Network VCC VCC 100 Ω 37 Ω EN, EN ROUT, Y 7V 7V 300 kΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 3 SN65LVDS349 SLLSE23 – SEPTEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2), VCC,VCCA,VCCD1, and VCCD2 Voltage range -0.5 V to 4 V Enables, ROUT, or Y -0.5 V to 6 V RIN+, RIN-, A or B -5 V to 6 V Human body model (3) Electrostatic discharge Charged-device model (4) A, B, RIN+, RIN- and GND ±15 kV All pins ±7 kV All pins Continuous power dissipation ±500 V See Dissipation Rating Table Storage temperature range (1) (2) (3) (4) -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal (GND, AGND). Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. THERMAL INFORMATION SN65LVDS349 THERMAL METRIC (1) PW UNITS 16 PINS qJA Junction-to-ambient thermal resistance (2) qJC(top) Junction-to-case(top) thermal resistance qJB Junction-to-board thermal resistance 111.9 (3) 33.3 (4) 52.4 (5) yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter qJC(bottom) (1) (2) (3) (4) (5) (6) (7) 4 Junction-to-case(bottom) thermal resistance 2.0 (6) (7) °C/W 51.2 N/A For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 RECOMMENDED OPERATING CONDITIONS VCC,VCCA,VCCD1, and VCCD2 Supply voltage VIH High-level input voltage Enables VIL Low-level input voltage Enables Magnitude of differential input voltage |VID| (LVDS349) Input voltage (any combination of common mode or input signals) TA Operating free-air temperature MIN NOM MAX UNIT 3 3.3 3.6 V 2 5 V 0 0.8 V 0.1 3 V -4 5 V -40 85 °C MIN TYP (1) MAX ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VITH1 Positive-going differential input voltage threshold See Figure 1 and Figure 2 VITH2 Negative-going differential input voltage threshold See Figure 1 VID(HYS) Differential input voltage hysteresis, VITH1 – VITH2 VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA ICC Supply current II Input current (RIN+, RIN-, A or B inputs) 50 -50 LVDS349 mV mV 50 LVDS349 UNIT mV 2.4 V 0.4 Enabled, EN at VCC, EN at 0 V, No load 16 20 Disabled, EN at 0 or EN at VCC 1.1 4 V mA VI = -4 V, Other input open -75 0 V ≤ VI ≤ 2.4 V, Other input 1.2 V -20 0 0 40 VCC = 1.5 V, VI = -4 V or 5 V, Other input open -50 50 VCC = 1.5 V, 0 V ≤ VI≤ 2.4 V, Other input at 1.2 V -20 20 -4 4 µA VI = 5 V, Other input open 0 µA Power-off input current (RIN+, RIN-, A or B inputs) LVDS349 IID Differential input current (IRIN+ - IRIN-, or IIA - IIB) LVDS349 VID = 100 mV, VIC = -3.9 V or 4.9 V IIH High-level input current Enables VIH = 2 V 0 10 µA IIL Low-level input current Enables VIL = 0.8 V 0 10 µA IOZ High-impedance output current -10 10 µA CIN Input capacitance, RIN+, RIN- input to GND or VI = 0.4 sin (4E6pft) + 0.5 V A or B input to AGND II(OFF) (1) VO = 0 V µA 5 pF All typical values are at 25°C and with a 3.3-V supply. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 5 SN65LVDS349 SLLSE23 – SEPTEMBER 2010 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 4 6 ns 4 6 ns UNIT tPLH Propagation delay time, low-to-high-level output 2.5 tPHL Propagation delay time, high-to-low-level output 2.5 tsk(p) Pulse skew (|tpHL1 - tpLH1|) tsk(o) Output skew (2) tsk(pp) Part-to-part skew (3) tr Output signal rise time tf Output signal fall time tr Output signal rise time tf Output signal fall time tPHZ Propagation delay time, high-level-to-high-impedance output 5 9 ns tPLZ Propagation delay time, low-level-to-high-impedance output 5 9 ns tPZH Propagation delay time, high-impedance-to-high-level output 8 12 ns tPZL Propagation delay time, high-impedance-to-low-level output 8 12 ns (1) (2) (3) 6 200 CL = 10 pF, See Figure 3 ps 150 ps 1 CL = 1 pF, See Figure 3 See Figure 4 ns 1.2 ns 1 ns 650 ps 400 ps All typical values are at 25°C and with a 3.3-V supply. tsk(o) is the magnitude of the time difference between the tPHL or tPLH of all receivers of a single device with all of their inputs connected together. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION IIA or IRIN+ A or RIN+ Y or ROUT VID (VIA + VIB)/2 or (VRIN+ + VRIN–)/2 VIC IOY or IROUT B or RIN– VIA or VRIN+ IIB or IRIN– VOY or VROUT VIB or VRIN– Figure 1. Voltage and Current Definitions 1000 Ω 100 Ω + 1000 Ω 100 Ω† VID + V1 V2 VO – – 10 pF VIC 10 pF 10 pF + – A. Fixture capacitance ±20%. B. Resistors are metal film, 1% tolerance, and surface mount VITH1 0V VID –100 mV VO 100 mV VID 0V VITH2 VO A. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1 ns. Figure 2. VITH1 and VITH2, Input Voltage Threshold Test Circuit and Definitions Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 7 SN65LVDS349 SLLSE23 – SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) A or RIN+ Y or ROUT VID VIA or VRIN+ B or RIN– CL VOY or VROUT VIB or VRIN– A or VRIN+ 1.4 V B or VRIN– 1V >1.5 µs 0.4 V VID 0V –0.2 V –0.4 V tPHL tPLH td1 td2 VOH VOY or VROUT VCC/2 VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 250 kHz, duty cycle = 50 ±2%, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%. Figure 3. Timing Test Circuit and Waveforms 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) 1.2 V RIN– 500 Ω ROUT RIN+ Inputs EN VROUT + _ VTEST 10 pF EN VTEST 2.5 V VRIN+ 1V 2V 1.4 V 0.8 V 2V 1.4 V 0.8 V EN EN tPZL tPZL tPLZ tPLZ 2.5 V 1.4 V VOL +0.5 V VOL VROUT VTEST 0V 1.4 V VRIN+ 2V 1.4 V 0.8 V 2V 1.4 V 0.8 V EN EN tPZH tPZH VOH VOH –0.5 V 1.4 V 0V VROUT A. tPHZ tPHZ All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 500 kHz, duty cycle = 50 ±2%, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%. Figure 4. Enable/Disable Time Test Circuit and Waveforms Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 9 SN65LVDS349 SLLSE23 – SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS LOW-TO-HIGH PROPAGATION DELAY vs FREE-AIR TEMPERATURE HIGH-TO-LOW PROPAGATION DELAY vs FREE-AIR TEMPERATURE 5 4.5 t PHL - High-to-Low Propagation Delay - ns t PLH - Low-to-High Propagation Delay - ns 5 VCC = 3 V VCC = 3.3 V 4 VCC = 3.6 V 3.5 3 -50 0 50 VCC = 3 V 4.5 VCC = 3.3 V 4 VCC = 3.6 V 3.5 3 -50 100 0 50 TA - Free-Air Temperature - °C TA - Free-Air Temperature - °C Figure 5. Figure 6. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 40 TA = 25°C, VCC = 3.3 V I OH - High-Level Output Current - mA I OL - Low-Level Output Current - mA TA = 25°C, VCC = 3.3 V 30 20 10 0 -10 -20 -30 -40 0 1 2 3 4 5 0 VOL - Low-Level Output Voltage - V Figure 7. 10 100 1 2 3 VOH - High-Level Output Voltage - V 4 Figure 8. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) DATA TRANSFER RATE vs FREE-AIR TEMPERATURE RMS SUPPLY CURRENT vs SWITCHING FREQUENCY 110 500 400 I CC - RMS Supply Current - mA Maximum T ransfer Rate - Mxfr/s 450 215 -1 prbs NRZ, VIC = 1.2 V, CL = 5.5 pF, 40% Open Eye, 4 Receivers Switching, VCC = 3.3 V, SN65LVDS349PW VID = 0.4 V 350 300 VID = 0.2 V VID = 0.1 V 4 Receivers Switching, 50% Duty Cycle, CL = 5.5 pF, TA = 25°C 90 VCC = 3.6 V VCC = 3.3 V 70 VCC = 3 V 50 30 250 200 -60 10 -40 -20 0 20 40 60 80 100 0 50 100 150 200 250 300 f - Switching Frequency - MHz TA - Free-Air Temperature - °C Figure 9. Figure 10. 223 -1 prbs NRZ, TA = 25°C, CL = 5.5 pF, 4 Receivers Switching, VCC = 3.3 V Figure 11. SN65LVDS349 Eye Pattern Running at 200 Mxfr/s Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 11 SN65LVDS349 SLLSE23 – SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION IMPEDANCE MATCHING AND REFLECTIONS A termination mismatch can result in reflections that degrade the signal at the load. A low source impedance causes the signal to alternate polarity at the load (oscillates) as shown in Figure 12. High source impedance results in the signal accumulating monotonically to the final value (stair step) as shown in Figure 13. Both of these modes result in a delay in valid signal and reduce the opening in the eye pattern. A 10% termination mismatch results in a 5% reflection (r = ZL - ZO/ZL + ZO), even a 1:3 mismatch absorbs half of the incoming signal. This shows that termination is important in the more critical cases, however, in a general sense, a rather large termination mismatch is not as critical when the differential output signal is much greater than the receiver sensitivity. TIME DOMAIN RESPONSE 0.25 TIME DOMAIN RESPONSE 0.25 ZS = 0 Ω ZO = 100 Ω ZT = 132 Ω V at Load 0.2 ZS = 0 Ω ZO = 100 Ω ZT = 90 Ω 0.2 V at Load VI 0.15 Voltage - V Voltage - V VI 0.1 0.05 0.15 0.1 0.05 0 0 0 5 10 15 20 25 0 t - Time - ns 5 10 15 20 25 t - Time - ns Figure 12. Low-Source Impedance Figure 13. High-Source Impedance For example, a 200-mV drive signal into a 100-Ω lossless transmission media with a termination resistor of 90 Ω to 132Ω results in ~227 mV to 189 mV into the receiver. This would typically be more than enough signal into a receiver with a sensitivity of ±50 mV assuming no other disturbance or attenuation on the line. The other factors, which reduce the signal margin, do affect this and therefore it is important to match the impedance as closely as possible to allow more noise immunity at the receiver. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 SN65LVDS349 www.ti.com SLLSE23 – SEPTEMBER 2010 ACTIVE FAILSAFE FEATURE A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current LVDS failsafe solutions require either external components with subsequent reductions in signal quality or integrated solutions with limited application. In the SN65LVDS349, the failsafe circuit does not exist. Thus the output can switch if there is noise on the input lines. EN EN RIN+ To Three Other Receivers RIN– Figure 14. Failsafe Circuit Does Not Exist in the SN65LVDS349 ECL/PECL-to-LVTTL CONVERSION WITH TI LVDS RECEIVER The various versions of emitter-coupled logic (i.e., ECL, PECL, and LVPECL) are often the physical layer of choice for system designers. Designers know that established technology is capable of high-speed data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the termination bias voltage required for ECL termination (VCC - 2 V). Figure 15 shows the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received by TI's wide common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the characteristic load impedance of 50 Ω. The R2 resistor is a small value intended to minimize common-mode reflections. VCC R1 = 50 Ω R2 = 50 Ω ICC 5 Meters of CAT-5 LV/PECL R3 VEE R3 VB VCC ICC LVDS VB R1 R1 R2 R3 = 240 Ω Figure 15. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS349 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LVDS349PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL349 SN65LVDS349PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL349 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of