SN65LVDT125DBT


 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 
 


  FEATURES D Signaling Rates >1.5 Gbps per Channel D Supports Telecom/Datacom and HDTV Video Switching D Non-Blocking Architecture Allows Each Output to be Connected to Any Input D Compatible With ANSI TIA/EIA-644-A LVDS Standard D 25 mV of Input Voltage Threshold Hysteresis D Propagation Delay Times, 900 ps Typical D Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels D Operates From a Single 3.3-V Supply D Integrated 110-Ω Line Termination Resistors Available With SN65LVDT125 APPLICATIONS D D D D Clock Buffering / Clock Muxing Wireless Base Stations High-Speed Network Routing Designed to support signaling rates up to 1.5 Gbps for OC-12 clocks (622 MHz). The 1.5-Gbps signaling rate allows use in HDTV systems, including SMPTE 292 video applications requiring signaling rates of 1.485 Gbps. The SN65LVDS125 and SN65LVDT125 are characterized for operation from −40°C to 85°C. SN65LVDS125DBT ( Marked as LVDS125) SN65LVDT125DBT ( Marked as LVDT125) (TOP VIEW) S10 S11 1A 1B S20 S21 2A 2B GND VCC GND 3A 3B S30 S31 4A 4B S40 S41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 VCC GND 1Y 1Z 1DE 2Y 2Z 2DE GND VCC GND 3Y 3Z 3DE 4Y 4Z 4DE GND VCC HDTV Video Switching Eye Pattern of Two Outputs Operating Simultaneously The SN65LVDS125 and SN65LVDT125 are 4x4 nonblocking crosspoint switches. Low-voltage differential signaling (LVDS) is used to achieve signaling rates of 1.5 Gbps per channel. Each output driver includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT125 incorporates 110-Ω termination resistors for those applications where board space is a premium. 175 mV/div DESCRIPTION VIC = 1.2 V SVIDS = 200 mV 1.5 Gbps 223−1 PRBS VCC = 3.3 V 200 − ps/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.       !"   #!$% &"' &!   #" #" (" "  " !" && )*' &! #"+ &"  ""%* %!&" "+  %% #""' Copyright  2002−2004, Texas Instruments Incorporated 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC DIAGRAM S10 − S41 8 1DE 1A 1Y 1B 1Z 2DE 2A 2B 2Y 4X4 MUX 2Z 3DE 3A 3Y 3B 3Z 4DE 4A 4Y 4B 4Z Integrated 110-W Termination on LVDT Only 2 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUT LVDS125 VCC A VCC B 7V 7V VCC VCC 300 kΩ DE S10, S41 400 Ω 400 Ω 300 kΩ 7V 7V OUTPUT LVDS125 VCC VCC VCC Y 7V Z 7V 3 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 CROSSPOINT LOGIC TABLES OUTPUT CHANNEL 1 CONTROL PINS INPUT SELECTED OUTPUT CHANNEL 2 CONTROL PINS INPUT SELECTED OUTPUT CHANNEL 3 CONTROL PINS OUTPUT CHANNEL 4 INPUT SELECTED CONTROL PINS INPUT SELECTED S10 S11 1Y/1Z S20 S21 2Y/2Z S30 S31 3Y/3Z S40 S41 4Y/4Z 0 0 1A/1B 0 0 1A/1B 0 0 1A/1B 0 0 1A/1B 0 1 2A/2B 0 1 2A/2B 0 1 2A/2B 0 1 2A/2B 1 0 3A/3B 1 0 3A/3B 1 0 3A/3B 1 0 3A/3B 1 1 4A/4B 1 1 4A/4B 1 1 4A/4B 1 1 4A/4B PACKAGE DISSIPATION RATINGS PACKAGE TA ≤ 25°C POWER RATING CIRCUIT BOARD MODEL DERATING FACTOR(1) ABOVE TA = 25°C TA = 85°C POWER RATING TSSOP (DBT) High−K(2) 1772 mW 15.4 mW/°C (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounded and with no air flow. (2) In accordance with the High−K thermal metric definitions of EIA/JESD51−6 847 mW THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS VALUE θJB θJC Junction-to-board thermal resistance 40.3 Junction-to-case thermal resistance 8.5 PD Device power dissipation Typical Maximum VCC = 3.3 V, TA = 25°C, 750 MHZ VCC = 3.6 V, TA = 85°C, 750 MHZ UNITS °C/W 356 mW 522 mW ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNITS Supply voltage range, vcc Voltage range Electrostatic discharge Continuous power dissipation Storage temperature range −0.5 V to 4 V S, DE −0.5 V to 4 V (A, B) −0.5 V to 4 V |VA − VB| (LVDT only) (Y, Z) Human body model(3) 1V All pins ±3 kV Charged-device model(4) All pins ±500 V −0.5 V to 4 V See Dissipation Rating Table −65°C to 150°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C101. 4 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS MIN NOM 3 3.3 Supply voltage, VCC High-level input voltage, VIH S10−S41, 1DE−4DE Low-level input voltage, VIL S10−S41, 1DE−4DE Magnitude of differential input voltage |VID| MAX UNIT 3.6 2 V V 0.8 V LVDS 0.1 LVDT 0.1 0.8 V 0 3.3 V 140 °C 85 °C Input voltage (any combination of common−mode or input signals) V Junction temperature, TJ Operating free-air temperature, TA (1) −40 (1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. TIMING SPECIFICATIONS PARAMETER tSET tHOLD MIN Input to select setup time Input to select hold time NOM MAX UNIT 0.6 ns 0.2 See Figure 7 tSWITCH Select to switch output 1.2 ns 1.6 ns INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted(1) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold See Figure 1 VIT− Negative-going differential input voltage threshold See Figure 1 VID(HYS) Differential input voltage hysteresis 1DE−4DE IIH High-level input current S10−S41 1DE−4DE MIN TYP(1) MAX UNIT 100 mV −100 mV 25 mV −10 VIH = 2 V 20 −10 µA IIL Low-level input current II Input current VI = 0 V or 3.3 V, second input at 1.2 V (other input open for LVDT) −20 20 µA II(OFF) Input current VCC ≤ 1.5 V, VI = 0 V or 3.3 V, second input at 1.2 V (other input open for LVDT) −20 20 µA IIO Input offset current (|IIA − IIB|) −6 6 µA Termination resistance (’LVDT) VIA = VIB, 0≤ VIA ≤ 3.3 V VID = 300 mV, VIC= 0 V to 3.3 V 90 110 132 Termination resistance(’LVDT with power-off) VID = 300 mV, VIC= 0 V to 3.3 V, VCC = 1.5 V 90 110 132 RT S10−S41 (’LVDS) CT Differential input capacitance (1) All typical values are at 25°C and with a 3.3 V supply. VIL = 0.8 V µA 20 0.6 Ω pF 5 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 350 454 mV mV VOD Differential output voltage magnitude See Figure 2 247 ∆VOD Change in differential output voltage magnitude between logic states VID = ±100 mV −50 50 VOC(SS) Steady-state common-mode output voltage 1.125 1.375 ∆VOC(SS) Change in steady-state common-mode output voltage between logic states −50 50 mV VOC(PP) Peak-to-peak common-mode output voltage 50 150 mV ICC Supply current RL=100Ω, 107 145 mA IOS Short-circuit output current VOY or VOZ = 0 V −27 27 mA IOSD Differential short circuit output current VOD = 0 V −12 12 mA IOZ High-impedance output current VO = 0 V or VCC −1 ±1 µA CO Differential output capacitance See Figure 3 CL = 1 pF 1.2 V pF SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted(1) PARAMETER tPLH tPHL Propagation delay time, low-to-high-level output tr tf Differential output signal rise time (20%−80%) tsk(p) tsk(o) TEST CONDITIONS Propagation delay time, high-to-low-level output See Figure 4 Differential output signal fall time (20%−80%) Pulse skew (|tPHL − tPLH|)(1) MIN TYP MAX 700 900 1200 700 900 1200 210 255 210 255 0 50 ps 150 ps 300 ps 0.4 3 ps 4.7 13 ps 65 110 ps 56 90 ps Channel-to-channel output skew(2) tsk(pp) Part-to-part skew(3) tjit(per) Period jitter, rms (1 standard deviation)(4) tjit(cc) Cycle-to-cycle jitter (peak)(4) tjit(pp) Peak-to-peak jitter(4) tjit(det) Deterministic jitter, peak-to-peak(4) tPHZ tPLZ Propagation delay, high-level-to−high-impedance output 1.5 Gbps 27−1 PRBS input(8) (see Figure 6) ps 6 6 See Figure 5 ns tPZH Propagation delay, high-impedance -to-high-level output 50 tPZL Propagation delay, high-impedance-to-low-level output 50 (1) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. (2) tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (4) Jitter specifications are based on design and characteriztion. Stimulus system jitter of 1.9 ps tjit(per), 16 ps tjit(cc). 17 ps tjit(pp), and 7.2 ps tjit(det) have been subtracted from the values. (5) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%), measured over 1000 samples. (6) Input voltage = VID = 200 mV, 50% duty cycle at 750 MHz, tr = tf = 50 ps (20% to 80%). (7) Input voltage = VID = 200 mV, 223−1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples. (8) Input voltage = VID = 200 mV, 27−1 PRBS pattern at 1.5 Gbps, tr = tf = 50 ps (20% to 80%). 6 Propagation delay, low-level-to-high-impedance output 750 MHz clock input(5) (see Figure 6) 750 MHz clock input(6) (see Figure 6) 1.5 Gbps 223−1 PRBS input(7) (see Figure 6) UNIT 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION IIA VIA+VIB 2 Y B Z VID VIA VIC A VIB VOD VOY VOY+VOZ 2 VOZ IIB Figure 1. Voltage and Current Definitions 3.75 kΩ Y VOD Z + _ 100 Ω 0 V ≤ V(test) ≤ 2.4 V 3.75 kΩ Figure 2. Differential Output Voltage (VOD) Test Circuit A Y A ≈1.4 V B ≈1 V 49.9 Ω ±1% VID VOC(PP) B Z 1 pF 49.9 Ω ±1% VOC VOC(SS) VOC NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100W; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.;the measurement of VOC(PP) is made on test equipment with a −3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions fot the Driver Common-Mode Output Voltage A VIA VID B VIB Y 1 pF VOY Z 100 Ω VIA 1.4 V VIB 1V VID 0.4 V 0V −0.4 V VOZ tPHL tPLH 0V Differential 80% VOY − VOZ 20% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ .25 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Timing Test Circuit and Waveforms 7 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 49.9 Ω ±1% Y 1 V or 1.4 V 1 pF 1.2 V VOY 49.9 Ω ±1% Z DE 1.2 V VOZ 3V 1.5 V 0V DE 1.4 V 1.25 V 1.2 V VOY or VOZ tPZH tPHZ 1.2 V 1.15 V 1V VOZ or VOY tPZL tPLZ : NOTE A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 5. Enable and Disable Time Circuit and Definitions Clock Input VA 0V VB 0V Ideal Output VY − VZ 1/fo 1/fo Period Jitter Cycle-to-Cycle Jitter Actual Output Actual Output 0V 0V VY − VZ tc(n) VY − VZ tc(n) tc(n+1) tjit(cc) = | tc(n) − tc(n + 1) | tjit(pp) = | tc(n) − 1/fo | Peak-to-Peak Jitter PRBS Input VA 0V VB PRBS Output VY 0V VZ NOTE: A. All input pulses are supplied by an Agilent 81250 Stimulus System. NOTE: B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software. tjit(pp) Figure 6. Driver Jitter Measurement Waveforms 8 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 A/B A/B S tSET tHOLD OUT Y/Z Y/Z tSWITCH DE A/B A/B S tSET OUT tHOLD Y/Z Y/Z tSWITCH DE NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches. Figure 7. Input to Select for Both Rising and Falling Edge Setup and Hold Times 9 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 1000 110 105 100 1000 940 tPHL 880 tPLH 820 VCC = 3.3 V VIC = 1.2 V VID = 200 mV f = 1 MHz 760 0 −45 100 200 300 400 500 600 700 800 f − Frequency − MHz −25 −5 35 75 95 0 VID =200 m V 40 VID = 400 m V 8 4 VID = 800 m V VID =200 m V 100 0 0 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 1400 1600 f − Frequency − MHz Data Rate − Mbps Figure 11 Figure 12 PEAK-TO-PEAK JITTER vs DATA RATE 0 Figure 13 PEAK-TO-PEAK JITTER vs DATA RATE 120 20 80 VID = 400 m V 40 VID =200 m V 0 VCC = 3.3 V TA = 25°C VIC = 2.9 V Input = Clock 16 VID =200 m V 12 VID = 800 m V 8 VID = 400 m V 4 Figure 14 80 VID =200 m V 60 40 VID = 400 m V 20 0 0 200 400 600 800 1000 1200 1400 1600 Data Rate − Mbps VID = 800 m V VCC = 3.3 V TA = 25°C VIC = 2.9 V Input = PRBS 223−1 100 Peak-To-Peak Jitter − ps VID = 800 m V Peak-To-Peak Jitter − ps VCC = 3.3 V TA = 25°C VIC = 1.2 V Input = PRBS 223−1 100 200 300 400 500 600 700 800 f − Frequency − MHz PEAK-TO-PEAK JITTER vs FREQUENCY 120 0 VID =200 m V 12 20 0 20 VCC = 3.3 V TA = 25°C VIC= 1.2 mV Input = Clock 16 VID = 400 m V VID = 400 m V 60 PEAK-TO-PEAK JITTER vs FREQUENCY VID = 800 m V 80 60 0.5 1 1.5 2 2.5 3 3.5 VIC − Common-Mode Input Voltage − V Figure 10 Peak-To-Peak Jitter − ps VID = 800 m V 0 Peak-To-Peak Jitter − ps 55 20 VCC = 3.3 V TA = 25°C VIC = 400 mV Input = PRBS 223−1 100 Peak-To-Peak Jitter − ps Peak-To-Peak Jitter − ps 15 120 VCC = 3.3 V TA = 25°C VIC = 400 mV Input = Clock 4 100 VCC = 3.3 V TA = 25°C VID = 200 mV f = 1 MHz 760 PEAK-TO-PEAK JITTER vs DATA RATE 20 8 tPLH 820 Figure 9 PEAK-TO-PEAK JITTER vs FREQUENCY 12 880 TA − Free-Air Temperature − °C Figure 8 16 tPHL 940 700 700 95 10 t pd − Propagation Delay Time − ps VCC = 3.3 V TA = 25°C VIC = 1.2 V VID = 200 mV t pd − Propagation Delay Time − ps I CC − Supply Current − mA 115 PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE 0 100 200 300 400 500 f − Frequency − MHz Figure 15 600 700 800 0 200 400 600 800 1000 1200 1400 1600 Data Rate − Mbps Figure 16 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE PEAK-TO-PEAK JITTER vs DATA RATE 140 VCC = 3.3 V VIC = 1.2 V VID = 200 mV Input = 1.5 Gbps PRBS 223−1 VCC = 3.3 V VIC = 1.2 V VID = 200 mV TA = 25°C Input = PRBS 223−1 120 Peak-To-Peak Jitter − ps 72 64 56 100 80 60 40 48 20 0 40 −20 0 20 40 60 80 100 0 500 TA − Free-Air Temperature − °C 1000 1500 2000 2500 Data Rate − Mbps Figure 17 Figure 18 DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY 400 80 350 70 60 300 VCC = 3.3 V VIC = 1.2 V VID = 200 mV TA = 25°C Input = Clock 250 200 150 Added Random Jitter 50 40 30 100 20 50 10 0 0 400 800 1200 1600 f − Frequency − MHz Period Jitter − ps −40 V OD − Differential Output Voltage − mV Peak-To-Peak Jitter − ps 80 0 2000 Figure 19 11 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 APPLICATION INFORMATION CONFIGURATION EXAMPLES S10 0 S30 1 S11 0 S31 0 S20 0 S40 1 S21 1 S41 1 S10 0 S30 0 S20 0 S40 0 S21 0 S41 0 1A 1Y 1A 1Y 1B 1Z 1B 1Z 2A 2Y 2Y 2B 2Z 2Z 3A 3Y 3Y 3B 3Z 3Z 4A 4Y 4Y 4B 4Z 4Z S10 0 S30 1 S11 0 S31 0 S20 0 S40 1 S21 0 S41 0 S10 1 S30 0 S11 1 S31 0 S20 1 S40 0 S21 1 S41 0 1A 1Y 1A 1Y 1B 1Z 1B 1Z 2Y 2Y 2Z 2Z 12 S11 0 S31 0 3A 3Y 3Y 3B 3Z 3Z 4Y 4A 4Y 4Z 4B 4Z 

 
   www.ti.com SLLS555C − DECEMBER 2002 − REVISED OCTOBER 2004 APPLICATION INFORMATION TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, ETC.) 3.3 V or 5 V 50 Ω 3.3 V SN65LVDS125 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC −2 V VTT Figure 20. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 3.3 V 50 Ω 50 Ω 3.3 V 3.3 V SN65LVDS125 A CML B 50 Ω 50 Ω 3.3 V Figure 21. Current-Mode Logic (CML) 3.3 V 3.3 V 50 Ω SN65LVDS125 A ECL B 50 Ω 1.1 kΩ VTT 1.5 kΩ VTT = VCC −2 V 3.3 V Figure 22. Single-Ended (LVPECL) 3.3 V or 5 V 50 Ω 3.3 V SN65LVDS125 A 100 Ω LVDS B 50 Ω Figure 23. Low-Voltage Differential Signaling (LVDS) 13 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) SN65LVDS125DBT NRND TSSOP DBT 38 TBD Call TI Call TI -40 to 85 SN65LVDS125DBTR NRND TSSOP DBT 38 TBD Call TI Call TI -40 to 85 SN65LVDT125DBT NRND TSSOP DBT 38 TBD Call TI Call TI -40 to 85 SN65LVDT125DBTR NRND TSSOP DBT 38 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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