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SN7414D

SN7414D

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC14

  • 描述:

    IC INVERT SCHMITT 6CH 6IN 14SOIC

  • 数据手册
  • 价格&库存
SN7414D 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 SNx414 and SNx4LS14 Hex Schmitt-Trigger Inverters 1 Features 3 Description • • • Each circuit in SNx414 and SNx4LS14 functions as an inverter. However, because of the Schmitt-Trigger action, they have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. 1 Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity 2 Applications • • • • • • HVAC Gateways Residential Ductless Air Conditioning Outdoor Units Robotic Controls Industrial Stepper Motors Power Meter and Power Analyzers Digital Input Modules for Factory Automation These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals. Device Information(1) PART NUMBER SN7414, SN74LS14 SN5414, SN54LS14 PACKAGE BODY SIZE (NOM) SOIC (14) 4.90 mm × 3.91 mm SSOP (14) 6.20 mm × 5.30 mm PDIP (14) 19.30 mm × 6.35 mm SO (14) 10.30 mm × 5.30 mm CDIP (14) 19.56 mm × 6.67 mm CFP (14) 9.21 mm × 5.97 mm LCCC (20) 8.89 mm × 8.89 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) A Y Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 7.1 Series SN5414 and SN7414 Devices ....................... 9 7.2 Series SN54LS14 and SN74LS14 Devices ............ 11 8 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 13 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application .................................................. 14 9.3 System Examples ................................................... 16 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 17 11.1 Layout Guidelines ................................................. 17 11.2 Layout Example .................................................... 17 12 Device and Documentation Support ................. 18 12.1 12.2 12.3 12.4 12.5 12.6 Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 18 13 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History Changes from Revision B (February 2002) to Revision C Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Deleted Ordering Information table; see the Package Option Addendum at the end of the data sheet ............................... 1 • Changed Package thermal impedance, RθJA, values in Thermal Information table From: 86°C/W To: 90.1°C/W (D), From: 96°C/W To: 105.4°C/W (DB), From: 80°C/W To: 54.9°C/W (N), and From: 76°C/W To: 88.8°C/W (NS)................... 4 2 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 5 Pin Configuration and Functions D, DB, N, NS, J, or W Package 14-Pin SOIC, SSOP, PDIP, SO, CDIP, or CFP Top View 5 10 5Y 6 9 4A GND 7 8 4Y 2A 4 18 6Y NC 5 17 NC 2Y 6 16 5A NC 7 15 NC 3A 8 14 5Y 9 3Y 6A 3A 19 5A Not to scale 13 11 NC 4 VCC 2Y 1 6Y 20 6A 12 12 13 3 11 2 2A 1A 1Y 2 VCC 10 14 1Y 1 3 1A FK Package 20-Pin LCCC Top View 4A 4Y NC GND 3Y Not to scale NC – No internal connection Pin Functions PIN I/O DESCRIPTION SOIC, SSOP, TVSOP, CDIP, PDIP,TSSOP, CFP LCCC 1A 1 2 I Channel 1 input 1Y 2 3 O Channel 1 output 2A 3 4 I Channel 2 input 2Y 4 6 O Channel 2 output 3A 5 8 I Channel 3 input 3Y 6 9 O Channel 3 output 4A 9 13 I Channel 4 input 4Y 8 12 O Channel 4 output 5A 11 16 I Channel 5 input 5Y 10 14 O Channel 5 output 6A 13 19 I Channel 6 input 6Y 12 18 O Channel 6 output GND 7 10 — Ground NC — 1, 5, 7, 11, 15, 17 — No internal connection VCC 14 20 — Power supply NAME Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 3 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 7 V Supply voltage, VCC (2) SNx414 Input voltage 5.5 SNx4LS14 Junction temperature, TJ Storage temperature, Tstg (1) (2) V 7 –65 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage IOH High-level output current IOL Low-level output current MIN NOM MAX SN5414, SN54LS14 4.5 5 5.5 SN7414, SN74LS14 4.75 5 5.25 SN5414, SN7414 –0.8 SN54LS14, SN74LS14 –0.4 SN5414, SN7414 TA Operating free-air temperature UNIT V mA 16 SN54LS14 4 SN74LS14 8 SN5414, SN54LS14 –55 125 SN7414, SN74LS14 0 70 mA °C 6.4 Thermal Information SNx414, SNx4LS14 THERMAL METRIC (1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) UNIT 14 PINS 14 PINS 14 PINS 14 PINS Junction-to-ambient thermal resistance (2) 90.1 105.4 54.9 88.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50.3 57.3 42.5 46.5 °C/W RθJB Junction-to-board thermal resistance 44.3 52.7 34.7 47.5 °C/W ψJT Junction-to-top characterization parameter 17.9 22.5 27.8 16.8 °C/W ψJB Junction-to-board characterization parameter 44.1 52.2 34.6 47.2 °C/W RθJA (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The package termal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VT+ VCC = 5 V VT– VCC = 5 V Hysteresis (VT+ – VT–) VCC = 5 V VIK VOH MIN TYP (2) SNx414 1.5 1.7 2 SNx4LS14 1.4 1.6 1.9 SNx414 0.6 0.9 1.1 SNx4LS14 0.5 0.8 1 0.4 0.8 –1.5 VCC = MIN, II = –18 mA, SNx4LS14 –1.5 VCC = MIN, VI = 0.6 V, IOH = –0.8 mA, SNx414 2.4 3.4 VCC = MIN, VI = 0.5 V, IOH = –0.4 mA, SNx4LS14 2.4 3.4 VCC = MIN, VI = 1.9 V IT+ VCC = 5 V, VI = VT+ IT– VCC = 5 V, VI = VT– IOL = 4 mA, SNx4LS14 0.25 0.4 IOL = 8 mA, SN74LS14 0.35 0.5 SNx4LS14 –0.14 SNx414 –0.56 SNx4LS14 –0.18 IIH 1 0.1 VCC = MAX, VIH = 2.4 V, SNx414 40 VCC = MAX, VIH = 2.7 V, SNx4LS14 20 VCC = MAX, VIL = 0.4 V IOS (3) VCC = MAX ICCH VCC = MAX ICCL VCC = MAX SNx414 V V mA VCC = MAX, VI = 7 V, SNx4LS14 IIL V mA VCC = MAX, VI = 5.5 V, SNx414 II (1) (2) (3) 0.4 –0.43 V V 0.2 SNx414 UNIT V VCC = MIN, II = –12 mA, SNx414 VCC = MIN, VI = 2 V, IOL = 16 mA, SNx414 VOL MAX –0.8 –1.2 SNx4LS14 –0.4 SNx414 –18 –55 SNx4LS14 –20 –100 SNx414 22 36 SNx4LS14 8.6 16 SNx414 39 60 SNx4LS14 12 21 mA µA mA mA mA mA For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V and TA = 25°C. Not more than one output should be shorted at a time. 6.6 Switching Characteristics VCC = 5 V, TA = 25°C, and over operating free-air temperature range (unless otherwise noted; see Figure 20) PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN tPLH A Y RL = 400 Ω and CL = 15 pF, or RL = 2 kΩ and CL = 15 pF tPHL A Y RL = 400 Ω and CL = 15 pF, or RL = 2 kΩ and CL = 15 pF Copyright © 1983–2016, Texas Instruments Incorporated TYP MAX 15 22 ns 15 22 ns Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 UNIT 5 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com 6.7 Typical Characteristics 6.7.1 SNx414 Circuits Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SN5414 only. 0.90 VCC = 5 V V T– – Negative-Going Threshold Voltage – V V T+ – Positive-Going Threshold Voltage – V 1.70 1.69 1.68 1.67 1.66 1.65 1.64 1.63 1.62 1.61 VCC = 5 V 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.80 1.60 –75 –50 –25 0 25 50 75 100 125 –75 –50 0 –25 25 50 75 100 125 TA – Free-Air Temperature –°C TA – Free-Air Temperature –°C Figure 1. Positive-Going Threshold Voltage vs Free-Air Temperature Figure 2. Negative-Going Threshold Voltage vs Free-Air Temperature 850 VCC = 5 V TA = 25°C VCC = 5 V Relative Frequency of Occurence 840 V T+ – V T– – Hysteresis – mV 830 820 810 800 790 780 770 760 750 –75 –50 –25 0 25 50 75 100 740 125 760 Figure 3. Hysteresis vs Free-Air Temperature 820 840 860 880 900 2.0 TA = 25°C 1.6 Positive-Going Threshold Voltage, VT+ 1.4 TA = 25°C 1.8 V T+ – VT– – Hysteresis – V 1.8 Threshold Voltage -– V 800 Figure 4. Distribution of Units for Hysteresis 2.0 1.2 1.0 0.8 Negative-Going Threshold Voltage, VT– 0.6 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.4 0.2 0.2 0 0 4.5 5 5.25 4.75 VT+ – VT– – Hysteresis – mV 5.5 Figure 5. Threshold Voltages vs Supply Voltage 6 780 VT+ – VT– – Hysteresis – mV TA – Free-Air Temperature –°C Submit Documentation Feedback 4.5 5 5.25 4.75 VCC – Supply Voltage – V 5.5 Figure 6. Hysteresis vs Supply Voltage Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 SNx414 Circuits (continued) 4 VO – Output Voltage – V VCC = 5 V TA = 25°C VT– VT+ 3 2 1 0 0 0.4 0.8 1.2 1.6 2 VCC – Supply Voltage – V Figure 7. Output Voltage vs Input Voltage Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 7 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com 6.7.2 SNx4LS14 Circuits Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are applicable for SNx4LS14 only. 0.90 VCC = 5 V 1.69 VT– – Negative-Going Threshold Voltage – V V T+ – Positive-Going Threshold Voltage – V 1.70 1.68 1.67 1.66 1.65 1.64 1.63 1.62 1.61 VCC = 5 V 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 0.80 1.60 –75 –50 –25 0 25 50 75 100 –75 –50 125 TA – Free-Air Temperature –°C Figure 8. Positive-Going Threshold Voltage vs Free-Air Temperature 0 25 50 75 100 –25 TA – Free-Air Temperature –°C 125 Figure 9. Negative-Going Threshold Voltage vs Free-Air Temperature 850 Relative Frequency of Occurence V T+ – VT– – Hysteresis – V VCC = 5 V TA = 25°C VCC = 5 V 840 830 820 810 800 790 780 770 99% ARE ABOVE 735 mV 760 750 –75 –50 –25 0 25 50 75 100 720 125 TA – Free-Air Temperature –°C 740 760 780 800 820 840 860 880 VT+ – VT– – Hysteresis – mV Figure 10. Hysteresis vs Free-Air Temperature Figure 11. Distribution of Units for Hysteresis 4 2.0 VCC = 5 V TA = 25°C TA = 25°C 1.8 VT– VT+ 3 Positive-Going Threshold Voltage, VT+ 1.4 VO – Output Voltage – V Threshold Voltage – V 1.6 1.2 Negative-Going Threshold Voltage, VT– 1.0 0.8 Hysteresis, VT+ – VT– 0.6 2 1 0.4 0.2 0 0 4.5 4.75 5 5.25 5.5 VCC – Supply Voltage – V Figure 12. Threshold Voltages and Hysteresis vs Supply Voltage 8 Submit Documentation Feedback 0 0.8 0.4 1.2 1.6 2 VI – Input Voltage – V Figure 13. Output Voltage vs Input Voltage Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 7 Parameter Measurement Information 7.1 Series SN5414 and SN7414 Devices Test Point VCC VCC RL RL From Output Under Test CL From Output Under Test Test Point CL Figure 14. Load Circuit For 2-State Totem-Pole Outputs VCC Test Point Figure 15. Load Circuit For Open-Collector Outputs High-Level Pulse RL 1.5 V 1.5 V S1 tw From Output Under Test Low-Level Pulse CL 1 kΩ 1.5 V 1.5 V S2 Figure 16. Load Circuit For 3-State Outputs Figure 17. Voltage Waveforms Pulse Durations 3V Timing Input 3V Input 1.5 V 1.5 V 1.5 V 0V 0V th tsu Data Input tPLH 3V 1.5 V 1.5 V tPHL In-Phase Output VOH 1.5 V 0V 1.5 V VOL tPHL tPLH Out-of-Phase Output VOH 1.5 V 1.5 V VOL Figure 18. Voltage Waveforms Setup and Hold Times Copyright © 1983–2016, Texas Instruments Incorporated Figure 19. Voltage Waveforms Propagation Delay Times Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 9 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com Series SN5414 and SN7414 Devices (continued) 3V Output Control (low-level enabling) 1.5 V 1.5 V 0V tPZL tPLZ Waveform 1 ≈1.5 V 1.5 V VOL tPZH VOL + 0.5 V tPHZ VOH Waveform 2 1.5 V VOH – 0.5 V ≈1.5 V A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω ; tr and tf ≤ 7 ns for Series SN5414 and SN7414 devices and tr and tf ≤ 2.5 ns for Series SN54S14 and SN74S14 devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 20. Voltage Waveforms Enable and Disable Times, 3-State Outputs 10 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 7.2 Series SN54LS14 and SN74LS14 Devices Test Point VCC VCC RL RL From Output Under Test CL From Output Under Test Test Point CL Figure 21. Load Circuit For 2-State Totem-Pole Outputs VCC Test Point Figure 22. Load Circuit For Open-Collector Outputs High-Level Pulse RL 1.3 V 1.3 V S1 tw From Output Under Test Low-Level Pulse CL 5 kΩ 1.3 V 1.3 V S2 Figure 23. Load Circuit For 3-State Outputs Figure 24. Voltage Waveforms Pulse Durations 3V Timing Input 3V Input 1.3 V 1.3 V 1.3 V 0V 0V th tsu Data Input tPLH 3V 1.3 V 1.3 V tPHL In-Phase Output VOH 1.3 V 1.3 V 0V VOL tPHL tPLH Out-of-Phase Output VOH 1.3 V 1.3 V VOL Figure 25. Voltage Waveforms Setup and Hold Times Copyright © 1983–2016, Texas Instruments Incorporated Figure 26. Voltage Waveforms Propagation Delay Times Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 11 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com Series SN54LS14 and SN74LS14 Devices (continued) Output Control (low-level enabling) 3V 1.3 V 1.3 V 0V tPZL Waveform 1 tPLZ ≈1.5 V 1.3 V VOL tPZH VOL + 0.5 V tPHZ VOH Waveform 2 1.3 V VOH – 0.5 V ≈1.5 V A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 27. Voltage Waveforms Enable and Disable Times, 3-State Outputs 12 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 8 Detailed Description 8.1 Overview The SNx414 and SNx4LS14 Schmitt-Trigger devices contain six independent inverters. They perform the Boolean function Y = A in positive logic. Schmitt-Trigger inputs are designed to provide a minimum separation between positive and negative switching thresholds. This allows for noisy or slow inputs that would cause problems such as oscillation or excessive current draw with normal CMOS inputs. 8.2 Functional Block Diagram A Y Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description The device can operate from very slow transition edge inputs. This device has high noise immunity. 8.4 Device Functional Modes Table 1 lists the functional modes of the SNx414 and SNx4LS14. Table 1. Function Table Copyright © 1983–2016, Texas Instruments Incorporated INPUT A OUTPUT Y H L L H Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 13 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SNx414 and SNx4LS14 device is a Schmitt-Trigger input CMOS device that can be used for a multitude of inverting buffer type functions. The application shown here takes advantage of the Schmitt-Trigger inputs to produce a delay for a logic input. 9.2 Typical Application Copyright © 2016, Texas Instruments Incorporated Figure 28. Simplified Application Schematic 9.2.1 Design Requirements This device uses CMOS technology. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. Parallel output drive can create fast edges into light loads, so consider routing and load conditions to prevent ringing. 9.2.2 Detailed Design Procedure This circuit is designed around an RC network that produces a slow input to the second inverter. The RC time constant (τ) is calculated from: τ = RC. The delay time for this circuit is from tdelay(min) = –ln |1 – VT+(min) / VCC| τ to tdelay(max) = –ln |1 – VT+(max) / VCC| τ. It must be noted that the delay is consistent for each device, but because the switching threshold is only ensured between the minimum and maximum value, the output pulse length varies between devices. These values must be calculated by using the minimum and maximum ensured VT+ values in the Electrical Characteristics. The resistor value must be chosen such that the maximum current to and from the SNx414/SNx4LS14 is 8 mA at 5-V VCC. 14 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 Typical Application (continued) 9.2.3 Application Curve VCC Voltage VT+(max) VT+ VT+ Typical VT+(min) tdelay (max) t delay (min) VT (max) |W VCC VT (min) ln | 1 |W VCC ln | 1 VC VOUT 0.0 t0 t0 + 2 t0 + 22 t0 + 32 t0 + 42 t0 + 52 Time Figure 29. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 15 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com 9.3 System Examples Here are some examples of various applications using the SNx414 and SNx4LS14 device. TTL System VT+ VT– Input CMOS Sine-Wave Oscillator Output Figure 30. TTL System Interface For Slow Input Waveforms Figure 31. Pulse Shaper 0.1 Hz to 10 MHz 330Ω VT+ VT– Input Input Output Figure 32. Multivibrator Figure 33. Threshold Detector Open-Collector Output Input Input A Output VT+ Point A Output Figure 34. Pulse Stretcher 16 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 SN5414, SN54LS14, SN7414, SN74LS14 www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. The VCC terminal must have a good bypass capacitor to prevent power disturbance. TI recommends using a 0.1-µF capacitor on the VCC terminal, and must be placed as close as possible to the pin for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such inputs must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. Floating outputs are generally acceptable, unless the part is a transceiver. 11.2 Layout Example Vcc Input Unused Input Output Output Unused Input Input Figure 35. Layout Diagram Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 17 SN5414, SN54LS14, SN7414, SN74LS14 SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN5414 Click here Click here Click here Click here Click here SN54LS14 Click here Click here Click here Click here Click here SN7414 Click here Click here Click here Click here Click here SN74LS14 Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14 PACKAGE OPTION ADDENDUM www.ti.com 4-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9665801Q2A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629665801Q2A SNJ54LS 14FK 5962-9665801QCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9665801QC A SNJ54LS14J 5962-9665801QDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9665801QD A SNJ54LS14W 5962-9665801VDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9665801VD A SNV54LS14W JM38510/31302BCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31302BCA Samples M38510/31302BCA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 31302BCA Samples SN5414J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN5414J Samples SN54LS14J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54LS14J Samples SN7414D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7414 Samples SN7414DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7414 Samples SN7414DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7414 Samples SN7414N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN7414N Samples SN7414NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN7414 Samples SN74LS14D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples SN74LS14DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples SN74LS14DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Sep-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LS14DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples SN74LS14DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples SN74LS14DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples SN74LS14DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples SN74LS14N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS14N Samples SN74LS14NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS14N Samples SN74LS14NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS14 Samples SNJ5414J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ5414J Samples SNJ5414W ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ5414W Samples SNJ54LS14FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629665801Q2A SNJ54LS 14FK SNJ54LS14J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9665801QC A SNJ54LS14J SNJ54LS14W ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9665801QD A SNJ54LS14W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 2 Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Sep-2022 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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