SN74ABT2952ADBR

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 D D D D D D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions Noninverting Outputs Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs SN54ABT2952A . . . JT OR W PACKAGE SN74ABT2952A . . . DB, DW, PW, OR NT PACKAGE (TOP VIEW) B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CLKENAB GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA CLKENBA SN54ABT2952A . . . FK PACKAGE (TOP VIEW) B6 B7 B8 NC VCC A8 A7 D description To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 4 B5 B4 B3 NC B2 B1 OEAB 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 A6 A5 A4 NC A3 A2 A1 CLKAB CLKENAB GND NC CLKENBA CLKBA OEBA The ’ABT2952A transceivers consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. NC – No internal connection The SN54ABT2952A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT2952A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 FUNCTION TABLE† INPUTS OUTPUT B CLKENAB CLKAB OEAB A H X L X X H or L L X B0‡ B0‡ L ↑ L L L H L ↑ L H X X H X Z † A-to-B data flow is shown; B-to-A data flow is similar, but uses CLKENBA, CLKBA, and OEBA. ‡ Level of B before the indicated steady-state input conditions were established logic symbol§ OEBA CLKENBA CLKBA OEAB CLKENAB CLKAB A1 A2 A3 A4 A5 A6 A7 A8 15 13 14 9 11 10 16 EN3 G1 1 C5 EN4 G2 2 C6 3 1 5D 6D 1 4 17 7 18 6 19 5 20 4 21 3 22 2 23 1 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 B2 B3 B4 B5 B6 B7 B8 SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 logic diagram (positive logic) CLKENAB CLKAB OEAB CLKENBA CLKBA OEBA 11 10 9 13 14 15 C1 A1 16 8 1D B1 C1 1D To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT2952A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT2952A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT2952A MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current ∆t/∆v Input transition rise or fall rate High-level input voltage SN74ABT2952A MIN 2 2 0.8 Input voltage 0 Outputs enabled UNIT V V 0.8 V VCC –32 V mA 48 64 mA 10 10 ns/V 0 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL MIN VCC = 4 4.5 5V MIN –1.2 MAX SN74ABT2952A MIN –1.2 MAX –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* VI = VCC or GND IOZH‡ IOZL‡ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0 0, VI = VCC or GND VO = 2.5 V Outputs high A or B ports ICEX IO§ 0.55 0.55* 0.55 A or B ports Outputs high Ci Control inputs Cio A or B ports mV ±1 ±1 ±100 ±100 ±100 50* 10 50 µA –50* –10 50 –100 –180 50 –50 –180 –50 µA –50 µA ±100 µA 50 µA –180 mA 1 250 250 250 µA Outputs low 24 35 35 35 mA Outputs disabled 0.5 250 250 250 µA 1.5 1.5 1.5 mA VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC¶ V ±1 ±100* –50 V V 100 Control inputs UNIT 2 0.55 IOL = 64 mA VCC = 5 5.5 5 V, V ICC SN54ABT2952A 2.5 Vhys II TA = 25°C TYP† MAX VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 3.5 pF 7.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C fclock tw Clock frequency Pulse duration, CLK high or low A or B tsu Setup time before CLK↑ th Hold time after CLK↑ CLKEN High or low A or B CLKEN POST OFFICE BOX 655303 MIN MAX 0 150 SN54ABT2952A MIN MAX 0 150 SN74ABT2952A MIN MAX 0 150 3.3 3.3 3.3 2.5 3 2.5 3 3 3 1.5 1.5 1.5 2 2 2 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns 5 SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ 6 FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN TYP SN54ABT2952A MAX 150 CLKAB or CLKBA B or A OEBA or OEAB A or B OEBA or OEAB A or B POST OFFICE BOX 655303 MIN MAX 150 SN74ABT2952A MIN 150 MHz 2 3.3 5.2 2 6.3 2 5.9 2.5 4 6.1 2.5 6.8 2.5 6.3 1.5 3.2 4.7 1.5 5.7 1.5 5.6 2 3.7 5.7 2 6.7 2 6.6 1.5 3.5 5.1 1.5 6.5 1.5 6.4 1.5 3.4 5.9 1.5 6.7 1.5 6.2 • DALLAS, TEXAS 75265 UNIT MAX ns ns ns SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 0V Output 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH 1.5 V 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 12-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 5962-9308602QLA ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9308602QL A SNJ54ABT2952AJ T SN74ABT2952ADWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT2952A SNJ54ABT2952AJT ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-9308602QL A SNJ54ABT2952AJ T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of