SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
D
D
D
D
D
D
D
D
D
D
D
Independent Asynchronous Inputs and
Outputs
Low-Power Advanced CMOS Technology
Bidirectional
Dual 1024 by 9 Bits
Programmable Almost-Full/Almost-Empty
Flag
Empty, Full, and Half-Full Flags
Access Times of 25 ns With a 50-pF Load
Data Rates up to 50 MHz
Fall-Through Times of 22 ns Maximum
High Output Drive for Direct Bus Interface
Package Options Include 44-Pin Plastic
Leaded Chip Carriers (FN) and 64-Pin Thin
Quad Flat (PAG, PM) Packages
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT2235 is arranged as two 1024 × 9-bit FIFOs for high speed and fast access times.
It processes data at rates up to 50 MHz, with access times of 25 ns in a bit-parallel format.
The SN74ACT2235 consists of bus-transceiver circuits, two 1024 × 9-bit FIFOs, and control circuitry arranged
for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable (GAB
and GBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates
the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.
Figure 2 shows the eight fundamental bus-management functions that can be performed with the
SN74ACT2235.
For more information on this device family, see the application report, 1K × 9 × 2 Asynchronous FIFO
SN74ACT2235, literature number SCAA010.
The SN74ACT2235 is characterized for operation from 0°C to 70°C.
A2
A1
A0
GND
GBA
SBA
SAB
GAB
GND
B0
B1
FN PACKAGE
(TOP VIEW)
A3
A4
7
6 5 4
3
2 1 44 43 42 41 40
39
8
38
VCC
A5
A6
A7
A8
GND
AF/AEA
HFA
LDCKA
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
FULLA
UNCKB
EMPTYB
DAF
RSTA
RSTB
DBF
EMPTYA
UNCKA
FULLB
LDCKB
30
17
29
18 19 20 21 22 23 24 25 26 27 28
B2
B3
B4
VCC
B5
B6
B7
B8
GND
AF/AEB
HFB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
A2
A1
A0
GND
GND
GBA
SBA
SAB
GAB
GND
GND
B0
B1
B2
VCC
VCC
PAG OR PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VCC
A3
A4
VCC
GND
GND
A5
A6
VCC
VCC
A7
A8
GND
GND
AF/AEA
HFA
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
NC
LDCKA
FULLA
UNCKB
EMPTYB
DAF
RSTA
NC
RSTB
DBF
EMPTYA
NC
UNCKA
FULLB
LDCKB
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC – No internal connection
2
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• DALLAS, TEXAS 75265
NC
VCC
B3
B4
GND
GND
VCC
B5
B6
VCC
B7
B8
GND
GND
AF/AEB
HFB
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
logic symbol†
SAB
SBA
GAB
GBA
RSTA
DAF
LDCKA
UNCKA
FULLA
EMPTYA
AF/AEA
HFA
A0
A1
A2
A3
A4
A5
A6
A7
A8
44
1
43
2
22
21
Φ
FIFO
1024 × 9 × 2
SN74ACT2235
MODE
1
0
EN1
EN2
Reset A
RESET B
DEF A FLAG
17
LDCKA
DEF B FLAG
25
15
16
4
24
28
LDCKB
19
26
18
23
UNCKA
FULLA
UNCKB
FULL B
EMPTYA
EMPTYB
ALMOST-FULL/
ALMOST-FULL/
ALMOST-EMPTY A ALMOST-EMPTY A
HALF-FULL A
HALF-FULL B
0
0
27
20
30
29
41
5
40
6
39
7
38
A Data
8
B Data
37
10
35
11
34
12
33
13
8
8
32
RSTB
DBF
LDCKB
UNCKB
FULLB
EMPTYB
AF/AEB
HFB
B0
B1
B2
B3
B4
B5
B6
B7
B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
logic diagram (positive logic)
SAB
SBA
Φ
FIFO B
1024 × 9
HFB
RSTB
AF/AEB
DBF
EMPTYB
FULLB
UNCKB
LDCKB
Q
GBA
D
B0
One of Nine Channels
To Other Channels
GAB
Φ
FIFO A
1024 × 9
RSTA
DAF
HFA
AF/AEA
EMPTYA
UNCKA
FULLA
LDCKA
A0
D
Q
One of Nine Channels
To Other Channels
4
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• DALLAS, TEXAS 75265
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
Terminal Functions
TERMINAL†
NAME
NO.
I/O
DESCRIPTION
AF/AEA
AF/AEB
15
30
O
Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the
almost-full/almost-empty offset value for FIFO A (X). AF/AEA is high when FIFO A contains X or fewer words
or 1024 – X words. AF/AEA is low when FIFO A contains between (X + 1) or (1023 – X) words. The operation
of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B.
A0–A8
4–8,
10–13
I/O
A-data inputs and outputs
B0–B8
32–35,
37–41
I/O
B-data inputs and outputs
DAF
DBF
21
24
I
Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0–A8 as the
almost-full/almost-empty offset value for FIFO A (X). The high-to-low transition of DBF stores the binary value
of B0–B8 as the almost-full/almost-empty offset value for FIFO B (Y).
EMPTYA
EMPTYB
25
20
O
Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high when
they are not empty.
FULLA
FULLB
18
27
O
Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they are
not full.
HFA
HFB
16
29
O
Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more words and
low when they contain 511 or fewer words.
LDCKA
LDCKB
17
28
I
Load clocks. Data on A0–A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on B0–B8 is
written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA and LDCKB have
no effect on the data residing in memory.
GAB
GBA
43
2
I
Output enables. GAB, GBA control the transceiver functions. When GBA is low, A0–A8 are in the
high-impedance state. When GAB is low, B0–B8 are in the high-impedance state.
RSTA
RSTB
22
23
I
Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA,
EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up.
SAB
SBA
44
1
I
Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level selects
real-time data and a high level selects stored data. Eight fundamental bus-management functions can be
performed as shown in Figure 2.
UNCKA
UNCKB
26
19
I
Unload clocks. Data in FIFO A is read to B0–B8 on a low-to-high transition of UNCKA. Data in FIFO B is read
to A0–A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and UNCKB have no
effect on data residing in memory.
† Terminals listed are for the FN package.
programming procedure for AF/AEA
The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The
almost-full/almost-empty offset value for FIFO A (X) and for FIFO B (Y) is either a user-defined value or the
default values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB
is programmed in the same manner for FIFO B.
user-defined X
Take DAF from high to low. This stores A0–A8 as X.
If RSTA is not already low, take RSTA low.
With DAF held low, take RSTA high. This defines AF/AEA using X.
To retain the current offset for the next reset, keep DAF low.
default X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.Figure 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Don’t Care
ÎÎ
ÎÎ
ÎÉ
É
Î
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
LDCKA
A0–A8
Word
1
Word
2
Word
257
Word
512
Word
768
Word
1024
Don’t Care
X
UNCKA
POST OFFICE BOX 655303
Q0–Q8
Invalid
Word Word
257
2
Word 1
Word Word
258
513
Word
514
Word
768
Word
769
Word
1024
Word ‡
1024
Invalid
• DALLAS, TEXAS 75265
EMPTYA
FULLA
HFA
AF/AEA
Set Flag to
Empty + X/Full – X
Set Flag to Empty + 256/
Full – 256 (default)
Empty + 256
Full – 256
Half Full
Full – 256
Half Full
Full
† Operation of FIFO B is identical to that of FIFO A.
‡ Last valid data stays on outputs when FIFO goes empty due to a read.
†
Figure 1. Timing Diagram for FIFO A
Empty + 256
Empty
Load X into
Flag Register
(0 ≤ X ≤ 511)
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
DAF
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
6
RSTA
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
In
FIFO A
Out
Bus A
Bus B
Bus A
Bus B
FIFO B
Out
In
FIFO B
Out
In
SAB SBA GAB GBA
L
X
H
L
In
SAB SBA GAB GBA
X
X
L
L
FIFO A
Out
In
Bus A
Bus B
Bus B
FIFO B
Out
In
SAB SBA GAB GBA
X
L
L
H
SAB SBA GAB GBA
H
L
H
H
FIFO A
Out
In
Bus A
Bus B
FIFO A
Out
Bus A
Bus B
FIFO B
Out
In
FIFO B
Out
In
SAB SBA GAB GBA
H
X
H
L
In
FIFO A
Out
Bus A
FIFO B
Out
In
In
FIFO A
Out
In
SAB SBA GAB GBA
L
H
H
H
FIFO A
Out
In
FIFO A
Out
Bus A
Bus A
Bus B
Bus B
FIFO B
Out
In
FIFO B
Out
In
SAB SBA GAB GBA
X
H
L
H
SAB SBA GAB GBA
H
H
H
H
Figure 2. Bus-Management Functions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
SELECT-MODE CONTROL
OPERATION
CONTROL
SAB
SBA
A BUS
B BUS
L
L
Real-time B to A bus
Real-time A to B bus
L
H
FIFO B to A bus
Real-time A to B bus
H
L
Real-time B to A bus
FIFO A to B bus
H
H
FIFO B to A bus
FIFO A to B bus
OUTPUT-ENABLE CONTROL
CONTROL
OPERATION
GAB
GBA
A BUS
B BUS
H
H
A bus enabled
B bus enabled
L
H
A bus enabled
Isolation/input to B bus
H
L
Isolation/input to A bus
B bus enabled
L
L
Isolation/input to A bus
Isolation/input to B bus
Figure 2. Bus-Management Functions (Continued)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PAG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
ACT2235-20
8
VCC
VIH
Supply voltage
VIL
Low-level input voltage
IOH
High level output current
High-level
IOL
Low level output current
Low-level
TA
Operating free-air temperature
ACT2235-30
ACT2235-40
ACT2235-60
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
High-level input voltage
2
2
2
2
0.8
0.8
0.8
A or B ports
–8
–8
–8
–8
Status flags
–8
–8
–8
–8
A or B ports
16
16
16
16
Status flags
8
8
8
8
POST OFFICE BOX 655303
70
0
• DALLAS, TEXAS 75265
70
0
70
0
V
V
0.8
0
UNIT
70
V
mA
mA
°C
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
Flags
I/O ports
II
IOZ
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
IOH = –8 mA
IOL = 8 mA
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 16 mA
VI = VCC or 0
MIN
VCC = 5.5 V,
VI = 0,
Ci
MAX
2.4
0.5
10
One input at 3.4 V,
Other inputs at VCC or GND
f = 1 MHz
Co
VO = 0,
f = 1 MHz
† All typical values are at VCC = 5 V, TA = 25°C.
‡ ICC is tested with outputs open.
§ This is the supply current when each input is at one of the specified TTL voltage levels, rather than 0 V or VCC.
UNIT
V
0.5
VCC = 5.5 V,
VO = VCC or 0
VI = VCC – 0.2 V or 0
ICC‡
∆ICC§
TYP†
V
±5
µA
±5
µA
400
µA
1
mA
4
pF
8
pF
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 3)
’ACT2235-20
MIN
fclock
l k
Clock frequency
Pulse duration
th
Hold time
MAX
’ACT2235-40
MIN
MAX
’ACT2235-60
MIN
MAX
33
25
16.7
UNCKA or UNCKB
50
33
25
16.7
20
20
25
25
LDCKA or LDCKB low
8
10
14
20
LDCKA or LDCKB high
8
10
14
20
UNCKA or UNCKB low
8
10
14
20
8
10
14
20
10
10
10
10
Data before LDCKA
or LDCKB↑
4
4
5
5
Define AF/AE:
D0–D8 before DAF or DBF↓
5
5
5
5
Define AF/AE: DAF or DBF↓
before RSTA or RSTB↑
7
7
7
7
Define AF/AE (default):
DAF or DBF high before
RSTA or RSTB↑
5
5
5
5
RSTA or RSTB inactive (high)
before LDCKA or LDCKB↑
5
5
5
5
Data after LDCKA or LDCKB↑
1
1
2
2
Define AF/AE: D0–D8
after DAF or DBF↓
0
0
0
0
Define AF/AE: DAF or DBF low
after RSTA or RSTB↑
0
0
0
0
Define AF/AE (default):
DAF or DBF high after
RSTA or RSTB↑
0
0
0
0
DAF or DBF high
Setup time
MIN
50
UNCKA or UNCKB high
tsu
’ACT2235-30
LDCKA or LDCKB
RSTA or RSTB low
tw
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
9
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
fmax
FROM
(INPUT)
tPLH
50
33
25
16.7
50
33
25
16.7
MAX
UNIT
MHz
22
8
24
8
26
25
12
25
12
35
12
45
4
15
4
15
4
17
4
19
EMPTYA,
EMPTYB
2
17
2
17
2
19
2
21
2
18
2
18
2
20
2
22
LDCK↑,
LDCKB↑
FULLA, FULLB
4
15
4
15
4
17
4
19
UNCKA↑,
UNCKB↑
FULLA, FULLB
4
15
4
15
4
17
4
19
FULLA, FULLB
2
15
2
15
2
17
2
19
AF/AEA,
AF/AEB
2
15
2
15
2
17
2
19
HFA, HFB
2
15
2
15
2
17
2
19
4
18
4
18
4
20
4
22
1
15
1
15
1
17
1
19
1
11
1
11
1
12
1
14
1
11
1
11
1
12
1
14
2
18
2
18
2
20
2
22
2
18
2
18
2
20
2
22
2
11
2
11
2
13
2
15
ns
1
13
ns
LDCK↑,
LDCKB↑
RSTA↓, RSTB↓
RSTA↓,
↓ RSTB↓
↓
UNCKA↑,
UNCKB↑
A or B
LDCK↑,
LDCKB↑
UNCKA↑,
UNCKB↑
ten
tdis
MIN
8
RSTA↓, RSTB↓
SAB or SBA‡
tpd
MAX
22
LDCK↑,
LDCKB↑
tPHL
MIN
’ACT2235-60
LDCK
GBA or GAB
8
MAX
’ACT2235-40
UNCK
UNCKA↑,
UNCKB↑
tPHL
’ACT2235-30
MIN
UNCKA↑,
UNCKB↑
tPLH
’ACT2235-20
TYP†
MAX
MIN
LDCK↑,
LDCKB↑
tpd
d
TO
(OUTPUT)
B or A
ns
12
EMPTYA,
EMPTYB
HFA,, HFB
B or A
AF/AEA,,
AF/AEB
A or B
17
GBA or GAB
A or B
1
9
1
9
1
11
† All typical values are at VCC = 5 V, TA = 25°C.
‡ These parameters are measured with the internal output state of the storage register opposite that of the bus input.
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
10
Power dissipation capacitance per 1K bits
POST OFFICE BOX 655303
TEST CONDITIONS
Outputs enabled
Outputs disabled
• DALLAS, TEXAS 75265
CL = 50 pF,
pF
f = 5 MHz
TYP
71
57
UNIT
pF
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
7V
PARAMETER
S1
ten
500 Ω
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
tdis
tpd
500 Ω
S1
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
Open
Closed
Open
Closed
Open
Open
tw
LOAD CIRCUIT
3V
Input
0V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tsu
th
3V
Data
Input
1.5 V
1.5 V
0V
3V
Output
Control
1.5 V
tPLZ
tPZL
3V
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
0V
tPLH
1.5 V
≈3.5 V
Output
Waveform 1
S1 at 7 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
1.5 V
3V
Timing
Input
Input
1.5 V
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTE A: CL includes probe and jig capacitance.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN74ACT2235
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS148F – DECEMBER 1990 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
POWER-DISSIPATION CAPACITANCE
vs
SUPPLY VOLTAGE
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
typ + 2
VCC = 5 V
TA = 25°C
RL = 500 Ω
typ + 6
Cpd – Power Dissipation Capacitance – pF
t pd – Propagation Delay Time – ns
typ + 8
typ + 4
typ + 2
typ
typ – 2
0
50
100
150
200
250
300
typ + 1
VCC = 5 V
fi = 5 MHz
TA = 25°C
typ
typ – 1
typ – 2
typ – 3
4.5
4.6
4.9
5
Figure 4
Figure 5
POST OFFICE BOX 655303
5.1
5.2
VCC – Supply Voltage – V
CL – Load Capacitance – pF
12
4.7 4.8
• DALLAS, TEXAS 75265
5.3
5.4
5.5
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ACT2235-20FN
ACTIVE
PLCC
FN
44
26
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74ACT2235-20PAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
SN74ACT2235-20PM
OBSOLETE
LQFP
PM
64
TBD
Call TI
Call TI
Call TI
SN74ACT2235-30FN
OBSOLETE
PLCC
FN
44
SN74ACT2235-30PAG
ACTIVE
TQFP
PAG
64
SN74ACT2235-30PM
OBSOLETE
LQFP
PM
64
SN74ACT2235-40FN
ACTIVE
PLCC
FN
SN74ACT2235-40PAG
ACTIVE
TQFP
SN74ACT2235-40PM
OBSOLETE
SN74ACT2235-60FN
ACTIVE
SN74ACT2235-60PAG
ACTIVE
SN74ACT2235-60PM
OBSOLETE
Lead/Ball Finish
MSL Peak Temp (3)
TBD
Call TI
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
TBD
Call TI
44
26
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
LQFP
PM
64
TBD
Call TI
PLCC
FN
44
26
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
LQFP
PM
64
TBD
Call TI
Level-3-260C-168 HR
Call TI
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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