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SN54AHC540, SN74AHC540
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
SNx4AHC540 Octal Buffers/Drivers With 3-State Outputs
1 Features
3 Description
•
•
The SNx4AHC540 octal buffers/drivers are ideal for
driving bus lines or buffer memory address registers.
These devices feature inputs and outputs on opposite
sides of the package to facilitate printed circuit board
layout.
1
•
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA
Per JESD 17
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Device Information(1)
PART NUMBER
PACKAGE (PINS)
BODY SIZE (NOM)
SN74AHC540N
PDIP (20)
25.40 mm × 6.35 mm
SN74AHC540DB
SSOP (20)
7.50 mm × 5.30 mm
2 Applications
SN74AHC540PW
TSSOP (20)
6.50 mm × 4.40 mm
•
•
•
•
•
•
SN74AHC540DGV
TVSOP (20)
5.00 mm × 4.40 mm
SN74AHC540DW
SOIC (20)
12.80 mm × 7.50 mm
SNJ54AHC540FK
LCCC (20)
9.0 mm x 9.0 mm
SNJ54AHC540W
CFP (20)
13.72 mm x 8.13 mm
Servers
PCs and Notebooks
Network Switches
Wearable Health and Fitness Devices
Telecom Infrastructures
Electronic Points of Sale
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
OE1
OE2
A1
Y1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHC540, SN74AHC540
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
5
5
5
6
6
7
7
8
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
10.1 Layout Guidelines ................................................. 12
11 Layout................................................................... 12
11.1 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
Community Resources..........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (October 2015) to Revision M
Page
•
Updated front page Simplified Schematic diagram ............................................................................................................... 1
•
Updated Pin Out drawing diagrams to new standard ............................................................................................................ 4
•
Updated Functional Block Diagram ..................................................................................................................................... 10
•
Updated Outputs in Function Table of Device Functional Modes section .......................................................................... 10
Changes from Revision K (September 2014) to Revision L
Page
•
Added junction temperature .................................................................................................................................................. 5
•
Updated the Handling Ratings table to an ESD Ratings table and move the storage temperature to the Absolute
Maximum Ratings table ......................................................................................................................................................... 5
•
Corrected the Overview to state that the outputs provide non-inverted data ...................................................................... 10
•
Added Community Resources ............................................................................................................................................. 13
Changes from Revision J (July 2003) to Revision K
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table ........................................................................................................................................ 1
•
Added Military Disclaimer to Features list .............................................................................................................................. 1
•
Added Applications ................................................................................................................................................................. 1
•
Updated the simplified schematic........................................................................................................................................... 1
•
Added Pin Functions table...................................................................................................................................................... 4
•
Added Handling Ratings table ................................................................................................................................................ 5
•
Extended operating temperature range to 125°C................................................................................................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 6
•
Added –40°C to 125°C range for SN74AHC540 in Electrical Characteristics table............................................................... 6
2
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Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
SN54AHC540, SN74AHC540
www.ti.com
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
•
Added TA = –40°C to 125°C for SN74AHC540 in both Switching Characteristics tables. ..................................................... 7
•
Added Typical Characteristics. ............................................................................................................................................... 8
•
Added Detailed Description section...................................................................................................................................... 10
•
Added Application and Implementation section.................................................................................................................... 11
•
Added Power Supply Recommendations and Layout sections............................................................................................ 12
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
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3
SN54AHC540, SN74AHC540
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
www.ti.com
5 Pin Configuration and Functions
SN54AHC540: J or W Package; SN74AHC540: DB, DGV, DW,
N, NS, or PW Package
SN54AHC540: 20-Pin CDIP or CFP; SN74AHC540: 20-Pin
SSOP, TVSOP, SOIC, PDIP, PDIP, or TSSOP
Top View
Y1
A3
4
17
Y2
A4
5
16
Y3
A5
6
15
Y4
A6
7
14
A7
8
A8
6
16
Y3
Y5
A6
7
15
Y4
13
Y6
A7
8
14
Y5
9
12
Y7
10
11
Y8
Not to scale
13
A5
Y6
Y2
12
17
Y7
5
11
A4
Y8
Y1
10
18
GND
4
9
A3
A8
GND
OE2
18
19
3
VCC
A2
20
OE2
OE1
19
1
2
A1
VCC
2
20
A2
1
3
OE1
A1
SN54AHC540: FK Package
20-Pin LCCC
Top View
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
OE1
I
Output Enable 1
2
A1
I
A1 Input
3
A2
I
A2 Input
4
A3
I
A3 Input
5
A4
I
A4 Input
6
A5
I
A5 Input
7
A6
I
A6 Input
8
A7
I
A7 Input
9
A8
I
A8 Input
10
GND
—
Ground
11
Y8
O
Y8 Output
12
Y7
O
Y7 Output
13
Y6
O
Y6 Output
14
Y5
O
Y5 Output
15
Y4
O
Y4 Output
16
Y3
O
Y3 Output
17
Y2
O
Y2 Output
18
Y1
O
Y1 Output
19
OE2
I
Output Enable 2
20
VCC
—
4
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Power Pin
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
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SCLS260M – DECEMBER 1995 – REVISED MAY 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage range
–0.5
7
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
1000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHC540
VCC
Supply voltage
VIH
High-level input voltage
Low-level Input voltage
MAX
MIN
MAX
2
5.5
2
5.5
VCC = 2 V
1.5
VCC = 3 V
2.1
2.1
3.85
3.85
VCC = 5.5 V
VIL
Input voltage
VO
Output voltage
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
0.5
VCC = 3 V
0.9
0.9
1.65
1.65
0.5
0
5.5
0
5.5
0
VCC
0
V
V
VCC
V
–50
–50
µA
VCC = 3.3 V ± 0.3 V
–4
–4
VCC = 5 V ± 0.5 V
–8
–8
VCC = 2 V
VCC = 2 V
IOH
UNIT
1.5
VCC = 2 V
VCC = 5.5 V
VI
SN74AHC540
MIN
50
50
VCC = 3.3 V ± 0.3 V
4
4
VCC = 5 V ± 0.5 V
8
8
100
100
20
20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
–55
125
–40
mA
µA
mA
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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SN54AHC540, SN74AHC540
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
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6.4 Thermal Information
SN74AHC540
THERMAL METRIC
RθJA
(1)
DGV
(TVSOP)
DW
(SOIC)
N
(PDIP)
NS
(PDIP)
PW
(TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
20 PINS
UNIT
99.9
119.2
83.0
54.9
80.4
105.4
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
61.7
34.5
48.9
41.7
46.9
39.5
°C/W
RθJB
Junction-to-board thermal resistance
55.2
60.7
50.5
35.8
47.9
56.4
°C/W
ψJT
Junction-to-top characterization
parameter
22.6
1.2
21.1
27.9
19.9
3.1
°C/W
ψJB
Junction-to-board characterization
parameter
54.8
60.0
50.1
35.7
47.5
55.8
°C/W
(1)
Junction-to-ambient thermal resistance
DB
(SSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
IOH = –50 µA
MIN
MAX
MIN
MAX
–40°C to 125°C
SN74AHC540
MIN
2
1.9
1.9
1.9
2.9
3V
2.9
3
2.9
2.9
4.4
4.5
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
3.8
UNIT
MAX
V
3.8
2V
0.1
0.1
0.1
0.1
3V
0.1
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
IOH = 4 mA
3V
0.36
0.5
0.44
0.44
IOH = 8 mA
4.5 V
0.36
0.5
0.44
0.44
±0.1
±1 (1)
±1
±1
µA
IOL = 50 µA
VOL
6
1.9
TYP MAX
SN74AHC540
4.5 V
VOH
(1)
(2)
2V
SN54AHC540
V
II
VI = 5.5 V or GND
0 V to 5.5
V
IOZ (2)
VO = VCC or GND
VI (OE) = VIL or VIH
5.5 V
±0.2
5
±2.5
±2.5
±2.5
µA
ICC
VI = VCC or
GND
5.5 V
4
40
40
40
µA
Ci
VI = VCC or GND
5V
2
CO
VO = VCC or GND
5V
4
IO =
0
10
10
pF
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
For input and output pins, IOZ includes the input leakage current.
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SCLS260M – DECEMBER 1995 – REVISED MAY 2016
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
tsk(o)
(1)
(2)
TA = 25°C
SN54AHC540
SN74AHC540
TA = –40°C to 125°C
SN74AHC540
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
4.8 (1)
7 (1)
1 (1)
8.5 (1)
1
8.5
1
9.5
4.8
(1)
7
(1)
1
(1)
8.5 (1)
1
8.5
1
9.5
6.8
(1)
10.5
(1)
1
(1)
(1)
1
12.5
1
13.5
6.8 (1)
10.5 (1)
1 (1)
12.5
12.5 (1)
1
12.5
1
13.5
6.8 (1)
10.5 (1)
1 (1)
12.5 (1)
1
12.5
1
13.5
6.8 (1)
10.5 (1)
1 (1)
12.5 (1)
1
12.5
1
13.5
7.3
10.5
1
12
1
12
1
13.5
7.3
10.5
1
12
1
12
1
13.5
8
14
1
16
1
16
1
17
8
14
1
16
1
16
1
17
8
15.4
1
17.5
1
17.5
1
18.5
8
15.4
1
17.5
1
17.5
1
18.5
1.5 (2)
CL = 50 pF
ns
ns
ns
ns
ns
ns
1.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
(1)
(2)
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
CL = 50 pF
TA = 25°C
SN54AHC540
SN74AHC540
TA = –40°C to 125°C
SN74AHC540
UNIT
TYP
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.7 (1)
5 (1)
1 (1)
6 (1)
1
6
1
7
3.7
(1)
5
(1)
1
(1)
6 (1)
1
6
1
7
4.7
(1)
7.2
(1)
1
(1)
(1)
1
8.5
1
9.5
4.7 (1)
7.2 (1)
1 (1)
8.5
8.5 (1)
1
8.5
1
9.5
4.5 (1)
6.8 (1)
1 (1)
8 (1)
1
8
1
8.5
4.5 (1)
6.8 (1)
1 (1)
8 (1)
1
8
1
8.5
5.2
7
1
8
1
8
1
9
5.2
7
1
8
1
8
1
9
6.2
9.2
1
10.5
1
10.5
1
11.5
6.2
9.2
1
10.5
1
10.5
1
11.5
6
8.8
1
10
1
10
1
10.5
6
8.8
1
10
1
10
1
10.5
1 (2)
1
ns
ns
ns
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
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SN54AHC540, SN74AHC540
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
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6.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHC540
PARAMETER
MIN
UNIT
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
VIH(D)
High-level dynamic input voltage
3.5
VIL(D)
Low-level dynamic input voltage
(1)
V
V
1.5
V
Characteristics are for surface-mount packages only.
6.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
TYP
f = 1 MHz
UNIT
12
pF
6.10 Typical Characteristics
5
9
TPD in ns
8
4
7
TPD (ns)
TPD (ns)
6
5
4
3
2
3
2
1
1
TPD in ns
0
0
1
2
3
4
VCC (V)
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6
0
-100
-50
D001
Figure 1. TPD vs VCC
8
5
0
50
Temperature qC
100
150
D001
Figure 2. TPD vs Temperature
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SCLS260M – DECEMBER 1995 – REVISED MAY 2016
7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SNx4AHC540 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These
devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a two-input AND gate with active-low inputs. If either output-enable (OE1 or OE2)
input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data when
they are not in the high-impedance state.
OE should be tied to VCC through a pullup resistor to ensure the high-impedance state during power up or power
down. The minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
OE1
OE2
A1
Y1
To Seven Other Channels
8.3 Feature Description
SNx4AHC540 device has a wide operating voltage range and operates from 2 V to 5.5 V. The inputs accept
voltages up to 5.5 V, which allows for down translation. Slow input edges and low drive will minimize output
overshoots and undershoots.
8.4 Device Functional Modes
Table 1 shows the device functions for each buffer and driver.
Table 1. Function Table (Each Buffer/Driver)
INPUTS
10
A
OUTPUT
Y
L
L
H
L
H
L
H
X
X
Hi-Z
X
H
X
Hi-Z
OE1
OE2
L
L
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Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
SN54AHC540, SN74AHC540
www.ti.com
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHC540 is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs accept voltages up to 5.5 V, which allows down translation to the VCC level. Figure 5
shows how the slower edges can reduce ringing on the output compared to higher drive parts like AC.
9.2 Typical Application
Regulated 5.0 V
OE
VCC
A1
Y1
A8
Y8
µC or
System Logic
5-V µC
System logic
LEDs
GND
Figure 4. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
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11
SN54AHC540, SN74AHC540
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
www.ti.com
Typical Application (continued)
9.2.3 Application Curve
Figure 5. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC terminals
then 0.01 μF or 0.022 μF is recommended for each power terminal. It is acceptable to parallel multiple bypass
caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass
capacitor should be installed as close to the power terminal as possible for best results.
10.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. Specified in the Figure 6 are
rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected
to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused
input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more
sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver
has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the
input section of the I/Os so they also cannot float when disabled.
11 Layout
11.1 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
12
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Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
SN54AHC540, SN74AHC540
www.ti.com
SCLS260M – DECEMBER 1995 – REVISED MAY 2016
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHC540
Click here
Click here
Click here
Click here
Click here
SN74AHC540
Click here
Click here
Click here
Click here
Click here
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1995–2016, Texas Instruments Incorporated
Product Folder Links: SN54AHC540 SN74AHC540
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9685001Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629685001Q2A
SNJ54AHC
540FK
5962-9685001QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9685001QS
A
SNJ54AHC540W
SN74AHC540DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA540
Samples
SN74AHC540DGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA540
Samples
SN74AHC540DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC540
Samples
SN74AHC540DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC540
Samples
SN74AHC540N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC540N
Samples
SN74AHC540PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA540
Samples
SN74AHC540PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA540
Samples
SNJ54AHC540FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629685001Q2A
SNJ54AHC
540FK
SNJ54AHC540W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9685001QS
A
SNJ54AHC540W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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