SN74AHC574PWR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 SNx4AHC574 Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 1 Features 3 Description • • • The SNx4AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 • • Operating Range 2-V to 5.5-V VCC 3-State Outputs Drive Bus Lines Directly Latch-Up Performance Exceeds 250 mA Per JESD 17 On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model – 200-V Machine Model – 1000-V Charged-Device Model Device Information(1) PART NUMBER SNx4AHC574 2 Applications • • • • • • • • PACKAGE BODY SIZE (NOM) SSOP (20) 7.50 mm × 5.30 mm TVSOP (20) 5.00 mm × 4.40 mm SOIC (20) 12.80 mm × 7.50 mm PDIP (20) 25.40 mm × 6.35 mm TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Smart Grids TVs Set Top Boxes Audio Servers Surveillance Cameras Network Switches Infotainment 4 Simplified Schematic OE CLK C1 1Q 1D 1D To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 4 4 4 5 5 5 6 6 7 7 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements, VCC = 3.3 V ± 0.3 V .............. Timing Requirements, VCC = 5 V ± 0.5 V ................. Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ Switching Characteristics, VCC = 5 V ± 0.5 V ........... Noise Characteristics .............................................. Operating Characteristics........................................ Typical Characteristics ............................................ 8 9 Parameter Measurement Information .................. 9 Detailed Description ............................................ 10 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 10 Application and Implementation........................ 11 10.1 Application Information.......................................... 11 10.2 Typical Application ............................................... 11 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 13 12.1 Layout Guidelines ................................................. 13 12.2 Layout Example .................................................... 13 13 Device and Documentation Support ................. 13 13.1 13.2 13.3 13.4 Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 5 Revision History Changes from Revision I (July 2003) to Revision J Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Added Military Disclaimer to Features list. ............................................................................................................................. 1 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4 2 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 SN54AHC574, SN74AHC574 www.ti.com SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 6 Pin Configuration and Functions SN54AHC574 . . . J OR W PACKAGE SN74AHC574 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 3D 4D 5D 6D 7D 1Q 2D 1D OE VCC VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q OE 1D 2D 3D 4D 5D 6D 7D 8D GND SN54AHC574 . . . FK PACKAGE (TOP VIEW) Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 OE I Output Enable Pin 2 1D I 1D Input 3 2D I 2D Input 4 3D I 3D Input 5 4D I 4D Input 6 5D I 5D Input 7 6D I 6D Input 8 7D I 7D Input 9 8D I 8D Input 10 GND — 11 CLK I Clock Pin 12 8Q O 8Q Output 13 7Q O 7Q Output 14 6Q O 6Q Output 15 5Q O 5Q Output 16 4Q O 4Q Output 17 3Q O 3Q Output 18 2Q O 2Q Output 19 1Q O 1Q Output 20 VCC — Power Pin Ground Pin Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 Submit Documentation Feedback 3 SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 7 UNIT V (2) –0.5 7 V –0.5 VCC + 0.5 VI Input voltage range VO Output voltage range (2) IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±75 mA 150 °C Continuous current through VCC or GND Tstg (1) (2) Storage temperature range –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1000 Machine Model (MM) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) SN54AHC574 VCC Supply voltage VIH High-level input voltage Low-level Input voltage MAX MIN MAX 2 5.5 2 5.5 VCC = 2 V 1.5 VCC = 3 V 2.1 2.1 3.85 3.85 VCC = 5.5 V VIL Input voltage VO Output voltage High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) 4 V V 0.5 VCC = 3 V 0.9 0.9 1.65 1.65 0.5 0 5.5 0 5.5 0 VCC 0 V V VCC V –50 –50 µA VCC = 3.3 V ± 0.3 V –4 –4 VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V VCC = 2 V IOH UNIT 1.5 VCC = 2 V VCC = 5.5 V VI SN74AHC574 MIN 50 50 VCC = 3.3 V ± 0.3 V 4 4 VCC = 5 V ± 0.5 V 8 8 100 100 20 20 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –55 125 –40 125 mA µA mA ns/V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 SN54AHC574, SN74AHC574 www.ti.com SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 7.4 Thermal Information SN74AHC574 THERMAL METRIC (1) DB DGV DW N NS PW UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 97.9 117.2 79.4 53.3 79.2 103.3 RθJC(top) Junction-to-case (top) thermal resistance 59.6 32.7 45.7 40.0 45.7 37.8 RθJB Junction-to-board thermal resistance 53.1 58.7 46.9 34.2 46.8 54.3 ψJT Junction-to-top characterization parameter 21.3 1.15 18.7 26.4 19.3 2.9 ψJB Junction-to-board characterization parameter 52.7 58.0 46.5 34.1 46.4 53.8 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN74AHC574 –40°C to 85°C MIN MAX MIN –40°C to 125°C TYP 2V 1.9 2 1.9 1.9 1.9 3V 2.9 3 2.9 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 4.4 IOH = –4 mA 3V 2.58 2.48 2.48 2.48 IOH = –8 mA 4.5 V 3.94 3.8 3.8 VOH MAX –40°C to 85°C MIN IOH = –50 µA MAX MIN UNIT MAX V 3.8 2V 0.1 0.1 0.1 0.1 3V 0.1 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 0.1 3V 0.36 0.5 0.44 0.44 IOH = 8 mA 4.5 V 0.36 0.5 0.44 0.44 II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 (1) ±1 ±1 µA IOZ (2) VO = VCC or GND VI (OE) = VIL or VIH 5.5 V ±0.25 ±2.5 ±2.5 ±2.5 µA 4 40 40 40 µA 10 10 pF IOL = 50 µA VOL IOH = 4 mA (1) (2) SN54AHC574 TA = 25°C VCC ICC VI = VCC or GND, Ci VI = VCC or GND IO = 0 5.5 V 5V 3 CO VO = VCC or GND 5V 3 ±1 10 V pF On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. For input and output pins, IOZ includes the input leakage current. 7.6 Timing Requirements, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) TA = 25°C PARAMETER MIN tw Pulse duration, CLK high or low tsu th MAX SN54AHC574 –40°C to 85°C MIN MAX SN74AHC574 –40°C to 85°C MIN MAX –40°C to 125°C MIN UNIT MAX 5 5 5 5.5 ns Setup time, data before CLK↑ 3.5 3.5 3.5 4 ns Hold time, data after CLK↑ 1.5 1.5 1.5 2 ns Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 Submit Documentation Feedback 5 SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 www.ti.com 7.7 Timing Requirements, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54AHC574 TA = 25°C PARAMETER MIN SN74AHC574 –40°C to 85°C MAX MIN –40°C to 85°C MAX MIN –40°C to 125°C MAX MIN UNIT MAX tw Pulse duration, CLK high or low 5 5 5 5.5 ns tsu Setup time, data before CLK↑ 3 3 3 3.5 ns th Hold time, data after CLK↑ 1.5 1.5 1.5 2 ns 7.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ (1) (2) 6 –40°C to 85°C CL = 15 pF 80 (1) 125 (1) 65 (1) 65 65 CL = 50 pF 50 75 45 45 45 CL = 15 pF OE Q CL = 15 pF OE Q CL = 15 pF CLK Q CL = 50 pF OE Q CL = 50 pF OE Q CL = 50 pF CL = 50 pF MIN MAX MIN MAX –40°C to 125°C TYP Q MAX SN74AHC574 –40°C to 85°C MIN CLK tsk(o) SN54AHC574 TA = 25°C LOAD CAPACITANCE MIN MHz 8.5 (1) 13.2 (1) 1 (1) 15.5 (1) 1 15.5 1 17 8.5 (1) 13.2 (1) 1 (1) 15.5 (1) 1 15.5 1 17 8.2 (1) 12.8 (1) 1 (1) 15 (1) 1 15 1 16 8.2 (1) 12.8 (1) 1 (1) 15 (1) 1 15 1 16 8.5 (1) 13 (1) 1 (1) 15 (1) 1 15 1 16 (1) (1) (1) (1) 1 15 1 16 8.5 13 1 15 11 16.7 1 19 1 19 1 20.5 11 16.7 1 19 1 19 1 20.5 10.7 16.3 1 18.5 1 18.5 1 19.5 10.7 16.3 1 18.5 1 18.5 1 19.5 11 15 1 17 1 17 1 18 11 15 1 17 1 17 1 18 1.5 (2) UNIT MAX 1.5 ns ns ns ns ns ns ns On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 SN54AHC574, SN74AHC574 www.ti.com SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 7.9 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ (1) (2) –40°C to 85°C CL = 15 pF 130 (1) 180 (1) 110 (1) 110 110 CL = 50 pF 85 115 75 75 75 CL = 15 pF OE Q CL = 15 pF OE Q CL = 15 pF CLK Q CL = 50 pF OE Q CL = 50 pF OE Q CL = 50 pF CL = 50 pF MIN MAX MIN –40°C to 125°C TYP Q MAX SN74AHC574 –40°C to 85°C MIN CLK tsk(o) SN54AHC574 TA = 25°C LOAD CAPACITANCE MAX MIN UNIT MAX MHz 5.6 (1) 8.6 (1) 1 (1) 10 (1) 1 10 1 11 5.6 (1) 8.6 (1) 1 (1) 10 (1) 1 10 1 11 5.9 (1) 9 (1) 1 (1) 10.5 (1) 1 10.5 1 11.5 5.9 (1) 9 (1) 1 (1) 10.5 (1) 1 10.5 1 11.5 5.5 (1) 9 (1) 1 (1) 10.5 (1) 1 10.5 1 11.5 5.5 (1) 9 (1) 1 (1) 10.5 (1) 1 10.5 1 11.5 7.1 10.6 1 12 1 12 1 13 7.1 10.6 1 12 1 12 1 13 7.4 11 1 12.5 1 12.5 1 13.5 7.4 11 1 12.5 1 12.5 1 13.5 7.1 10.1 1 11.5 1 11.5 1 12.5 7.1 10.1 1 11.5 1 11.5 1 12.5 1 (2) 1 ns ns ns ns ns ns 1 ns On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. 7.10 Noise Characteristics VCC = 5 V, CL = 50 pF, TA = 25°C (1) SN74AHC574 PARAMETER MIN UNIT MAX VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL –0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.2 VIH(D) High-level dynamic input voltage 3.5 VIL(D) Low-level dynamic input voltage (1) V V 1.5 V Characteristics are for surface-mount packages only. 7.11 Operating Characteristics VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 f = 1 MHz TYP UNIT 28 Submit Documentation Feedback pF 7 SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 www.ti.com 7.12 Typical Characteristics 7 8 7 6 6 TPD (ns) TPD (ns) 5 4 5 4 3 3 2 2 1 TPD in ns 1 -100 0 50 Temperature (qC) 100 Submit Documentation Feedback 150 0 1 2 D001 Figure 1. TPD vs Temperature 8 TPD in ns 0 -50 3 VCC 4 5 6 D001 Figure 2. TPD vs VCC at 25°C Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 SN54AHC574, SN74AHC574 www.ti.com SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 8 Parameter Measurement Information From Output Under Test Test Point From Output Under Test RL = 1 kΩ S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC 50% VCC VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 Submit Documentation Feedback 9 SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 www.ti.com 9 Detailed Description 9.1 Overview The SNx4AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs. The states of the Q outputs are not predictable until the first valid clock. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pull-up components. 9.2 Functional Block Diagram OE CLK C1 1Q 1D 1D To Seven Other Channels 9.3 Feature Description • • 5.5-V tolerant input allows for 5 V to 3.3 V voltage translation Slow edges reduce output ringing 9.4 Device Functional Modes Table 1. Function Table (Each Flip-Flop) INPUTS 10 OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 SN54AHC574, SN74AHC574 www.ti.com SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information SN74AHC574 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation 10.2 Typical Application 5-V regulated 3.3-V or 5-V regulated OE VCC CLK 1D 1Q µC or System Logic 8D 8Q µC System Logic LEDs GND Figure 4. Typical Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table. – For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table. 2. Recommend Output Conditions – Load currents should not exceed 25 mA per output and 75 mA total for the part. – Outputs should not be pulled above VCC. Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 Submit Documentation Feedback 11 SN54AHC574, SN74AHC574 SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 www.ti.com Typical Application (continued) 10.2.3 Application Curves Figure 5. Switching Charactersitics Comparison 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Submit Documentation Feedback Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 SN54AHC574, SN74AHC574 www.ti.com SCLS244J – OCTOBER 1995 – REVISED DECEMBER 2014 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 12.2 Layout Example Vcc Input Unused Input Output Unused Input Output Input Figure 6. Layout Diagram 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 1995–2014, Texas Instruments Incorporated Product Folder Links: SN54AHC574 SN74AHC574 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9685401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629685401Q2A SNJ54AHC 574FK 5962-9685401QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9685401QR A SNJ54AHC574J 5962-9685401QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9685401QS A SNJ54AHC574W SN74AHC574DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 SN74AHC574DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 SN74AHC574DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 SN74AHC574DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 SN74AHC574DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 SN74AHC574DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 SN74AHC574N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 SN74AHC574N SN74AHC574NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHC574 SN74AHC574PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 SN74AHC574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 SN74AHC574PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 HA574 SNJ54AHC574FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629685401Q2A SNJ54AHC Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 574FK SNJ54AHC574J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9685401QR A SNJ54AHC574J SNJ54AHC574W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9685401QS A SNJ54AHC574W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of