SN74ALS563BNSR




    
  
 
 
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004 D 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information These 8-bit D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the complements of data (D) inputs. When LE is taken low, the outputs are latched at the inverse of the levels set up at the D inputs. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 2D 1D A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components. 3D 4D 5D 6D 7D 3 1Q SN54ALS563B . . . FK PACKAGE (TOP VIEW) OE VCC D SN54ALS563B . . . J OR W PACKAGE SN74ALS563B . . . DW, N, OR NS PACKAGE (TOP VIEW) 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D GND LE 8Q 7Q OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. 2Q 3Q 4Q 5Q 6Q ORDERING INFORMATION PDIP − N 0°C to 70°C −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING Tube of 20 SN74ALS563BN Tube of 25 SN74ALS563BDW Reel of 2000 SN74ALS563BDWR SOP − NS Reel of 2000 SN74ALS563BNSR ALS563B CDIP − J Tube of 20 SNJ54ALS563BJ SNJ54ALS563BJ CFP − W Tube of 85 SNJ54ALS563BW SNJ54ALS563BW LCCC − FK Tube of 55 SNJ54ALS563BFK SOIC − DW SN74ALS563BN ALS563B SNJ54ALS563BFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated    ! " #$%! "  &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%"  %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 



    
  
 
 
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H L L H L H L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θJA (see Notes 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



    
  
 
 
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004 recommended operating conditions (see Note 3) SN54ALS563B SN74ALS563B MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current −1 −2.6 mA IOL tw Low-level output current 12 24 mA Pulse duration, LE high 15 15 ns tsu th Setup time, data before LE↓ 20 10 ns Hold time, data after LE↓ 12 10 ns High-level input voltage 2 2 V V TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = − 18 mA IOH = − 0.4 mA VCC = 4.5 V IOH = − 1 mA IOH = − 2.6 mA VOL VCC = 4.5 V IOL = 12 mA IOL = 24 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH ICC VCC = 5.5 V SN54ALS563B TYP† MAX MIN SN74ALS563B TYP† MAX MIN −1.2 VCC − 2 2.4 −1.2 UNIT V VCC − 2 3.3 V 2.4 0.25 −20 0.4 3.2 0.25 0.4 0.35 0.5 V 20 20 µA −20 −20 µA 0.1 0.1 mA 20 20 µA −0.1 −0.1 mA −112 mA −112 −30 Outputs high 10 17 10 17 Outputs low 16 26 16 26 mA Outputs disabled 17 29 17 29 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 



    
  
 
 
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 4.5 V to 5.5 V CL = 50 pF R1 = 500 Ω R2 = 500 Ω TA = MIN to MAX† SN54ALS563B SN74ALS563B MIN MAX MIN MAX 3 26 3 18 3 15 3 14 8 29 6 22 4 22 6 21 4 25 3 18 4 21 4 18 2 12 1 10 3 22 1 15 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns 



    
  
 
 
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ tPHZ 1.3 V 1.3 V 0.3 V tPHL [3.5 V tPLH VOL 0.3 V VOH 1.3 V 3.5 V Input 1.3 V tPZH Waveform 2 S1 Open (see Note B) 1.3 V 0.3 V 90 V VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 5962-8870001RA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8870001RA SNJ54ALS563BJ SN74ALS563BDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS563B SN74ALS563BN ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type 0 to 70 SN74ALS563BN SN74ALS563BNSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS563B SN74ALS563BNSRG4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ALS563B SNJ54ALS563BJ ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8870001RA SNJ54ALS563BJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of