SN74ALVC3631-10PQ

SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Synchronous Read-Retransmit Capability Mailbox Register in Each Direction Programmable Almost-Full (AF) and Almost-Empty (AE) Flags Microprocessor Interface Control Logic Input-Ready and AF Flags Synchronized by CLKA D D D D D D Output-Ready and AE Flags Synchronized by CLKB Low-Power 0.8-µm Advanced CMOS Technology Supports Clock Frequencies up to 100 MHz Fast Access Times of 6.5 ns Pin-to-Pin Compatible With 5-V Operating SN74ACT3631, SN74ACT3641, and SN74ACT3651 Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages description The SN74ALVC3631, SN74ALVC3641, and SN74ALVC3651 are high-speed, low-power, CMOS, synchronous FIFO memories that support clock frequencies up to 100 MHz and have read access times as fast as 6.5 ns. The 512 × 36, 1024 × 36, and 2048 × 36 dual-port SRAM FIFOs buffer data from port A to port B. The FIFO memories have retransmit capability, which allows previously read data to be accessed again. The FIFOs have flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion also is possible in word depth. The SN74ALVC3631/41/51 are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The input-ready (IR) flag and almost-full (AF) flag of the FIFOs are two-stage, synchronized to CLKA. The output-ready (OR) flag and almost-empty (AE) flag of the FIFOs are two-stage, synchronized to CLKB. Offset values for AF and AE are programmed from port A or through a serial input. The SN74ALVC3631/41/51 are characterized for operation from 0°C to 70°C. For more information on this device family, see the following application reports: D D D D D D D FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering (literature number SCAA009) FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Metastability Performance of Clocked FIFOs (literature number SCZA004) FIFO Architecture, Functions, and Applications (literature number SCAA042) Optimizing DSP-Based Digital Filters With Application-Specific FIFOs (literature number SCAA021) FIFO Memories: Surface-Mount Packages for PCMCIA Applications (literature number SDMA001A) Interfacing TI Clocked FIFOs with TI Floating-Point DSPs (literature number SCAA005A) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B7 B8 B9 B10 B11 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 GND CLKA ENA W/RA CSA IR OR VCC AF AE VCC MBF2 MBA RST GND FS0/SD FS1/SEN RTM RFM VCC NC MBB GND MBF1 GND CSB W/RB ENB CLKB VCC PCB PACKAGE (TOP VIEW) B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 NC NC VCC CLKB ENB W/RB CSB GND MBF1 GND MBB NC VCC RFM RTM FS1/SEN FS0/SD GND RST MBA MBF2 VCC AE AF VCC OR IR CSA W/RA ENA CLKA GND NC PQ PACKAGE† (TOP VIEW) 17 16 15 14 13 12 11 10 9 NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 8 7 6 5 4 3 2 18 1 132 130 128 126 124 122 120 118 129 121 119 131 127 125 123 117 116 19 115 20 114 21 113 22 112 23 111 24 110 25 109 26 108 27 107 28 106 29 105 30 104 31 103 32 102 33 101 34 100 35 99 36 98 37 97 38 96 39 95 40 94 41 93 42 92 43 91 44 90 45 89 46 88 47 87 48 86 49 85 50 84 NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC – No internal connection † Uses Yamaichi socket IC51-1324-828 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 functional block diagram MBF1 36 Write Pointer Read Pointer Output Register Reset Logic 512 × 36 or 1024 × 36 or 2048 × 36† SRAM Sync Retransmit Logic RST Port-A Control Logic Input Register CLKA CSA W/RA ENA MBA Mail1 Register RTM RFM A0–A35 B0–B35 IR AF Status-Flag Logic FS0/SD FS1/SEN Flag-Offset Register Port-B Control Logic 10 Mail2 Register MBF2 † 512 × 36 for the SN74ALVC3631, 1024 × 36 for the SN74ALVC3641, and 2048 × 36 for the SN74ALVC3651 4 OR AE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLKB CSB W/RB ENB MBB SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 Terminal Functions TERMINAL NAME I/O A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A. AE O Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less than or equal to the value in the almost-empty offset register (X). AF O Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO is less than or equal to the value in the almost-full offset register (Y). B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B. DESCRIPTION CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA. CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB. CSA I Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0–A35 outputs are in the high-impedance state when CSA is high. CSB I Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0–B35 outputs are in the high-impedance state when CSB is high. ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. Flag-offset select 1/serial enable, flag-offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used for flag-offset-register programming. During a device reset, FS1/SEN and FS0/SD select the flag-offset programming method. Three offset-register programming methods are available: automatically load one of two preset values, parallel load from port A, and serial load. FS1/SEN, FS0/SD I IR O Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset. MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. MBB I Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO data for output. MBF1 O Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by a reset. MBF2 O Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by a reset. OR O Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory. RFM I Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset the read pointer to the beginning retransmit location and output the first selected retransmit data. RST I Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection. RTM I Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO out of retransmit mode. When serial load is selected for flag-offset-register programming, FS1/SEN is used as an enable synchronous to the low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into the X-and Y-offset registers. The number of bit writes required to program the offset registers is 22. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION W/RA I Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is low. detailed description reset The SN74ALVC3631/41/51 are reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset initializes the memory-read and-write pointers and forces the IR flag low, the OR flag high, the AE flag low, and the AF flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO is reset, IR is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. almost-empty flag and almost-full flag offset programming Two registers in the SN74ALVC3631/41/51 are used to hold the offset values for the AE and AF flags. The AE flag offset register is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the offset registers, parallel load from port A, or serial load. The offset-register-programming mode is chosen by the flag select (FS1, FS0) inputs during a low-to-high transition on RST (see Table 1). Table 1. Flag Programming FS1 FS0 RST X AND Y REGISTERS† H H ↑ Serial load H L ↑ 64 L H ↑ 8 L L ↑ Parallel load from port A † X register holds the offset for AE; Y register holds the offset for AF. preset values If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of an RST low-to-high transition according to Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA. parallel load from port A To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA. The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X. Each offset register of the SN74ALVC3631/41/51 uses port-A inputs (A10–A0). The highest number input is used as the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to 508 (SN74ALVC3631), 1 to 1020 (SN74ALVC3641), and 1 to 2044 (SN74ALVC3651). After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 serial load To program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN high during the low-to-high transition of RST. After this reset is complete, the X-and Y-register values are loaded bitwise through FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Eighteen (SN74ALVC3631), twenty (SN74ALVC3641), and twenty-two (SN74ALVC3651) bit writes are needed to complete the programming. The first bit write stores the most-significant bit of the Y register and the last bit write stores the least-significant bit of the X register. Each register value can be programmed from 1 to 508 (SN74ALVC3631), 1 to 1020 (SN74ALVC3641), and 1 to 2044 (SN74ALVC3651). When the option is chosen to program the offset registers serially, the IR flag remains low until all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded, to allow normal FIFO operation. FIFO write/read operation The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA and the port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the IR flag are high (see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads. Table 2. Port-A Enable Function Table CSA W/RA ENA MBA CLKA A0–A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, mail2 register None L L H L ↑ Active, mail2 register None L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high) The port-B control signals are identical to those of port A, with the exception that the port-B write/read select (W/RB) is the inverse of the W/RA. The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and W/RB. The B0–B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0–B35 outputs are active when CSB is low and W/RB is high. Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and MBB are low, W/RB, ENB, and the OR flag are high (see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 Table 3. Port-B Enable Function Table CSB W/RB ENB MBB CLKB B0–B35 OUTPUTS PORT FUNCTION H X X L L L X X In high-impedance state None X X In high-impedance state L L H L None ↑ In high-impedance state None L L H H L H L L ↑ In high-impedance state Mail2 write X Active, FIFO output register None L H H L L H L H ↑ Active, FIFO output register FIFO read X Active, mail1 register L H H H ↑ None Active, mail1 register Mail1 read (set MBF1 high) The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select can change states during the setup- and hold-time window of the cycle. When OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high transition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by CSB, W/RB, ENB, and MBB. synchronized FIFO flags Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the flag’s reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously with one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows the relationship of each flag to the number of words stored in memory. Table 4. FIFO Flag Operation NUMBER OF WORDS IN FIFO†‡ SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA OR AE AF IR 0 L L H H 1 to X (X + 1) to [D§ – (Y + 1)] H L H H H H H H (D§ – Y) to 2047 D§ H H L H H H L L † X is the almost-empty offset for AE. Y is the almost-full offset for AF. ‡ When a word is present in the FIFO output register, its previous memory location is free. § D = 512 for the SN74ALVC3631, D = 1024 for the SN74ALVC3641, and D = 2048 for the SN74ALVC3651 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 output-ready flag The OR flag of a FIFO is synchronized to CLKB. When OR is high, new data is present in the FIFO output register. When OR is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. When a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore, an OR flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles have not elapsed since the word was written. The output-ready flag of the FIFO remains low until the third low-to-high transition of CLKB occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO output register. A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tsk(1), or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 6). input-ready flag The IR flag of a FIFO is synchronized to the CLKA. When the IR flag is high, a memory location is free in the SRAM to write new data. No memory locations are free when the IR flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. When a word is read from a FIFO, its previous memory location can be written in a minimum of three cycles of CLKA; therefore, an IR flag is low if less than two cycles of CLKA have elapsed since the next memory write location has been read. The second low-to-high transition on CLKA after the read sets the IR flag high, and data can be written in the following cycle. A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tsk(1), or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 7). almost-empty flag The AE flag of a FIFO is synchronized to CLKB. The almost-empty state is defined by the contents of register X. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The AE flag is low when the FIFO contains X or fewer words and is high when the FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of fill; therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of CLKB begins the first synchronization cycle if it occurs at time tsk(2), or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 8). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 almost-full flag The AF flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The almost-full state is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The AF flag is low when the number of words in the FIFO is greater than or equal to D – Y, where D = FIFO depth (512 for SN74ALVC3631, 1024 for SN74ALVC3641, and 2048 for SN74ALVC3651). The AF flag is high when the number of words in the FIFO is less than or equal to [D – (Y + 1)]. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of CLKA are required after a FIFO read for its AF flag to reflect the new level of fill. Therefore, the AF flag of a FIFO containing [D – (Y + 1)] or less words remains low if two cycles of CLKA have not elapsed since the read that reduced the number of words in memory to [D – (Y + 1)]. An AF flag is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of words in memory to [D – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time tsk(2), or greater, after the read that reduces the number of words in memory to [D – (Y + 1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9). synchronous retransmit The synchronous-retransmit feature of the SN74ALVC3631/41/51 allows FIFO data to be read repeatedly, starting at a user-selected position. The FIFO is first put into retransmit mode (RTM) to select a beginning word and prevent ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three words can retransmit repeatedly, starting at the selected word. The FIFO can be taken out of RTM at any time without affecting normal device operation. The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the RTM input is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first retransmit data. The FIFO goes out of retransmit mode when RTM goes low (see Figure 10). When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a low-to-high transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can be done endlessly while the FIFO is in RTM. RFM must be low during the CLKB rising edge that takes the FIFO out of retransmit mode. When the FIFO is put into RTM, it operates with two read pointers. The current read pointer operates normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE flags. The shadow read pointer stores the SRAM location at the time the device is put into RTM and does not change until the device is taken out of RTM. The shadow read pointer is used by the IR and AF flags. Data writes can proceed while the FIFO is in RTM, but AF is set low by the write that stores (D – Y) words after the first retransmit word. The IR flag is set low by the Dth write after the first retransmit word. When the FIFO is in RTM and RFM is high, a rising CLKB edge loads the current read pointer with the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are needed to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit mode is the first synchronizing cycle of IR if it occurs at time tsk(1), or greater, after the rising CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of RTM is the first synchronizing cycle of AF if it occurs at time tsk(2), or greater, after the rising CLKB edge (see Figure 14). 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 mailbox registers Two 36-bit bypass registers pass command and control information between port A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is low. When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register when the MBB input is low and from the mail1 register when MBB is high. Mail2 data always is present on the port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The data in a mail register remains intact after it is read and changes only when new data is written to the register. CLKA th(RS) CLKB th(FS) tsu(RS) tsu(FS) RST ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ FS1, FS0 0,1 tpd(C-IR) tpd(C-IR) IR tpd(C-OR) OR tpd(R-F) AE tpd(R-F) AF tpd(R-F) MBF1, MBF2 Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 CLKA 4 RST tsu(FS) ÌÌÌ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th(FS) FS1, FS0 tpd(C-IR) IR ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÏÏÏÏÏÏÏÏÏÌÌÌÌÌ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏ ÏÏÏÏ ÌÌÌÌÌ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏÏÏÏÏ th(EN) tsu(EN) ENA th(D) tsu(D) A0–A35 AF Offset (Y) AE Offset (X) First Word Stored in FIFO NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles. Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A CLKA 4 RST tpd(C-IR) IR ÎÎÎ ÏÏÏÏÏÏÏÏÏ ÎÎÎ ÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏ ÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏ tsu(FS) FS1/SEN tsu(FS) FS0/SD th(SP) tsu(SEN) th(FS) th(SEN) th(SD) tsu(SD) tsu(SEN) tsu(SD) AF Offset (Y) MSB ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ th(SEN) th(SD) AE Offset (X) LSB NOTE A: It is not necessary to program offset-register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high. Figure 3. Programming the AF Flag and AE Flag Offset Values Serially 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 tc tw(CLKH) tw(CLKL) CLKA IR High CSA ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏ tsu(EN) W/RA tsu(EN) MBA tsu(EN) ENA tsu(D) A0–A35 ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÌÌÌÌÌÌ ÏÏÏÏ ÌÌÌÌÌÌ ÏÏÏÏ ÎÎÎÎÎÎ ÏÏÏÏ ÎÎÎÎÎÎ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ th(EN) tsu(EN) th(EN) th(EN) th(EN) th(EN) tsu(EN) th(EN) tsu(EN) th(D) W1 No Operation W2 Figure 4. FIFO Write Cycle tc tw(CLKH) tw(CLKL) CLKB OR High CSB W/RB MBB ÎÎÎÎ ÎÎÎÎ ÌÌÌÌÌÌ ÌÌÌÌÌÌ tsu(EN) tsu(EN) tsu(EN) ÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎ ÏÏÏ th(EN) ENB tpd(M-DV) ta ten B0–B35 th(EN) W1 ta W2 th(EN) No Operation tdis W3 Figure 5. FIFO Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 tc tw(CLKH) tw(CLKL) CLKA CSA W/RA Low High tsu(EN) ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÏÏÏÏÏ MBA tsu(EN) ENA IR High tsu(D) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌ ÌÌÌÌ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ th(EN) th(EN) th(D) W1 tsk(1)† tw(CLKH) A0–A35 tc tw(CLKL) 1 CLKB 2 3 tpd(C-OR) tpd(C-OR) Old Data in FIFO Output Register OR CSB Low W/RB High MBB Low ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌ tsu(EN) th(EN) ENB ta B0–B35 Old Data in FIFO Output Register W1 † tsk(1) is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(1), then the transition of OR high and the first word load to the output register can occur one CLKB cycle later than shown. Figure 6. OR-Flag Timing and First-Data-Word Fall Through When FIFO Is Empty 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 tc tw(CLKH) tw(CLKL) CLKB CSB Low W/RB High MBB Low ÎÎÎÎ ÌÌÌ ÎÎÎÎ ÌÌÌ tsu(EN) ENB OR High th(EN) ta B0–B35 FIFO Output Register Next Word From FIFO tsk(1)† tc tw(CLKH) 1 CLKA FIFO Full IR CSA W/RA MBA ENA tw(CLKL) 2 tpd(C-IR) tpd(C-IR) Low ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÌÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ High tsu(EN) th(EN) tsu(EN) th(EN) tsu(D) A0–A35 th(D) Write † tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown. Figure 7. IR-Flag Timing and First Available Write When FIFO Is Full POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 CLKA ÎÎÎÎÎ ÌÌÌÌ ÎÎÎÎÎ ÌÌÌÌ tsu(EN) ENA th(EN) tsk(2)† CLKB AE 1 2 tpd(C-AE) tpd(C-AE) X Words in FIFO ÎÎÎÎ ÌÌÌÌÌ ÎÎÎÎ ÌÌÌÌÌ (X + 1) Words in FIFO tsu(EN) ENB th(EN) † tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk(2), then AE can transition high one CLKB cycle later than shown. NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L) Figure 8. Timing for AE When FIFO Is Almost Empty tsk(2)‡ CLKA 1 ÎÎÎÎÎÌÌÌÌÌ tsu(EN) ENA tpd(C-AF) AF 2 th(EN) [D§ – (Y + 1)] Words in FIFO tpd(C-AF) (D§ – Y) Words in FIFO CLKB ÎÎÎÎÎ ÌÌÌÌ tsu(EN) ENB th(EN) ‡ tsk(2) is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown. § D = 512 for the SN74ALVC3631; D = 1024 for the SN74ALVC3641; D = 2048 for the SN74ALVC3651. NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L) Figure 9. Timing for AF When FIFO Is Almost Full 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 CLKB ÎÎÎÏÏÏ ÎÎÎ tsu(EN) ENB ÏÏÏ th(EN) tsu(EN) tsu(EN) RTM ÎÎÎ ÌÌÌ tsu(EN) RFM OR th(EN) th(EN) High ta B0–B35 ta W0 ta W2 W1 Initiate Retransmit Mode With W0 as First Word ta W0 Retransmit From Selected Position W1 End Retransmit Mode NOTE A: CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other enables are shown only to relate retransmit operations to the FIFO output register. Figure 10. Retransmit Timing Showing Minimum Retransmit Length CLKB RTM 1 High AE th(RM) ÎÎÎÎÎ ÌÌÌÌÌ tsu(RM) RFM 2 tpd(C-AE) X or Fewer Words From Empty (X + 1) or More Words From Empty NOTE A: X is the value loaded in the AE-flag offset register. Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 tsk(1)† CLKA 1 2 tpd(C-IR) IR FIFO Filled to First Retransmit Word One or More Write Locations Available CLKB ÌÌÌÌ ÏÏÏÏ ÌÌÌÌ ÏÏÏÏ tsu(EN) RTM th(EN) † tsk(1) is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(1), then IR can transition high one CLKA cycle later than shown. Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available tsk(2)‡ CLKA 1 2 tpd(C-AE) AF CLKB (D§ – Y) or More Words Past First Retransmit Word ÌÌÌÌ ÏÏÏÏÏ ÌÌÌÌ ÏÏÏÏÏ tsu(EN) RTM (Y + 1) or More Write Locations Available th(EN) ‡ tsk(2) is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk(2), then AF can transition high one CLKA cycle later than shown. § D = 512 for the SN74ALVC3631; D = 1024 for the SN74ALVC3641; D = 2048 for the SN74ALVC3651. NOTE A: Y is the value loaded in the AF flag offset register. Figure 13. AF Timing From the End of Retransmit Mode When (Y + 1) or More Write Locations Are Available 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 CLKA th(EN) tsu(EN) CSA W/RA MBA ENA ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ th(D) tsu(D) A0–A35 ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ W1 CLKB tpd(C-MF) tpd(C-MF) MBF1 CSB W/RB ÎÎÎÎ MBB ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÎÎÎÎ ÌÌÌÌ ÏÏÏÏ ÏÏÏÏ tsu(EN) ENB ten B0–B35 tpd(M-DV) tpd(C-MR) th(EN) tdis W1 (remains valid in mail1 register after read) FIFO Output Register Figure 14. Mail1 Register and MBF1 Flag POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 CLKB th(EN) tsu(EN) CSB ÌÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ W/RB MBB ENB tsu(D) B0–B35 W1 ÎÎÎ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ th(D) CLKA tpd(C-MF) tpd(C-MF) MBF2 CSA ÌÌÌÌÌ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌ ÎÎÎÎÎÎÎÎÎ ÌÌÌÌÌÌÌ ÎÎÎÎ ÌÌÌ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ W/RA MBA tsu(EN) th(EN) ENA ten tpd(C-MR) A0–A35 W1 (remains valid in mail2 register after read) Figure 15. Mail2 Register and MBF2 Flag 20 tdis POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA Package thermal impedance, θJA (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN TYP 3.0 3.3 MAX UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage High-level output current –4 mA IOL TA Low-level output current 8 mA 70 °C High-level input voltage 2 Operating free-air temperature 3.6 V VCC + 0.5 0.8 V 0 V electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP‡ MAX VCC = 3.0 V, VCC = 3.0 V, IOH = –4 mA IOL = 8 mA II IOZ VCC = 3.6 V, VCC = 3.6 V, VI = VCC or 0 VO = VCC or 0 ICC Cio VCC = 3.6 V, VI = 0, VI = VCC – 0.2 V or 0 f = 1 MHz 4 pF f = 1 MHz 8 pF Ccontrol VI = 0, ‡ All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2.4 UNIT VOH VOL V 0.5 V ±5 µA ±5 µA 350 µA 21 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 16) ’ALVC3631-10 ’ALVC3641-10 ’ALVC3651-10 MIN fclock tc Clock frequency, CLKA or CLKB tw(CH) tw(CL) MAX ’ALVC3631-15 ’ALVC3641-15 ’ALVC3651-15 MIN 100 Clock cycle time, CLKA or CLKB MAX ’ALVC3631-20 ’ALVC3641-20 ’ALVC3651-20 MIN 66.7 UNIT MAX 50 MHz 10 15 20 ns Pulse duration, CLKA and CLKB high 4 6 8 ns Pulse duration, CLKA and CLKB low 4 6 8 ns tsu(D) Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑ 2.5 3.5 4.5 ns tsu(EN) Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB, W/RB, ENB, MBB, RTM, and RFM before CLKB↑ 3.5 5 6 ns 6 7 8 ns Setup time, FS0 and FS1 before RST high tsu(RS) tsu(FS) tsu(SD)‡ Setup time, RST low before CLKA↑ or CLKB↑† 12 13 14 ns Setup time, FS0/SD before CLKA↑ 3.5 5 6 ns tsu(SEN)‡ th(D) Setup time, FS1/SEN before CLKA↑ 3.5 5 6 ns Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑ 0.5 0.5 0.5 ns Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, RFM, and MBB after CLKB↑ 0.5 0.5 0.5 ns th(RS) th(FS) th(SP)‡ Hold time, RST low after CLKA↑ or CLKB↑† 3.5 5 6 ns Hold time, FS0 and FS1 after RST high 0.5 0.5 0.5 ns Hold time, FS1/SEN high after RST high 0.5 0.5 0.5 ns th(SD)‡ th(SEN)‡ tsk(1)§ Hold time, FS0/SD after CLKA↑ 0.5 0.5 0.5 ns Hold time, FS1/SEN after CLKA↑ 0 0 0 ns Skew time between CLKA↑ and CLKB↑ for OR and IR 7 9 11 ns th(EN) tsk(2)§ Skew time between CLKA↑ and CLKB↑ for AE and AF 8 12 16 ns † Requirement to count the clock edge as one of at least four needed to reset a FIFO ‡ Applies only when serial load method is used to program flag offset registers § Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Figures 1 through 16) ’ALVC3631-10 ’ALVC3641-10 ’ALVC3651-10 PARAMETER MIN fmax ta MAX 100 ’ALVC3631-15 ’ALVC3641-15 ’ALVC3651-15 MIN MAX 66.7 ’ALVC3631-20 ’ALVC3641-20 ’ALVC3651-20 MIN UNIT MAX 50 MHz Access time, CLKB↑ to B0–B35 2 7.5 2 9.5 2 11.5 ns tpd(C-IR) tpd(C-OR) Propagation delay time, CLKA↑ to IR 1 6.5 1 8 1 10 ns Propagation delay time, CLKB↑ to OR 1 6.5 1 8 1 10 ns tpd(C-AE) tpd(C-AF) Propagation delay time, CLKB↑ to AE 1 8 1 8 1 10 ns Propagation delay time, CLKA↑ to AF 1 8 1 8 1 10 ns tpd(C-MF) Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and CLKB↑ to MBF2 low or MBF1 high 0 6.5 0 8 0 10 ns tpd(C-MR) Propagation delay time, CLKA↑ to B0–B35† and CLKB↑ to A0–A35‡ 2 11 2 12 2 13 ns Propagation delay time, MBB to B0–B35 valid 2 9 2 10 2 12 ns Propagation delay time, RST low to AE low and AF high 1 6.5 1 7.5 1 8.5 ns ten Enable time, CSA and W/RA low to A0–A35 active and CSB low and W/RB high to B0–B35 active 2 10 2 11 2 12 ns tdis Disable time, CSA or W/RA high to A0–A35 at high impedance and CSB high or W/RB low to B0–B35 at high impedance 1 10 1 11 1 12 ns tpd(M-DV) tpd(R-F) † Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high ‡ Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 PARAMETER MEASUREMENT INFORMATION 3.3 V 330 Ω From Output Under Test 30 pF (see Note A) 510 Ω LOAD CIRCUIT 3V 3V Timing Input High-Level Input 1.5 V 1.5 V GND GND tsu Data, Enable Input tw th 3V 1.5 V 3V Low-Level Input 1.5 V 1.5 V 1.5 V GND GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 3V 1.5 V 1.5 V GND tPLZ tPZL Low-Level Output ≈3 V 3V 1.5 V 1.5 V Input GND VOL tPHZ tpd tpd tPZH VOH High-Level Output 1.5 V ≈0 V VOH In-Phase Output 1.5 V VOL NOTES: A. Includes probe and jig capacitance B. tPZL and tPZH are the same as ten. C. tPLZ and tPHZ are the same as tdis. Figure 16. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 24 1.5 V • DALLAS, TEXAS 75265 SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 × 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY I CC(f) – Supply Current – mA 250 VCC = 3.6 V fdata = 1/2 fclock TA = 25°C CL = 0 pF 200 VCC = 3.3 V VCC = 3.0 V 150 100 50 0 0 20 40 60 80 100 fclock – Clock Frequency – MHz Figure 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ALVC3631-10PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3631-10PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3631-15PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3631-15PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3631-20PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) SN74ALVC3631-20PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3641-10PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3641-10PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3641-15PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3641-15PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3641-20PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3641-20PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3651-10PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3651-10PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3651-15PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3651-15PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI SN74ALVC3651-20PCB OBSOLETE HLQFP PCB 120 TBD Call TI Call TI SN74ALVC3651-20PQ OBSOLETE BQFP PQ 132 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MBQF001A – NOVEMBER 1995 PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK 100 LEAD SHOWN 13 89 1 100 14 88 0.012 (0,30) 0.008 (0,20) 0.006 (0,15) M ”D3” SQ 0.025 (0,635) 0.006 (0,16) NOM 64 38 0.150 (3,81) 0.130 (3,30) 39 63 Gage Plane ”D1” SQ ”D” SQ 0.010 (0,25) 0.020 (0,51) MIN ”D2” SQ 0°– 8° 0.046 (1,17) 0.036 (0,91) Seating Plane 0.004 (0,10) 0.180 (4,57) MAX LEADS *** 100 132 MAX 0.890 (22,61) 1.090 (27,69) MIN 0.870 (22,10) 1.070 (27,18) MAX 0.766 (19,46) 0.966 (24,54) MIN 0.734 (18,64) 0.934 (23,72) MAX 0.912 (23,16) 1.112 (28,25) MIN 0.888 (22,56) 1.088 (27,64) NOM 0.600 (15,24) 0.800 (20,32) DIM ”D” ”D1” ”D2” ”D3” 4040045 / C 11/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-069 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998 PCB (S-PQFP-G120) PLASTIC QUAD FLATPACK (DIE DOWN) 0,23 0,13 0,40 90 0,07 M 61 Heat Slug 91 60 120 31 0,13 NOM 1 30 11,60 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040202 / C 12/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced molded plastic package with a heat slug (HSL) Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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