SN74ALVCH16270DGGR

www.ti.com SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028G – JULY 1995 – REVISED AUGUST 2004 FEATURES • • • • • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DESCRIPTION This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. DGG OR DL PACKAGE (TOP VIEW) OEA CLKEN1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 CLKEN2B SEL 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK line space To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16270 is characterized for operation from -40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2004, Texas Instruments Incorporated SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 FUNCTION TABLES line space OUTPUT ENABLE INPUTS OUTPUTS CLK OEA OEB A 1B, 2B ↑ H H Z Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active A-TO-B STORAGE (OEB = L) INPUTS CLKENA1 CLKENA2 L L (1) (2) H OUTPUTS CLK A X H X L L ↑ L L ↑ H L H H 1B X X 2B 1B0 (1) 2B0 (1) 1B0 (1) 2B0 (1) L L (2) L H H (2) H ↑ L 1B0 (1) L L ↑ H 1B0 (1) H H X X 1B0 (1) 2B0 (1) Output level before the indicated steady-state input conditions were established Two CLK edges are needed to propagate data. B-TO-A STORAGE (OEA = L) INPUTS CLKEN1B CLKEN2B CLK SEL 1B 2B OUTPUT A H X X H X X A0 (1) X H X L X X A0 (1) L X ↑ H L X L L X ↑ H H X H X L ↑ L X L L X L ↑ L X H H (1) 2 Output level before the indicated steady-state input conditions were established SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 29 CLK 2 CLKEN1B 27 CLKEN2B CLKENA1 30 55 C1 CLKENA2 56 1D OEB 28 SEL OEA 1 CE 1D C1 1D C1 G1 A1 1 CE C1 1D 1D 6 2B1 CE C1 1D 1B1 CE 1 8 23 C1 1D CE C1 1D 1 of 12 Channels 3 SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage MIN MAX -0.5 4.6 Except I/O ports (2) -0.5 4.6 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.5 UNIT V VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 81 DL package 74 -65 150 V V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS (1) MIN VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MAX 1.65 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2.7 V to 3.6 V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V 0.8 VCC = 1.65 V -4 VCC = 2.3 V -12 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA V 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 IOL = 24 mA 2.7 V 0.4 3V 0.55 ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 VI = 2 V VI = 0 to 3.6 V (2) IOZ (3) VO = VCC or GND ICC VI = VCC or GND, IO = 0 ∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND UNIT 1.2 IOL = 4 mA IOL = 12 mA II(hold) MAX VCC - 0.2 1.65 V IOH = -12 mA II MIN TYP (1) IOH = -4 mA VOH VOL VCC V µA µA 3.6 V ±500 3.6 V ±10 µA 3.6 V 40 µA 3 V to 3.6 V 750 µA Ci Control inputs VI = VCC or GND 3.3 V 3.5 pF Cio A or B ports VO = VCC or GND 3.3 V 9 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. 5 SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 2.5 V ± 0.2 V VCC = 1.8 V MIN Clock frequency tw Pulse duration, CLK high or low th Setup time Hold time (1) MIN MAX (1) fclock tsu MAX VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN 150 150 (1) 3.3 3.3 3.3 A data before CLK↑ (1) 4.1 3.8 3.1 B data before CLK↑ (1) 0.9 1.2 0.9 CLKENA1 or CLKENA2 before CLK↑ (1) 3.5 3.2 2.7 CLKEN1B or CLKEN2B before CLK↑ (1) 3.4 3 2.6 OE data before CLK↑ (1) 4.4 3.9 3.2 A data after CLK↑ (1) 0 0 0.2 B data after CLK↑ (1) 1.4 1 1.7 CLKENA1 or CLKENA2 after CLK↑ (1) 0 0.1 0.3 CLKEN1B or CLKEN2B after CLK↑ (1) 0 0 0.6 OE after CLK↑ (1) 0 0 0.1 UNIT MAX MHz ns ns ns This information was not available at the time of publication. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN (1) fmax CLK tpd (1) MAX VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz B (1) 1.5 5.9 5.8 1.1 5.1 A (1) 1.2 5.4 5.4 1 4.7 5.5 ns SEL A (1) 1.4 6.2 6.4 1 ten CLK A or B (1) 1.5 7 6.8 1 6 ns tdis CLK A or B (1) 1.9 7.2 6.5 1.1 5.8 ns This information was not available at the time of publication. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd (1) 6 Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF, This information was not available at the time of publication. f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 87 120 (1) 80.5 118 UNIT pF SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 7 SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES028G – JULY 1995 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω S1 Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V tPZH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 2.7 V 1.5 V Output Waveform 1 S1 at 6 V (see Note B) tPHL VOH Output Output Control (low-level enabling) tPZL 2.7 V Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 0V 0V tsu 1.5 V Input Output Waveform 2 S1 at GND (see Note B) VOL tPHZ VOH 1.5 V VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ALVCH16270DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16270 SN74ALVCH16270DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16270 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of