SN74AUC16374GQLR

SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES403E – JULY 2002 – REVISED APRIL 2007 FEATURES • • • • • • • • • DGG OR DGV PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 2.8 ns at 1.8 V Low Power Consumption, 20-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE DESCRIPTION/ORDERING INFORMATION This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2D7 2D8 2CLK A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION PACKAGE (1) (2) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Reel of 2000 SN74AUC16374DGGR AUC16374 TVSOP – DGV Reel of 2000 SN74AUC16374DGVR MH374 VFBGA – ZQL Reel of 1000 SN74AUC16374ZQLR MH374 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2007, Texas Instruments Incorporated SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES403E – JULY 2002 – REVISED APRIL 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. GQL PACKAGE (TOP VIEW) 1 2 3 4 5 TERMINAL ASSIGNMENTS (1) 1 6 2 3 4 5 6 A 1OE NC NC NC NC 1CLK A B 1Q2 1Q1 GND GND 1D1 1D2 B C 1Q4 1Q3 VCC VCC 1D3 1D4 C D 1Q6 1Q5 GND GND 1D5 1D6 D E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2CLK E F G H GND J K (1) NC - No internal connection FUNCTION TABLE (EACH FLIP-FLOP) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1CLK 1D1 1 2OE 48 47 2CLK C1 2 1D 1Q1 24 25 C1 2D1 36 To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG and DGV packages. 2 1D Submit Documentation Feedback 13 2Q1 SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES403E – JULY 2002 – REVISED APRIL 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 3.6 V –0.5 3.6 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg (1) (2) (3) DGG package 70 DGV package 58 GQL package 42 Storage temperature range –65 V °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V MIN MAX 0.8 2.7 Low-level input voltage V VCC 0.65 × VCC V 1.7 VCC = 0.8 V VIL UNIT 0 VCC = 1.1 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V V 0.7 VI Input voltage 0 3.6 V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current VCC = 0.8 V –0.7 VCC = 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) mA mA 9 –40 20 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES403E – JULY 2002 – REVISED APRIL 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS MIN TYP (1) MAX VCC IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 IOH = –5 mA 1.4 V 1 IOH = –8 mA 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOL = 3 mA 1.1 V 0.3 IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 UNIT VCC – 0.1 0.55 V 0.2 0.25 V VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA IOZ VO = VCC or GND 2.7 V ±10 µA ICC VI = VCC or GND, 20 µA Ci VI = VCC or GND 2.5 V 3 pF Co VO = VCC or GND 2.5 V 5 pF II (1) All inputs IO = 0 0.8 V to 2.7 V All typical values are at TA = 25°C. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V TYP VCC = 1.2 V ± 0.1 V MIN MAX VCC = 1.5 V ± 0.1 V MIN 250 MAX VCC = 1.8 V ± 0.15 V MIN VCC = 2.5 V ± 0.2 V MAX 250 MIN 250 UNIT MAX fclock Clock frequency 85 250 MHz tw Pulse duration, CLK high or low 5.9 1.9 1.9 1.9 1.9 ns tsu Setup time, data before CLK↑ 1.4 1.2 0.7 0.6 0.6 ns th Hold time, data after CLK↑ 0.1 0.4 0.4 0.4 0.4 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) VCC = 0.8 V tpd CLK Q ten OE Q 7 tdis OE Q 8.2 PARAMETER fmax 4 VCC = 1.2 V ± 0.1 V MAX VCC = 1.5 V ± 0.1 V TYP MIN MIN MAX 85 250 7.3 1 4.5 0.8 2.9 1.2 5.3 0.8 2 7.1 1 MIN VCC = 2.5 V ± 0.2 V MAX 0.7 1.5 2.8 0.7 2.2 ns 3.6 0.8 1.5 2.9 0.7 2.2 ns 4.8 1.4 2.7 4.5 0.5 2.2 ns 250 MIN UNIT TYP 250 Submit Documentation Feedback VCC = 1.8 V ± 0.15 V MAX 250 MHz SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES403E – JULY 2002 – REVISED APRIL 2007 Operating Characteristics (1) TA = 25°C PARAMETER TEST CONDITIONS 1 fdata = 5 MHz, Outputs Cpd Power 1 fclk = 10 MHz, enabled, (each dissipation 1 fout = 5 MHz, 1 output output) (2) capacitance OE = GND, switching CL = 0 pF VCC = 0.8 V VCC = 1.8 V VCC = 2.5 V TYP VCC = 1.2 V VCC = 1.5 V TYP TYP TYP TYP 24 24 24.1 26.2 31.2 pF UNIT Cpd(Z) Outputs disabled, Power 1 clock dissipation and 1 capacitance data switching 1 fdata = 5 MHz, 1 fclk = 10 MHz, fout = not switching, OE = VCC, CL = 0 pF 7.5 7.5 8 9.4 13.2 pF Cpd (each clock) (3) Outputs Power disabled, dissipation clock capacitance only switching 1 fdata = 0 MHz, 1 fclk = 10 MHz, fout = not switching, OE = VCC, CL = 0 pF 13.8 13.8 14 14.7 17.5 pF (1) (2) (3) Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)} Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this test, but its ICC component has been subtracted out). Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz. Submit Documentation Feedback 5 SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCES403E – JULY 2002 – REVISED APRIL 2007 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND Open RL LOAD CIRCUIT VCC CL RL V∆ 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPHL tPLH VCC/2 VCC/2 VOL tPHL VOH Output tPLZ VCC VCC/2 tPZH VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VCC/2 VCC/2 tPZL VOH Output VCC Output Control VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74AUC16374DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AUC16374 Samples SN74AUC16374DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MH374 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of