SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
FEATURES
•
•
•
•
•
•
•
•
•
DCT OR DCU PACKAGE
(TOP VIEW)
Available in the Texas Instruments
NanoFree™ Package
Operates at 0.8 V to 2.7 V
Sub-1-V Operable
Max tpd of 0.5 ns at 1.8 V
Low Power Consumption, 10 µA at 2.7 V
High On-Off Output Voltage Ratio
High Degree of Linearity
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1A
1B
2C
GND
1
8
2
7
3
6
4
5
VCC
1C
2B
2A
YZP PACKAGE
(BOTTOM VIEW)
GND
2C
1B
1A
4 5
3 6
2 7
1 8
2A
2B
1C
VCC
DESCRIPTION/ORDERING INFORMATION
This dual analog switch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.1-V to 2.7-V VCC
operation.
The SN74AUC2G66 can handle both analog and digital signals. It permits signals with amplitudes of up to 2.7-V
(peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING (2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74AUC2G66YZPR
_ _ _U6_
SSOP – DCT
Reel of 3000
SN74AUC2G66DCTR
U66_ _ _
VSSOP – DCU
Reel of 3000
SN74AUC2G66DCUR
U66_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
H
ON
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
A
B
4
C
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range (2)
–0.5
3.6
V
VI
Input voltage range (2) (3)
–0.5
3.6
V
VI/O
Switch I/O voltage range
–0.5
VCC + 0.5
V
IIK
Control input clamp current
VI < 0
–50
mA
IIOK
I/O port diode current
VI/O < 0 or VI/O > VCC
±50
mA
IT
On-state switch current
VI/O = 0 to VCC
±50
mA
±100
mA
(2) (3)
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DCT package
220
DCU package
227
YZP package
(1)
(2)
(3)
(4)
2
UNIT
°C/W
102
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
Recommended Operating Conditions
VCC
(1)
Supply voltage
VCC = 0.8 V
VIH
High-level input voltage
MIN
MAX
0.8
2.7
UNIT
V
VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 × VCC
V
1.7
VCC = 0.8 V
0
0.35 × VCC
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VI/O
I/O port voltage
0
VCC
V
VI
Control input voltage
0
3.6
V
VCC = 2.3 V to 2.7 V
∆t/∆v
TA
(1)
(2)
(3)
Input transition rise or fall rate
0.7
VCC = 0.8 V to 1.65 V (2)
20
VCC = 1.65 V to 2.3 V (3)
20
VCC = 2.3 V to 2.7 V (3)
20
Operating free-air temperature
V
–40
ns/V
°C
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1).
The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1).
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP (1)
MAX
1.1 V
17
40
1.65 V
7
20
2.3 V
4
15
1.1 V
131
180
1.65 V
32
80
2.3 V
15
20
UNIT
VI = VCC or GND,
VC = VIH
(see Figure 1 and Figure 2)
IS = 4 mA
VI = VCC to GND,
VC = VIH
(see Figure 1 and Figure 2)
IS = 4 mA
Difference of
on-state resistance
between switches
VI = VCC to GND,
VC = VIH
(see Figure 1 and Figure 2)
IS = 4 mA
IS(off)
Off-state switch leakage current
VI = VCC and VO = GND, or
VI = GND and VO = VCC,
VC = VIL (see Figure 3)
2.7 V
IS(on)
On-state switch leakage current
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 4)
2.7 V
II
Control input current
VI = VCC or GND
ICC
Supply current
VI = VCC or GND,
Cic
Control input capacitance
2.5 V
2.5
pF
Cio(off)
Switch input/output capacitance
2.5 V
3
pF
Cio(on)
Switch input/output capacitance
2.5 V
7
pF
ron
On-state switch resistance
ron(p)
∆ron
(1)
(2)
Peak on resistance
IS = 8 mA
IS = 8 mA
IS = 8 mA
1.1 V
3
1.65 V
1
2.3 V
1
±1
IO = 0
±0.1 (2)
±1
±0.1 (2)
Ω
Ω
Ω
µA
µA
0 to 2.7 V
±5
µA
0.8 V to 2.7 V
10
µA
ta = 25°C
The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1).
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3
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 5)
(1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
tpd (1)
A or B
B or A
1
0.4
ns
ten
C
A or B
5
0.5
3
0.5
2.1
0.5
0.9
1.6
0.5
1.4
ns
tdis
C
A or B
5.3
0.5
4
0.5
3
0.5
2.6
3.3
0.5
2.7
ns
PARAMETER
TYP
MIN MAX
MIN MAX
0.6
MIN
TYP MAX
0.5
MIN
UNIT
MAX
0.5
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 5)
(1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
0.7
ns
ten
C
A or B
0.5
1.6
2.7
0.5
2.3
ns
tdis
C
A or B
0.5
2.7
3.4
0.5
2
ns
PARAMETER
MIN
TYP MAX
MIN
0.7
UNIT
MAX
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Analog Switch Characteristics
TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
Frequency response
(switch ON)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
Crosstalk
(between switches)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
4
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VCC
TYP
0.8 V
101
1.1 V
150
1.4 V
175
1.65 V
250
2.3 V
400
0.8 V
450
1.1 V
>500
1.4 V
>500
1.65 V
>500
2.3 V
>500
0.8 V
–60
1.1 V
–60
1.4 V
–60
1.65 V
–60
2.3 V
–60
0.8 V
–65
1.1 V
–65
1.4 V
–65
1.65 V
–65
2.3 V
–65
UNIT
MHz
dB
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
Analog Switch Characteristics (continued)
TA = 25°C
PARAMETER
FROM
(INPUT)
Crosstalk
(control input to signal
output)
C
TO
(OUTPUT)
TEST CONDITIONS
VCC
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 8)
A or B
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
Feedthrough attenuation
(switch OFF)
A or B
B or A
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
A or B
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 10)
B or A
Sine-wave distortion
A or B
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 10)
B or A
TYP
0.8 V
9
1.1 V
14
1.4 V
15
1.65 V
16
2.3 V
20
0.8 V
–50
1.1 V
–50
1.4 V
–50
1.65 V
–50
2.3 V
–50
0.8 V
–60
1.1 V
–60
1.4 V
–60
1.65 V
–60
2.3 V
–60
0.8 V
7
1.1 V
0.256
1.4 V
0.04
1.65 V
0.03
2.3 V
0.01
0.8 V
3.7
1.1 V
0.4
1.4 V
0.04
1.65 V
0.02
2.3 V
0.02
UNIT
mV
dB
%
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST
CONDITIONS
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
f = 10 MHz
2.5
2.5
2.5
2.5
2.5
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UNIT
pF
5
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
B or A
A or B
VI = VCC or GND
VIH
VO
C
VC
(ON)
GND
IS
r on +
V
VI * VO
W
IS
VI – VO
Figure 1. On-State Resistance Test Circuit
120
VCC = 1.1 V
100
80
60
40
VCC = 1.65 V
20
VCC = 2.3 V
0
0
1
2
Figure 2. Typical ron as a Function of Voltage (VI) for VI = 0 to VCC
6
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3
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
VI
B or A
A or B
A
VO
C
VC
VIL
(OFF)
GND
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
Figure 3. Off-State Switch Leakage-Current Test Circuit
VCC
VCC
VI = VCC or GND
A
B or A
A or B
VO
VO = Open
VIH
C
VC
(ON)
GND
Figure 4. On-State Leakage-Current Test Circuit
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7
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
INPUTS
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
VI
tr/tf
VCC
VCC
VCC
VCC
VCC
VCC
VCC
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
0.1 µF
C
VC
VIH
50 Ω
fin
B or A
A or B
VO
RL
(ON)
GND
CL
VCC/2
RL/CL: 600 Ω / 50 pF
RL/CL: 50 Ω / 5 pF
Figure 6. Frequency Response (Switch ON)
VCC
VCC
0.1 µF
Rin
600 Ω
fin
1B or 1A
1A or 1B
VIH
50 Ω
VO1
RL
600 Ω
C
VC
CL
50 pF
(On)
VCC/2
2B or 2A
2A or 2B
Rin
600 Ω
VIL
VO2
RL
600 Ω
C
VC
(Off)
GND
CL
50 pF
VCC/2
20log10(VO2/VI1) or
20log10(VO1/VI2)
Figure 7. Crosstalk (Between Switches)
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9
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
Rin
600 Ω
B or A
A or B
VCC/2
VO
CL
50 pF
RL
600 Ω
C
VC
GND
VCC/2
50 Ω
Figure 8. Crosstalk (Control Input – Switch Output)
VCC
VCC
0.1 µF
fin
50 Ω
B or A
A or B
RL
VIL
C
VC
RL
(OFF)
VCC/2
RL/CL: 600 Ω / 50 pF
RL/CL: 50 Ω / 5 pF
Figure 9. Feedthrough, Switch Off
10
VO
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GND
VCC/2
CL
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A – NOVEMBER 2003 – REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VCC
10 µF
fin
600 Ω
VIH
10 µF
B or A
A or B
VO
RL
10 kΩ
C
VC
(ON)
GND
CL
50 pF
VCC/2
VCC = 0.8 V, VI = 0.7 VP-P
VCC = 1.1 V, VI = 1 VP-P
VCC = 1.4 V, VI = 1.2 VP-P
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.3 V, VI = 2 VP-P
Figure 10. Sine-Wave Distortion
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11
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74AUC2G66DCTR
ACTIVE
SM8
DCT
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U66
(R, Z)
Samples
SN74AUC2G66DCUR
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
(66, U66Q, U66R)
(UR, UZ)
Samples
SN74AUC2G66DCURG4
ACTIVE
VSSOP
DCU
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
U66R
Samples
SN74AUC2G66YZPR
ACTIVE
DSBGA
YZP
8
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
U6N
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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