SN74AUC2GU04YZPR

SN74AUC2GU04 DUAL INVERTER GATE www.ti.com SCES438C – APRIL 2003 – REVISED JANUARY 2007 FEATURES • • • • • • • • Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Sub-1-V Operable Unbuffered Outputs Max tpd of 1.9 ns at 1.8 V • DBV PACKAGE (TOP VIEW) 1A 1 6 Low Power Consumption, 10 µA at 1.8 V ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) YZP PACKAGE (BOTTOM VIEW) DCK PACKAGE (TOP VIEW) 1A 1Y GND 2 5 VCC 2A 3 4 2Y 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 2A 3 4 2Y GND 1A 2 5 VCC 1 6 1Y See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This dual inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2GU04 contains two inverters with unbuffered outputs and performs the Boolean function Y = A. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027. ORDERING INFORMATION TA –40°C to 85°C (1) (2) PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74AUC2GU04YZPR _ _ _UD_ SOT (SOT-23) – DBV Reel of 3000 SN74AUC2GU04DBVR UU4_ SOT (SC-70) – DCK Reel of 3000 SN74AUC2GU04DCKR UD_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2007, Texas Instruments Incorporated SN74AUC2GU04 DUAL INVERTER GATE www.ti.com SCES438C – APRIL 2003 – REVISED JANUARY 2007 FUNCTION TABLE (EACH INVERTER) INPUT A OUTPUT Y H L L H LOGIC DIAGRAM (POSITIVE LOGIC) 1 6 1A 1Y 3 4 2A 2Y Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 3.6 V –0.5 VCC + 0.5 range (2) VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg Storage temperature range DBV package 165 DCK package 259 YZP package (1) (2) (3) 2 UNIT V °C/W 123 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback SN74AUC2GU04 DUAL INVERTER GATE www.ti.com SCES438C – APRIL 2003 – REVISED JANUARY 2007 Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage IO = –100 µA VIL Low-level input voltage IO = –100 µA VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current MIN MAX 0.8 2.7 Input transition rise or fall rate TA Operating free-air temperature (1) V 0.65 × VCC V 0.35 × VCC V 0 3.6 V 0 VCC V VCC = 0.8 V –0.7 VCC= 1.1 V –3 VCC = 1.4 V –5 VCC = 1.65 V –8 VCC = 2.3 V –9 VCC = 0.8 V 0.7 VCC= 1.1 V 3 VCC = 1.4 V 5 VCC = 1.65 V 8 VCC = 2.3 V ∆t/∆v UNIT mA mA 9 –40 20 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC IOH = –100 µA 0.8 V to 2.7 V IOH = –0.7 mA 0.8 V IOH = –3 mA 1.1 V 0.8 1.4 V 1 1.65 V 1.2 IOH = –9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V IOL = 0.7 mA 0.8 V IOH = –5 mA VIL = GND IOH = –8 mA IOL = 3 mA VOL IOL = 5 mA VIH = VCC IOL = 8 mA IOL = 9 mA II A inputs VI = VCC or GND ICC VI = VCC or GND, CI VI = VCC or GND (1) MIN IO = 0 TYP (1) MAX UNIT VCC – 0.1 0.55 V 0.2 0.25 1.1 V 0.3 1.4 V 0.4 1.65 V 0.45 2.3 V 0.6 V 0 to 2.7 V ±5 µA 0.8 V to 2.7 V 10 µA 2.5 V 2.5 pF All typical values are at TA = 25°C. Submit Documentation Feedback 3 SN74AUC2GU04 DUAL INVERTER GATE www.ti.com SCES438C – APRIL 2003 – REVISED JANUARY 2007 Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 0.8 V A Y 6.2 tpd TYP VCC = 1.2 V ± 0.1 V MIN MAX 0.7 3.1 VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V MIN MAX MIN 0.7 2.2 0.6 VCC = 2.5 V ± 0.2 V TYP MAX 1.1 1.9 UNIT MIN MAX 0.5 1.4 ns Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A Y tpd VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V UNIT MIN TYP MAX MIN MAX 0.7 1.6 2.7 0.5 2 ns Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V TYP TYP TYP TYP TYP f = 10 MHz 4.5 4.5 4.5 4.5 5.5 Submit Documentation Feedback UNIT pF SN74AUC2GU04 DUAL INVERTER GATE www.ti.com SCES438C – APRIL 2003 – REVISED JANUARY 2007 PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 2 × VCC S1 RL From Output Under Test Open S1 Open 2 × VCC GND GND CL (see Note A) RL LOAD CIRCUIT VCC CL RL VD 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kW 2 kW 2 kW 2 kW 2 kW 1 kW 500 W 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tW tsu VCC Input VCC/2 VCC/2 th VCC Data Input VCC/2 VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPLH VOH VCC/2 VOL tPHL VCC/2 tPLZ VCC VCC/2 tPZH VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC/2 tPZL tPHL VCC/2 Output VCC Output Control VOL + VD VOL tPHZ VCC/2 VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, slew rate ³ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) 74AUC2GU04DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UU4R SN74AUC2GU04DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UU4R SN74AUC2GU04DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 UDR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of