SN74AVC16269DGGR

SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 D D D D D Member of the Texas Instruments Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process DOC  (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC D D D Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages description A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal – Output Voltage – V 2.8 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 OH VCC = 1.8 V 0.8 V VOL – Output Voltage – V 2.8 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 VCC = 3.3 V VCC = 2.5 V 0.4 0.4 0 17 34 51 68 85 102 119 IOL – Output Current – mA 136 153 170 VCC = 1.8 V –160 –144 –128 –112 –96 –80 –64 –48 IOH – Output Current – mA –32 –16 0 Figure 1. Output Voltage vs Output Current This 12-bit to 24-bit registered bus exchanger is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments. Copyright  2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 description (continued) Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2). To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16269 is characterized for operation from –40°C to 85°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 terminal assignments DGG OR DGV PACKAGE (TOP VIEW) OEA OEB1 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 NC SEL 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OEB2 CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK NC – No internal connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 Function Tables OUTPUT ENABLE OUTPUTS INPUTS CLK OEA OEB A 1B, 2B ↑ H H Z Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active A-TO-B STORAGE (OEB = L) INPUTS OUTPUTS CLKENA1 CLKENA2 CLK A 1B 1B0† 2B 2B0† H H X X L X ↑ L X ↑ L L X H H X X L ↑ L X X L ↑ H L H X † Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (OEA = L) INPUTS OUTPUT A CLK SEL 1B 2B X H X X X L X X ↑ H L X L ↑ H H X H ↑ L X L L A0† A0† ↑ L X H H † Output level before the indicated steady-state input conditions were established 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 logic diagram (positive logic) CLK OEB1 29 C1 2 1D C1 OEB2 CLKENA1 CLKENA2 56 1D 30 55 C1 SEL OEA 28 1D 1 1D 1 of 12 Channels C1 G1 A1 8 C1 1 1D 23 1B1 1 CE C1 1D 6 2B1 CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any input/output when the output is in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 recommended operating conditions (see Note 4) VCC VIH Supply voltage High-level input voltage MIN MAX Operating 1.4 3.6 Data retention only 1.2 VCC = 1.2 V VCC = 1.4 V to 1.6 V VCC 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0.65 × VCC VI VO IOHS IOLS Low-level input voltage Output voltage Static high-level high level output current† low level output current† Static low-level V 2 GND 0.35 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V Input voltage V 1.7 VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL UNIT V 0.7 0.8 0 3.6 V Active state 0 3-state 0 VCC 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V –2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V –8 –4 mA –12 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V 2 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 8 4 mA 12 ∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature –40 85 °C † Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOHS = –100 µA IOHS = –2 mA, VOH VIH = 0.91 V VIH = 1.07 V IOHS = –4 mA, IOHS = –8 mA, II Ioff Control inputs IOZ‡ ICC 1.4 V VIH = 1.7 V VIH = 2 V IOHS = –12 mA, IOLS = 100 µA VOL VCC 1.4 V to 3.6 V VIL = 0.49 V VIL = 0.57 V IOLS = 8 mA, IOLS = 12 mA, VIL = 0.7 V VIL = 0.8 V VI = VCC or GND VI or VO = 3.6 V VO = VCC or GND VI = VCC or GND, Control inputs VI = VCC or GND Cio A or B ports orts VO = VCC or GND TYP† IO = 0 MAX UNIT VCC–0.2 1.05 1.65 V 1.2 2.3 V 1.75 3V 2.3 V 1.4 V to 3.6 V IOLS = 2 mA, IOLS = 4 mA, Ci MIN 0.2 1.4 V 0.4 1.65 V 0.45 2.3 V 0.55 V 3V 0.7 3.6 V ±2.5 µA 0 ±10 µA 3.6 V ±12.5 µA 3.6 V 40 µA 2.5 V 3.5 3.3 V 3.5 2.5 V 8.5 3.3 V 8.5 pF pF F † Typical values are measured at TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) VCC = 1.2V TYP VCC = 1.5 V ± 0.1 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu th 8 Setup time Hold time MAX VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN 75 MAX VCC = 3.3 V ± 0.3 V MIN 125 175 5.8 5 3.5 A data before CLK↑ 4.7 3.9 2.6 2.1 1.9 B data before CLK↑ 6.2 4.3 3 2.1 1.9 SEL before CLK↑ 4.5 3.4 2.2 1.6 1.3 CLKENA1 or CLKENA2 before CLK↑ 0.9 0.9 1 1.1 1.1 OE before CLK↑ 5.4 5.3 2 1.6 1.1 A data after CLK↑ 1.9 2 1.2 1.1 1 B data after CLK↑ 0.4 1.3 0.5 0.6 0.7 1 1 0.4 0.3 0.4 CLKENA1 or CLKENA2 after CLK↑ 2.6 2.2 1.4 1.1 1 OE after CLK↑ 0.4 0.4 0.4 0.5 0.3 SEL after CLK↑ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX MHz ns ns ns SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5) FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 1.2 V TYP VCC = 1.5 V ± 0.1 V MIN VCC = 1.8 V ± 0.15 V MAX MIN fmax VCC = 2.5 V ± 0.2 V MAX 75 tpd d CLK ten CLK tdis di CLK MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 175 MHz B 13.5 3 9.5 2.5 6.7 1.6 4 1.1 3 A 11.6 2.6 7.4 2.2 5.8 1.5 3.5 1 2.7 B 16 3.5 12 2.4 8.5 2.1 4.8 1.5 3.8 A 14.2 3.2 9.3 2 6.7 2 4.4 1.4 3.4 B 16 4.9 12.3 3.3 8.5 1.9 4.8 1.3 3.7 A 11.9 3 8.7 2.1 6.7 1.8 3.6 1.7 3.4 ns ns ns switching characteristics, TA = 0°C to 85°C, CL = 0 pF† FROM (INPUT) PARAMETER tpd d VCC = 3.3 V ± 0.15 V TO (OUTPUT) CLK MIN MAX B 1.4 2.4 A 1.2 2.1 UNIT ns † Texas Instruments SPICE simulation data operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0 0, POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP 133 145 168 102 109 124 f = 10 MHz • DALLAS, TEXAS 75265 UNIT pF 9 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open GND CL = 15 pF (see Note A) 2 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VCC/2 VOH VOH – 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AVC16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES152G – DECEMBER 1998 – REVISED MARCH 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V S1 500 Ω From Output Under Test 2 × VCC Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw LOAD CIRCUIT VCC VCC Timing Input Input VCC/2 VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 0V tPZL VCC Input VCC/2 VCC/2 0V tPLH VCC/2 tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC/2 VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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