SN74AVC16646DGVR

SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 • FEATURES • • • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages • • • DESCRIPTION A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. 3.2 TA = 25°C Process = Nominal - Output Voltage - V 2.8 2.4 VCC = 3.3 V 2.0 1.6 VCC = 2.5 V 1.2 OH VCC = 1.8 V 0.8 V VOL - Output Voltage - V 2.8 TA = 25°C Process = Nominal 2.4 2.0 1.6 1.2 0.8 VCC = 3.3 V 0.4 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 2.5 V VCC = 1.8 V -160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA -32 -16 0 Figure 1. Output Voltage vs Output Current This 16-bit bus transceiver and register is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16646 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 2 illustrates the four fundamental bus-management functions that can be performed with the SN74AVC16646. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC, DOC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2005, Texas Instruments Incorporated SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 DESCRIPTION (CONTINUED) The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function still is enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16646 is characterized for operation from –40°C to 85°C. TERMINAL ASSIGNMENTS DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR 2 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 FUNCTION TABLE (EACH 8-BIT TRANSCEIVER/REGISTER) INPUTS (1) DATA I/Os OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1-A8 B1-B8 X X ↑ X X X Input Unspecified (1) Store A, B unspecified (1) X ↑ X X Unspecified (1) Input Store B, A unspecified (1) X X H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. 3 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com OE L DIR L CLKAB CLKBA X X SAB X BUS B BUS A BUS A BUS B SCES181F – DECEMBER 1998 – REVISED JUNE 2005 SBA L OE L DIR H DIR X X X CLKAB CLKBA X ↑ X ↑ ↑ ↑ SAB X X X STORAGE FROM A, B, OR A AND B SBA X X X OE L L SBA X BUS B DIR L H CLKAB X H or L CLKBA H or L X SAB X H TRANSFER STORED DATA TO A AND/OR B Figure 2. Bus-Management Functions 4 SAB L BUS A BUS A OE X X H CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SBA H X SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 LOGIC SYMBOL(1) 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 1A1 56 1 55 54 2 3 29 28 30 31 27 26 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 ≥1 5 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 7 1 2A3 2A4 2A5 2A6 2A7 2A8 ≥1 7 51 49 9 48 10 47 12 45 13 44 14 43 15 16 1B1 2 8 ≥1 8 13D 2A2 52 5 1 6D 6 4D 5 12 11D 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 12 1 14 1 14 ≥1 9 41 17 40 19 38 20 37 21 36 23 34 24 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 5 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 56 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 To Seven Other Channels 29 2OE 28 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 1D C1 To Seven Other Channels 6 2B1 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V VO Voltage range applied to any input/output when the output is in the high-impedance or power-off state (2) –0.5 4.6 V VO Voltage range applied to any input/output when the output is in the high or low state (2) (3) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 64 DGV package 48 –65 150 UNIT °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. The package thermal impedance is calculated in accordance with JESD 51. 7 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 Recommended Operating Conditions (1) VCC Supply voltage Operating VCC = 1.2 V VIH High-level input voltage MIN MAX 1.2 3.6 0.65 × VCC VCC = 1.65 V to 1.95 V 0.65 × VCC VCC = 3 V to 3.6 V Low-level input voltage 2 GND VCC = 1.4 V to 1.6 V 0.35 × VCC VCC = 1.65 V to 1.95 V 0.35 × VCC VCC = 2.3 V to 2.7 V Input voltage VO Output voltage IOHS Static high-level output current (2) 0.8 0 3.6 Active state 0 VCC 3-state 0 3.6 VCC = 1.4 V to 1.6 V –2 VCC = 1.65 V to 1.95 V –4 VCC = 2.3 V to 2.7 V –8 VCC = 3 V to 3.6 V IOLS Static low-level output current (2) ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (2) 8 V V mA –12 VCC = 1.4 V to 1.6 V 2 VCC = 1.65 V to 1.95 V 4 VCC = 2.3 V to 2.7 V 8 VCC = 3 V to 3.6 V (1) V 0.7 VCC = 3 V to 3.6 V VI V 1.7 VCC = 1.2 V VIL V VCC VCC = 1.4 V to 1.6 V VCC = 2.3 V to 2.7 V UNIT mA 12 VCC = 1.4 V to 3.6 V –40 5 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 3.3-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009. SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOHS = –100 µA VOH 1.2 V to 3.6 V II Control inputs Ioff IOZ (2) ICC VIH = 0.91 V 1.4 V IOHS = –4 mA, VIH = 1.07 V 1.65 V 1.2 IOHS = –8 mA, VIH = 1.7 V 2.3 V 1.75 IOHS = –12 mA, VIH = 2 V 3V 2.3 1.2 V to 3.6 V 0.2 1.4 V 0.4 IOLS = 4 mA, VIL = 0.57 V 1.65 V 0.45 IOLS = 8 mA, VIL = 0.7 V 2.3 V 0.55 IOLS = 12 mA, VIL = 0.8 V 3V 0.7 VI = VCC or GND 3.6 V ±2.5 µA VI or VO = 3.6 V 0 ±10 µA V VO = VCC or GND, VI = VCC 3.6 V ±12.5 µA VI = VCC or GND, IO = 0 3.6 V 40 µA Control inputs (1) (2) V VIL = 0.49 V VI = VCC or GND A or B ports UNIT IOLS = 2 mA, CLK inputs Cio MAX 1.05 2.5 V Ci TYP (1) VCC – 0.2 IOHS = –2 mA, IOLS = 100 µA VOL MIN VO = VCC or GND 3 3.3 V 3 2.5 V 3.5 3.3 V 3.5 2.5 V 8 3.3 V 8 pF pF Typical values are measured at TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6) VCC = 1.2 V MIN fclock Clock frequency tw Pulse duration CLKAB or CLKBA high or low tsu Setup time A before CLKAB↑ or B before CLKBA↑ 2.1 th Hold time A after CLKAB↑ or B after CLKBA↑ 1.3 MAX VCC = 1.5 V ± 0.1 V MIN MAX VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 250 UNIT MAX 350 MHz 3.3 2 1.4 ns 1.6 1.2 0.9 0.8 ns 1 0.8 0.6 0.6 ns 9 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 through Figure 6) PARAMETER VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 3.3 V ± 0.3 V TO (OUTPUT) VCC = 1.2 V TYP MIN MAX A or B B or A 4.2 1.6 4.8 1.5 4.3 1.2 3.1 0.9 2.6 CLKAB or CLKBA A or B 5.9 2.2 7.4 1.9 6.1 1.3 4 1 3.3 4 fmax tpd VCC = 2.5 V ± 0.2 V FROM (INPUT) MIN MAX 150 SAB or SBA MIN MAX 250 MIN UNIT MAX 350 MHz ns 8.2 2.6 10 2.4 6.3 1.8 5.1 1.5 ten OE A or B 6.5 2.2 8 1.9 7 1.4 4.6 1.1 4 ns tdis OE A or B 6.7 2.6 8 2.6 7.2 1.4 4.3 1.4 4.2 ns ten DIR A or B 6.9 2.2 8.7 1.9 7.4 1.4 5 1.1 4.3 ns tdis DIR A or B 7.5 2.6 8.7 2.6 7.6 1.4 4.5 1.4 4.3 ns Operating Characteristics TA = 25°C PARAMETER Cpd 10 Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0, f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 62 73 120 25 29 34 UNIT pF SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V ± 0.1 V 2 × VCC S1 2 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 15 pF (see Note A) 2 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.1 V VOL tPHZ VOH VCC/2 VOH − 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 11 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 12 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 13 SN74AVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES181F – DECEMBER 1998 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw LOAD CIRCUIT VCC VCC Timing Input Input VCC/2 VCC/2 0V VCC/2 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC Output Control (low-level enabling) VCC/2 0V tPZL VCC Input VCC/2 VCC/2 0V tPLH VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 VOL + 0.3 V VOL tPZH VOH Output Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 Output Waveform 2 S1 at GND (see Note B) tPHZ VCC/2 VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 6. Load Circuit and Voltage Waveforms 14 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74AVC16646DGVR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CVA646 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of