SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
D
D
D
D
Member of the Texas Instruments
Widebus Family
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V VCC
D
D
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
– Output Voltage – V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL – Output Voltage – V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
VCC = 2.5 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL – Output Current – mA
136
153
170
VCC = 1.8 V
–160 –144 –128 –112 –96 –80 –64 –48
IOH – Output Current – mA
–32
–16
0
Figure 1. Output Voltage vs Output Current
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low
logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE
is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC and Widebus are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
ORDERING INFORMATION
TA
–40°C
40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AVC16835DGGR
AVC16835
TVSOP – DGV
Tape and reel
SN74AVC16835DGVR
CVA835
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
2
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SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
FUNCTION TABLE
(each universal bus driver)
INPUTS
LE
CLK
A
OUTPUT
Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
OE
Y0†
† Output level before the indicated steady-state
input conditions were established, provided
that CLK is high before LE goes low
L
L
L or H
X
logic diagram (positive logic)
OE
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
CLK
To 17 Other Channels
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3
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4
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SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VCC
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VI
VO
IOHS
IOLS
Low-level input voltage
Output voltage
Static high-level
high level output current†
low level output current†
Static low-level
V
2
GND
0.35 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input voltage
V
1.7
VCC = 1.2 V
VCC = 1.4 V to 1.6 V
VIL
UNIT
V
0.7
0.8
0
3.6
V
Active state
0
3-state
0
VCC
3.6
V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
–8
–4
mA
–12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
8
4
mA
12
∆t/∆v
Input transition rise or fall rate
VCC = 1.4 V to 3.6 V
5
ns/V
TA
Operating free-air temperature
–40
85
°C
† Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH
characteristics. Refer to TI application reports AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic
Output Control (DOC ) Circuitry Technology and Applications, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
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5
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA,
IOHS = –2 mA,
VOH
VIH = 0.91 V
VIH = 1.07 V
IOHS = –4 mA,
IOHS = –8 mA,
IOLS = 2 mA,
IOLS = 4 mA,
VIL = 0.49 V
VIL = 0.57 V
IOLS = 8 mA,
IOLS = 12 mA,
VIL = 0.7 V
VIL = 0.8 V
VI = VCC or GND
VI or VO = 3.6 V
IOZ
ICC
VO = VCC or GND,
VI = VCC or GND,
Ci
Co
MIN
TYP†
VI = VCC or GND
Data inputs
VI = VCC or GND
Outputs
Out
uts
VO = VCC or GND
UNIT
1.65 V
1.2
2.3 V
1.75
3V
2.3
V
0.2
1.4 V
0.4
1.65 V
0.45
2.3 V
0.55
V
3V
0.7
3.6 V
±2.5
µA
0
±10
µA
OE = VCC
3.6 V
±10
µA
IO = 0
3.6 V
40
µA
VI = VCC or GND
Control inputs
MAX
VCC–0.2
1.05
1.4 V to 3.6 V
II
Ioff
CLK input
1.4 V
VIH = 1.7 V
VIH = 2 V
IOHS = –12 mA,
IOLS = 100 µA
VOL
VCC
1.4 V to 3.6 V
2.5 V
4
3.3 V
4
2.5 V
4
3.3 V
4
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
F
† Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
MIN
fclock
MAX
MIN
Pulse
duration
tsu
Setup
S
t
time
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
3.3
3.3
CLK high or low
3.3
3.3
3.3
Data
before LE↓
CLK high
CLK low
Data
after LE↓
1
0.9
0.7
0.7
0.7
1.7
1.6
1.2
0.8
0.8
2
0.9
0.7
0.5
0.5
1.5
1.3
1
0.9
1.3
CLK high
3.2
2.4
2
1.7
1.6
CLK low
2.8
2.1
1.7
1.5
1.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
150
3.3
Data after CLK↑
Hold
H
ld
time
MAX
VCC = 2.5 V
± 0.2 V
LE high
Data before CLK↑
6
MIN
VCC = 1.8 V
± 0.15 V
Clock frequency
tw
th
MAX
VCC = 1.5 V
± 0.1 V
MHz
ns
ns
ns
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 1.2 V
TYP
VCC = 1.5 V
± 0.1 V
MIN
VCC = 1.8 V
± 0.15 V
MAX
fmax
MIN
VCC = 2.5 V
± 0.2 V
MAX
150
A
tpd
LE
Y
CLK
ten
tdis
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
4.5
1.2
6.2
1.3
5.5
1
3.1
0.9
2.5
6.2
1.6
9.4
1.3
7.2
1.1
4.7
0.9
3.8
5.2
1.6
7.8
1.5
6
1
3.7
0.8
3.1
ns
OE
Y
7.1
2.4
10.2
2.2
8.8
1.5
6.7
1.2
6.2
ns
OE
Y
6.9
2.2
10.3
2
8.4
1.2
5.3
1.1
5.3
ns
switching characteristics, TA = 0°C to 85°C, CL = 0 pF†
FROM
(INPUT)
PARAMETER
A
tpd
d
VCC = 3.3 V
± 0.15 V
TO
(OUTPUT)
Y
CLK
MIN
MAX
0.6
1.3
0.7
1.5
UNIT
ns
† Texas Instruments SPICE simulation data
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0
0,
POST OFFICE BOX 655303
VCC = 1.8 V
TYP
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
45
48
52
23
25
28
UNIT
pF
7
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
GND
CL = 15 pF
(see Note A)
2 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.1 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
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SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
From Output
Under Test
2 × VCC
S1
1 kΩ
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VOH
VCC/2
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AVC16835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES168J – DECEMBER 1998 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
VCC/2
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
tPLZ
VCC
VCC/2
VOL + 0.3 V
VOL
tPZH
tPHL
VOH
Output
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VCC/2
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74AVC16835DGVR
ACTIVE
TVSOP
DGV
56
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CVA835
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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