SN74CBT3305CD

SN74CBT3305C DUAL FET BUS SWITCH 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS125B – SEPTEMBER 2003 – REVISED AUGUST 2005 FEATURES • • • • • • • • Undershoot Protection for OFF Isolation on A and B Ports up to –2 V Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Ω Typ) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5 pF Typ) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) • • • • • Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, ClassII ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Bus Isolation, Low-Distortion Signal Gating xxx xxx D, DGK, OR PW PACKAGE (TOP VIEW) 1OE 1A 1B GND 1 8 2 7 3 6 4 5 VCC 2OE 2B 2A DESCRIPTION/ORDERING INFORMATION The SN74CBT3305C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active undershoot-protection circuitry on the A and B ports of the device provides protection for undershoot up to –2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT3305C is organized as two 1-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is ON, and the A port is conncected to the B port, allowing bidirectional data flow between ports. When OE is low, the associated 1-bit bus switch is OFF, and the high-impedance state exists between the A and B ports. ORDERING INFORMATION PACKAGE (1) TA SOIC – D –40°C to 85°C VSSOP – DGK TSSOP – PW (1) ORDERABLE PART NUMBER Tube SN74CBT3305CD Tape and reel SN74CBT3305CDR Tape and reel SN74CBT3305CDGKR Tube SN74CBT3305CPW Tape and reel SN74CBT3305CPWR TOP-SIDE MARKING CU305C SNR CU305C Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated SN74CBT3305C DUAL FET BUS SWITCH 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS125B – SEPTEMBER 2003 – REVISED AUGUST 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This device is fully specified for partial-power-down application using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. FUNCTION TABLE (EACH BUS SWITCH) INPUT OE INPUT/OUTPUT A FUNCTION H B A port = B port L Z Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 1A 1OE 3 1B SW 1 5 2A 6 SW 2B 7 2OE SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW) A B UndershootProtection Circuit EN(1) (1) 2 EN is the internal enable signal applied to the switch. SN74CBT3305C DUAL FET BUS SWITCH 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS125B – SEPTEMBER 2003 – REVISED AUGUST 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage –0.5 7 V VIN Control input voltage range (2) (3) –0.5 7 V VI/O Switch I/O voltage range (2) (3) (4) IIK Control input clamp current VIN < 0 –50 mA II/OK I/O port clamp current VI/O < 0 –50 mA ±128 mA ±100 mA II/O ON-state switch –0.5 current (5) Continuous current through VCC or GND D package θJA Tstg (1) (2) (3) (4) (5) (6) Package thermal impedance (6) Storage temperature range 7 UNIT V 97 DGK package 179 PW package 149 –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN MAX VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 5.5 V VIL Low-level control input voltage 0 0.8 V VI/O Data input/output voltage 0 5.5 V TA Operating free-air temperature –40 85 °C (1) UNIT All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74CBT3305C DUAL FET BUS SWITCH 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS125B – SEPTEMBER 2003 – REVISED AUGUST 2005 Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK MIN TYP (2) TEST CONDITIONS Control inputs VCC = 4.5 V, IIN = –18 mA VIKU Data inputs VCC = 5 V, 0 mA > II ≥ –50 mA, VIN = VCC or GND, IIN Control inputs VCC = 5.5 V, VIN = VCC or GND IOZ (3) VCC = 5.5 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 VCC = 5.5 V, II/O = 0, VIN = VCC or GND, Switch ON or OFF One input at 3.4 V, Other inputs at VCC or GND ICC ∆ICC (4) Control inputs VCC = 5.5 V, Cin Control inputs VIN = 3 V or 0 Switch OFF MAX UNIT –1.8 V –2 V ±1 µA ±10 µA 10 µA 3 µA 2.5 mA 3 pF Cio(OFF) VI/O = 3 V or 0, Switch OFF, VIN = VCC or GND 5 pF Cio(ON) VI/O = 3 V or 0, Switch ON, VIN = VCC or GND 12.5 pF VCC = 4 V, TYP at VCC = 4 V VI = 2.4 V, IO = –15 mA 8 12 IO = 64 mA 3 6 IO = 30 mA 3 6 IO = –15 mA 5 10 ron (5) VI = 0 VCC = 4.5 V VI = 2.4 V, (1) (2) (3) (4) (5) Ω VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND Measured by the voltage drop between the A and B terminals at the indicate current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) (1) VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) tpd (1) A or B B or A 0.24 ten OE A or B 4.4 tdis OE A or B 5.1 PARAMETER MAX UNIT MAX 0.15 ns 1.5 4.1 ns 1.5 4.8 ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Undershoot Characteristics See Figure 1 and Figure 2 PARAMETER VOUTU (1) 4 TEST CONDITIONS VCC = 5.5 V, Switch OFF, VIN = VCC or GND All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. MIN TYP (1) 2 VOH – 0.3 MAX UNIT V SN74CBT3305C DUAL FET BUS SWITCH 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS125B – SEPTEMBER 2003 – REVISED AUGUST 2005 VCC Input Generator 11 V 100 kΩ 50 Ω Ax DUT Bx 100 kΩ VS 10 pF Figure 1. Device Test Setup Input (Open Socket) 90 % 90 % 2 ns 5.5 V 2 ns 10 % 10 % −2 V 20 ns Output (VOUTU) VOH VOH − 0.3 Figure 2. Transient Input Voltage (VI) and Output Voltage (VOUTU) Waveforms (Switch OFF) 5 SN74CBT3305C DUAL FET BUS SWITCH 5-V BUS SWITCH WITH –2-V UNDERSHOOT PROTECTION www.ti.com SCDS125B – SEPTEMBER 2003 – REVISED AUGUST 2005 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 7V Input Generator S1 RL VO VI 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 50 pF 50 pF tPLZ/tPZL 5 V ± 0.5 V 4V 7V 7V 500 Ω 500 Ω GND GND 50 pF 50 pF 0.3 V 0.3 V tPHZ/tPZH 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC VCC 50 pF 50 pF 0.3 V 0.3 V V∆ 3V Output Control (VIN) 1.5 V 3V 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V VOL + V∆ VOL tPZH tPHL 1.5 V 0V tPZL Output Control (VIN) Open GND Output Waveform 2 S1 at Open (see Note B) tPHZ VOH 1.5 V VOH − V∆ 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CBT3305CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU305C SN74CBT3305CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU305C SN74CBT3305CPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU305C SN74CBT3305CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU305C SN74CBT3305CPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CU305C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of