SN74F2373DWE4

SN74F2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SDFS100 – JANUARY 1996 D D D D D DB, DW, OR N PACKAGE (TOP VIEW) Eight Latches in a Single Package 3-State True Outputs With 25-Ω Sink Resistors Full Parallel Access for Loading Buffered Control Inputs Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB) Packages, and Plastic (N) DIPs OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description This 8-bit latch features 3-state outputs designed to sink up to 12 mA, and include 25-Ω sink resitors to reduce overshoot and undershoot. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE The eight latches of the SN74F2373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE input does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN74F373 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74F2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SDFS100 – JANUARY 1996 logic symbol† OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 logic diagram (positive logic) EN OE C1 1D 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 LE 1 11 1Q C1 2Q 1D 3Q 3 1D 4Q 5Q 6Q 7Q To Seven Other Channels 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. schematic diagram VCC Q 25 Ω (nominal) Typical Output Configuration 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 1Q SN74F2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SDFS100 – JANUARY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V Input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . – 0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating free-air temperature range,TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded if the input current ratings are observed. recommended operating conditions VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL High-level output current TA Operating free-air temperature High-level input voltage MIN NOM MAX UNIT 4.5 5 5.5 V 2 V Input clamp current Low-level output current 0 0.8 V – 18 mA –3 mA 12 mA 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4 4.5 5V VCC = 4.75 V, II = – 18 mA IOH = – 1 mA IOH = – 3 mA IOH = -1 mA to – 3 mA MIN TYP‡ 2.5 3.4 2.4 3.3 MAX UNIT – 1.2 V V 2.7 VOL VCC = 4 4.5 5V IOL = 1 mA IOL = 12 mA IOZ(H) VCC = 5.5 V, VO = 2.7 V 50 µA IOZ(L) VCC = 5.5 V, VO = 0.5 V – 50 µA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V 0.1 mA 20 µA IIL IOS§ VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VO = 0 – 0.6 mA – 150 mA ICC(H) VCC = 5.5 V, See Note 2, Condition A 38 55 mA ICC(L) VCC = 5.5 V, See Note 2, Condition B 46 66 mA 62 mA ICC(Z) 0.2 0.5 0.5 0.75 – 60 VCC = 5.5 V, See Note 2, Condition C 43 ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with the outputs open under the following conditions: A. OE at ground (0) and all other inputs at 4.5 V. B. LE at 4.5 V and all other inputs grounded. C. OE at 4.5 V and all other inputs grounded. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 3 SN74F2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SDFS100 – JANUARY 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C MIN MIN MAX UNIT MAX tw Pulse duration, LE high 6 6 ns tsu Setup time, data before LE↓ 2 2 ns th Hold time, data after LE↓ 5 6 ns switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, CL = 50 PF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C MIN TYP MAX VCC = 4.5 V TO 5.5 V, CL = 50 PF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN TO MAX† MIN MAX 2.2 4.4 7 2.1 9 1.2 4.1 5.5 1.2 7 4.2 7.3 11.5 4.2 13 2.2 4.2 7 2.2 8 1.2 4.1 11 1.2 12 1.2 6 8.3 1.2 9.5 1.2 4.2 6.5 1.2 7.5 1.2 3.5 6 1.2 6 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN74F2373 25-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SDFS100 – JANUARY 1996 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) From Output Under Test Test Point CL (see Note A) R1 From Output Under Test R1 Test Point CL (see Note A) R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS RL = R1 = R2 LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse (see Note C) 3V 1.5 V 0V tw 3V Timing Input (see Note C) 3V 1.5 V Low-Level Pulse 0V th tsu Data Input (see Note C) 1.5 V 1.5 V 0V 3V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enable) 3V Input (see Note C) 1.5 V 1.5 V 1.5 V 0V tPZL 1.5 V tPLZ 0V tPLH In-Phase Output (see Note E) tPHL 1.5 V Out-of-Phase Output (see Note E) VOL 1.5 V VOL tPHZ VOH 1.5 V 1.5 V 0.3 V tPZH tPLH tPHL 3.5 V Waveform 1 (see Notes B and E) VOH Waveform 2 (see Notes B and E) VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D) 1.5 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is open. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 28-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74F2373DBLE OBSOLETE SSOP DB 20 SN74F2373DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F2373N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74F2373NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-May-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74F2373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74F2373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74F2373DBR SN74F2373DWR SSOP DB 20 2000 346.0 346.0 33.0 SOIC DW 20 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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