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SN74GTLPH1616DGGR

SN74GTLPH1616DGGR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    TSSOP64_17X6.1MM

  • 描述:

    IC UNIV BUS TXRX 17BIT 64TSSOP

  • 数据手册
  • 价格&库存
SN74GTLPH1616DGGR 数据手册
SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 D D D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) Member of Texas Instruments’ Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels GTLP Buffered CLKAB Signal (CLKOUT) LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) OEAB LEAB A1 A2 GND A3 VCC A4 A5 GND A6 A7 A8 GND A9 VCC A10 GND A11 A12 GND A13 A14 GND A15 VCC A16 ERC A17 CLKIN OEBA LEBA 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 CEAB CLKAB B1 B2 GND B3 BIAS VCC B4 B5 GND B6 B7 B8 GND B9 VCC B10 GND B11 B12 GND B13 B14 GND B15 VREF B16 GND B17 CLKOUT CLKBA CEBA description The SN74GTLPH1616 is a high-drive, 17-bit UBT transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion of a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing ( VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 V VCC 5.5 V B port Except B port B port ERC Except B port and ERC VREF+0.05 VCC–0.6 Low-level input voltage GND ERC Except B port and ERC IIK IOH Input clamp current IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate High-level output current VREF–0.05 0.6 V 0.8 A port –18 mA –24 mA A port 24 B port 100 Outputs enabled 10 –40 mA ns/V µs/V 20 Operating free-air temperature V 2 B port VIL V 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. 6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. 7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3 3.15 15 V IOH = –12 mA IOH = –24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3 3.15 15 V VOL B port II Control inputs A port IOZH‡ B port MIN VCC = 3.15 V VCC = 3.45 V, VCC = 3 3.45 45 V TYP† MAX UNIT –1.2 V VCC–0.2 2.4 V 2 IOL = 100 µA IOL = 12 mA 0.2 IOL = 24 mA IOL = 10 mA 0.5 0.4 0.2 IOL = 64 mA IOL = 100 mA 0.55 VI = 0 or 5.5 V ±10 0.4 VO = VCC 10 VO = 1.5 V 10 IOZL‡ IBHL§ A and B ports VCC = 3.45 V, VO = GND A port IBHH¶ A port VCC = 3.15 V, VCC = 3.15 V, VI = 0.8 V VI = 2 V IBHLO# IBHHO|| A port VCC = 3.45 V, VCC = 3.45 V, VI = 0 to VCC VI = 0 to VCC 45 A or B port VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND Outputs high ICC Outputs low 45 Outputs disabled 45 A port Ci Ciio –10 Control inputs A port B port or CLKOUT µA µA µA 75 µA –75 µA 500 µA –500 µA VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ∆ICCk V VI = 3.15 V or 0 VO = 3.15 V or 0 VO = 1.5 V or 0 VO = 3.15 V or 0 mA 1.5 mA pF 4 5.5 6.5 8 9.5 11.5 pF Co CLKIN 4.5 5.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameters IOZH and IOZL include the input leakage current. § The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. ¶ The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. k This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. hot-insertion specifications for A port over recommended operating free-air temperature range PARAMETER 8 TEST CONDITIONS MIN MAX UNIT 10 µA VO = 0.5 V to 3 V, VI or VO = 0 to 5.5 V OE = 0 ±30 µA VO = 0.5 V to 3 V, OE = 0 ±30 µA Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS BIAS VCC = 0, ±30 µA BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA BIAS VCC = 3 3.15 15 V to 3 3.45 45 V V, VO (B port) = 0 to 1.5 15V BIAS VCC = 3.3 V IO = 0 VO (B port) = 0.6 V IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V VO IO VCC = 0, UNIT µA BIAS VCC = 0, VCC = 3.15 V to 3.45 V VCC = 0, MAX 10 VCC = 0, VCC = 0 to 1.5 V, ICC (BIAS VCC) MIN VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 Ioff IOZPU BIAS VCC = 3.15 V to 3.45 V, 0.95 5 mA 10 µA 1.05 V µA –1 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (normal mode) (unless otherwise noted) MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time POST OFFICE BOX 655303 LEAB or LEBA high 3 CLKAB or CLKBA high or low 3 A before CLKAB↑ 2.2 B before CLKBA↑ 2.4 A before LEAB↓, CLK = Don’t care 1.8 B before LEBA↓, CLK = Don’t care 2.1 CEAB before CLKAB↑ 1.5 CEBA before CLKBA↑ 1.5 A after CLKAB↑ 0.7 B after CLKBA↑ 0.5 A after LEAB↓, CLK = Don’t care 1.2 B after LEBA↓, CLK = Don’t care 0.9 CEAB after CLKAB↑ 1.5 CEBA after CLKBA↑ 1.5 • DALLAS, TEXAS 75265 MAX UNIT 175 MHz ns ns ns 9 SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (normal mode) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis FROM (INPUT) TO (OUTPUT) EDGE RATE† A B Slow A B Fast LEAB B Slow LEAB B Fast CLKAB B Slow CLKAB B Fast CLKAB CLKOUT Slow CLKAB CLKOUT Fast OEAB B or CLKOUT Slow OEAB B or CLKOUT Fast time B outputs (20% to 80%) Rise time, tf Fall time, time B outputs (80% to 20%) 4.3 5.6 7.1 3.2 4.6 6.4 3.2 4.3 5.6 2.7 3.9 5.3 4.8 6.2 7.8 3.5 4.9 6.7 3.5 4.8 6.2 3.1 4.3 5.8 4.8 6.1 7.6 3.5 4.8 6.6 3.6 4.9 6.2 3.1 4.3 5.7 5.5 6.9 8.5 5.5 7 9.3 4 5.3 6.7 4.4 5.8 7.6 4.8 6.2 7.8 3.4 5.2 7.8 3.6 4.8 6.2 3 4.4 6.1 2.5 Fast 1.4 Slow 3.3 Fast 2.4 B A — tPLH tPHL LEBA A — tPLH tPHL CLKBA A — tPLH tPHL CLKOUT CLKIN — OEBA A or CLKIN — POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz Slow tPLH tPHL † Slow (ERC = GND) and Fast (ERC = VCC) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. 10 MAX 175 tr ten tdis TYP‡ MIN ns ns ns ns ns ns ns ns ns ns ns ns 1.1 2.8 4.3 1.9 3.1 4.1 1.3 3.1 4.6 1.4 2.6 3.8 1.3 3.3 4.8 1.8 2.9 4.1 2.2 3.7 5.3 2.7 3.9 5.1 1.2 2.9 4.8 2.3 4 5.5 ns ns ns ns ns SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 Ω From Output Under Test S1 Open CL = 50 pF (see Note A) 500 Ω 12.5 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th VOH Data Input VM VM 0V 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES (VM = 1.5 V for A port and 1 V for B port) (VOH = 3 V for A port and 1.5 V for B port) VOH Output 1V 1V 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 1V 0V tPLH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V tPZL 1.5 V Input Output Control 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (see Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 22 Ω .25” ZO = 50 Ω 1” Conn. 1” Conn. 1” Conn. 1” 1” .25” 22 Ω 1.5 V 1.5 V 1.5 V 11 Ω Conn. From Output Under Test 1” Rcvr Rcvr Rcvr Slot 2 Slot 19 Slot 20 LL = 14 nH Test Point CL = 18 pF Drvr Slot 1 Figure 2. High-Drive Test Backplane 12 POST OFFICE BOX 655303 Figure 3. High-Drive RLC Network • DALLAS, TEXAS 75265 SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES346C– JANUARY 2001 – REVISED AUGUST 2001 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) EDGE RATE† tPLH tPHL A B Slow tPLH tPHL A B Fast tPLH tPHL LEAB B Slow tPLH tPHL LEAB B Fast tPLH tPHL CLK B Slow tPLH tPHL CLK B Fast tPLH tPHL CLKAB CLKOUT Slow tPLH tPHL CLKAB CLKOUT Fast ten tdis OEAB B or CLKOUT Slow ten tdis OEAB B or CLKOUT Fast tr Rise time, time B outputs (20% to 80%) tf Fall time, time B outputs (80% to 20%) TYP‡ 5.3 5.3 4 4 5.2 5.2 3.9 3.9 5.5 5.5 4.3 4.3 5.9 5.9 4.8 4.8 5.7 4.3 4.3 3.8 Slow 2 Fast 1.2 Slow 2.5 Fast 1.8 UNIT ns ns ns ns ns ns ns ns ns ns ns ns † Slow (ERC = GND) and Fast (ERC = VCC) ‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2002, Texas Instruments Incorporated
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