SN74HC163DR


  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 D D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable SN54HC163 . . . J OR W PACKAGE SN74HC163 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD SN54HC163 . . . FK PACKAGE (TOP VIEW) description/ordering information CLK CLR NC VCC RCO These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QA QB NC QC QD ENP GND NC LOAD ENT A B NC C D NC − No internal connection ORDERING INFORMATION PACKAGE† TA PDIP − N SN74HC163N Tube of 40 SN74HC163D Reel of 2500 SN74HC163DR Reel of 250 SN74HC163DT SOP − NS Reel of 2000 SN74HC163NSR HC163 SSOP − DB Reel of 2000 SN74HC163DBR HC163 Tube of 90 SN74HC163PW Reel of 2000 SN74HC163PWR Reel of 250 SN74HC163PWT CDIP − J Tube of 25 SNJ54HC163J SNJ54HC163J CFP − W Tube of 150 SNJ54HC163W SNJ54HC163W TSSOP − PW −55°C −55 C to 125 125°C C TOP-SIDE MARKING Tube of 25 SOIC − D −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER SN74HC163N HC163 HC163 LCCC − FK Tube of 55 SNJ54HC163FK SNJ54HC163FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated    ! "#$ !  %#&'" ($) (#"! "  !%$""! %$ *$ $!  $+! !#$! !(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!)  %(#"! "%'  /01 2  '' %$$! $ $!$( #'$!! *$,!$ $()  '' *$ %(#"! %(#" %"$!!. ($!  $"$!!'- "'#($ $!.  '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 description/ordering information (continued) These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR 2 1 CK LD R A B C D M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 G4 D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the logic diagram of the overall device. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CK† TG CK† 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (synchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC163 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v‡ Low-level input voltage MIN NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage 0 Input transition rise/fall time SN74HC163 VCC = 2 V VCC = 4.5 V VCC = 6 V 0.5 1.35 1.35 1.8 1.8 0 0 V V 0.5 VCC VCC UNIT VCC VCC 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25°C TYP MAX MIN MAX SN74HC163 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 3 10 10 10 pF 6V Ci SN54HC163 2 V to 6 V V timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock tw Clock frequency Pulse duration CLK high or low A, B, C, or D LOAD low tsu Setup time before CLK↑ ENP, ENT CLR low CLR inactive th Hold time, all synchronous inputs after CLK CLK↑ POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HC163 MIN MAX SN74HC163 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 150 225 190 4.5 V 30 45 38 6V 26 38 32 2V 135 205 170 4.5 V 27 41 34 6V 23 35 29 2V 170 255 215 4.5 V 34 51 43 6V 29 43 37 2V 160 240 200 4.5 V 32 48 40 6V 27 41 34 2V 160 240 200 4.5 V 32 48 40 6V 27 41 34 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns 7 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax RCO CLK tpd Any Q ENT tt RCO Any VCC MIN TA = 25°C TYP MAX SN54HC163 MIN MAX SN74HC163 MIN 2V 6 14 4.2 5 4.5 V 31 40 21 25 6V 36 44 25 29 MAX UNIT MHz 2V 83 215 325 270 4.5 V 24 43 65 54 6V 20 37 55 46 2V 80 205 310 255 4.5 V 25 41 62 51 6V 21 35 53 43 2V 62 195 295 245 4.5 V 17 39 59 49 6V 14 33 50 42 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd 8 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 60 UNIT pF 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 APPLICATION INFORMATION n-bit synchronous counters This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter. The ’HC163 devices count in binary. Virtually any count mode (modulo-N, N1-to-N2, N1-to-maximum) can be used with this fast look-ahead circuit. The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and 4.5-V VCC). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in addition to the bipolar equivalents (LS, ALS, AS). 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 APPLICATION INFORMATION LSB CTR CT=0 M1 3CT=MAX G3 CLR Clear (L) LOAD ENT Count (H)/ Disable (L) ENP CLK RCO G4 C5/2,3,4+ Load (L) A 1,5D [1] QA Count (H)/ Disable (L) B [2] QB C [3] QC Clock D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD To More-Significant Stages Figure 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 APPLICATION INFORMATION n-bit synchronous counters (continued) The glitch on RCO is caused because the propagation delay of the rising edge of QA of the second stage is shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, QA, QB, QC, and QD (ENT × QA × QB × QC × QD). The resulting glitch is about 7−12 ns in duration. Figure 3 shows the condition in which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to other stages. QB, QC, and QD of the first and second stage are at logic one, and QA of both stages are at logic zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, QA and RCO of the first stage go high. On the rising edge of the third clock pulse, QA and RCO of the first stage return to a low level, and QA of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears because of the race condition inside the chip. 1 2 3 4 5 CLK ENT1 QB1, QC1, QD1 QA1 RCO1, ENT2 QB2, QC2, QD2 QA2 RCO2 Glitch (7−12 ns) Figure 3 The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (tg). In other words, fmax = 1/(tpd CLK-to-RCO + tg). For example, at 25°C at 4.5-V VCC, the clock-to-RCO propagation delay is 43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the cascaded counters can use is 18 MHz. The following tables contain the fclock, tw, and fmax specifications for applications that use more than two ’HC163 devices cascaded together. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  

 
SCLS298D − JANUARY 1996 − REVISED − OCTOBER 2003 APPLICATION INFORMATION n-bit synchronous counters (continued) timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock tw Clock frequency Pulse duration, CLK high or low TA = 25°C MIN MAX SN54HC163 MIN MAX SN74HC163 MIN MAX 2V 3.6 2.5 2.9 4.5 V 18 12 14 6V 21 14 17 2V 140 200 170 4.5 V 28 40 36 6V 24 36 30 UNIT MHz ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Note 4) PARAMETER FROM (INPUT) TO (OUTPUT) fmax VCC TA = 25°C MIN MAX SN54HC163 MIN MAX SN74HC163 MIN 2V 3.6 2.5 2.9 4.5 V 18 12 14 6V 21 14 17 MAX UNIT MHz NOTE 4: These limits apply only to applications that use more than two ’HC163 devices cascaded together. If the ’HC163 devices are used as a single unit, or only two cascaded together, then the maximum clock frequency that the devices can use is not limited because of the glitch. In these situations, the devices can be operated at the maximum specifications. A glitch can appear on RCO of a single ’HC163 device, depending on the relationship of ENT to CLK. Any application that uses RCO to drive any input, except an ENT of another cascaded ’HC163 device, must take this into consideration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 86076012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 86076012A SNJ54HC 163FK 8607601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8607601EA SNJ54HC163J JM38510/66304BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 66304BEA M38510/66304BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 66304BEA SN54HC163J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC163J SN74HC163D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC163N SN74HC163NE4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC163N SN74HC163NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SN74HC163PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC163 SNJ54HC163FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 86076012A SNJ54HC 163FK Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) SNJ54HC163J ACTIVE Package Type Package Pins Package Drawing Qty CDIP J 16 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD A42 N / A for Pkg Type Op Temp (°C) Device Marking (4/5) -55 to 125 8607601EA SNJ54HC163J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of