SN54HC259, SN74HC259
SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
SNx4HC259 8-Bit Addressable Latches
1 Features
2 Description
•
•
These 8-bit addressable latches are designed
for general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional devices
capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or
demultiplexer with active-high outputs.
•
•
•
•
•
•
•
•
•
•
Wide operating voltage range of 2 V to 6 V
High-current inverting outputs drive up to 10
LSTTL loads
Low power consumption, 80-μA max ICC
Typical tpd = 14 ns
±4-mA output drive at 5 V
Low input current of 1 μA max
8-bit parallel-out storage register performs serialto-parallel conversion with storage
Asynchronous parallel clear
Active-high decoder
Enable input simplifies expansion
Expandable for n-bit applications
Four distinct functional modes
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74HC259D
SOIC (16)
9.90 mm × 3.90 mm
SN74HC259N
PDIP (16)
19.31 mm × 6.35 mm
SN74HC259NS
SO (16)
6.20 mm × 5.30 mm
SN74HC259PW
TSSOP (16) 5.00 mm × 4.40 mm
SN54HC259J
CDIP (16)
24.38 mm × 6.92 mm
SNJ54HC259FK
LCCC (20)
8.89 mm × 8.45 mm
(1)
For all available packages, see the orderable addendum at
the end of the document.
Pin numbers are for the D, J, N, NS, PW, and W packages.
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HC259, SN74HC259
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(1) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Timing Requirements ................................................. 5
5.6 Switching Characteristics ...........................................6
5.7 Operating Characteristics........................................... 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2003) to Revision F (March 2022)
Page
• Updated the numbering, formatting, tables, figures, and cross-references thorughout the document to reflect
modern data sheet standards............................................................................................................................. 1
2
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
4 Pin Configuration and Functions
J, D, N, NS, or PW Package
16-Pin CDIP, SOIC, PDIP, SO, TSSOP
Top View
FK Package
20-Pin LCCC
Top View
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
Supply voltage range
current(2)
MIN
MAX
–0.5
7
UNIT
V
IIK
Input clamp
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(1)
SN54HC259
VCC
NOM
MAX
2
5
6
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 4.5 V
VI
Input voltage
VO
Output voltage
5
6
3.15
4.2
VCC = 4.5 V
0
Input transition rise/fall time VCC = 4.5 V
Operating free-air temperature
−55
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
0
VCC = 6 V
(1)
2
4.2
VCC = 2 V
TA
MAX
3.15
VCC = 6 V
tt
NOM
1.5
VCC = 2 V
Low-level input voltage
MIN
1.5
VCC = 6 V
VIL
SN74HC259
MIN
V
1.8
VCC
0
VCC
0
VCC
V
VCC
V
1000
1000
500
500
400
400
125
−40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
RθJA
(1)
4
Junction-to-ambient thermal
(1)
resistance
D (SOIC)
N (PDIP)
NS (SO)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
16 PINS
UNIT
73
67
64
108
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST
(1)
CONDITIONS
IOH = −20 μA
VOH
IOH = −4 mA
IOH = −5.2 mA
ICC
MAX
MIN
SN74HC259
MIN
TYP
MAX
MIN
2
1.9
1.998
1.9
1.9
4.5
4.4
4.499
4.4
4.4
6
5.9
5.999
5.9
5.9
4.5
3.98
4.3
3.7
3.84
6
5.48
5.8
5.2
5.34
MAX
UNIT
V
2
0.002
0.1
0.1
0.1
4.5
0.001
0.1
0.1
0.1
6
0.001
0.1
0.1
0.1
IOL = 4 mA
4.5
0.17
0.26
0.4
0.33
IOL = 5.2 mA
6
0.15
0.26
0.4
0.33
VI = VCC or 0
6
±0.1
±100
±1000
±1000
nA
VI = VCC or 0, IO
=0
6
8
160
80
μA
10
10
10
pF
Ci
(1)
SN54HC259
IOL = 20 μA
VOL
II
TA = 25°C
VCC (V)
2 to 6
3
V
VI = VIH or VIL, unless otherwise noted.
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC (V)
CLR low
tw
Pulse duration
G low
tsu
th
Setup time, data or address before G↑
Hold time, data or address after GG↑
TA = 25°C
MIN
SN54HC259
MAX
MIN
MAX
SN74HC259
MIN
2
80
120
100
4.5
16
24
20
6
14
20
17
2
80
120
100
4.5
16
24
20
6
14
20
17
2
75
115
95
4.5
15
23
19
6
13
20
16
2
5
5
5
4.5
5
5
5
6
5
5
5
MAX
UNIT
ns
ns
ns
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement
Information)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC (V)
tPHL
CLR
Any Q
Data
tpd
Any Q
Address
G
Any Q
Any Q
tt
Any
TA = 25°C
MIN
SN54HC259
MIN
SN74HC259
TYP
MAX
MAX
MIN
MAX
2
60
150
225
190
4.5
18
30
45
38
6
14
26
38
32
2
56
130
195
165
4.5
17
26
39
33
6
13
22
33
28
2
74
200
300
250
4.5
21
40
60
50
6
17
34
51
43
2
66
170
255
215
4.5
20
34
51
43
6
16
29
43
37
2
28
75
110
95
4.5
8
15
22
19
6
6
13
19
16
UNIT
ns
ns
ns
5.7 Operating Characteristics
TA = 25℃
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance per latch
No load
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TYP
33
UNIT
pF
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
From Output
Under Test
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
VCC
Input
50%
90%
tPLH
tPHL
10%
10%
0V
(1)
tr(1)
(1)
VOH
Output
50%
VOL
tPLH(1)
VOH
Output
50%
0V
tf(1)
90%
VOH
90%
Output
50%
tPHL(1)
VCC
90%
Input
50%
50%
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 6-3. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
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7 Detailed Description
7.1 Overview
These 8-bit addressable latches are designed for general-purpose storage applications in digital systems.
Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers.
They are multifunctional devices capable of storing single-line data in eight addressable latches and being a
1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the
addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch
follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode,
all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines are
changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input
with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.
7.2 Functional Block Diagram
8
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
Figure 7-1. Logic Diagram, Each Internal Latch (positive logic)
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS
CLR
G
OUTPUT OF
ADDRESSED
LATCH
H
L
D
QiO
H
H
QiO
QiO
Memory
L
L
D
L
8-line demultiplexer
L
H
L
L
Clear
EACH OTHER
OUTPUT
FUNCTION
Addressable latch
Table 7-2. Latch Selection Table
SELECT INPUTS
S2
S1
S0
LATCH
ADDRESSED
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
10
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SCLS134F – DECEMBER 1982 – REVISED MARCH 2022
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
85519012A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
85519012A
SNJ54HC
259FK
8551901EA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8551901EA
SNJ54HC259J
Samples
JM38510/65402BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65402BEA
Samples
M38510/65402BEA
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
JM38510/
65402BEA
Samples
SN54HC259J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
SN54HC259J
Samples
SN74HC259D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259DG4
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259DRE4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259DRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259DT
ACTIVE
SOIC
D
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC259N
Samples
SN74HC259NE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC259N
Samples
SN74HC259NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SN74HC259PWT
ACTIVE
TSSOP
PW
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC259
Samples
SNJ54HC259FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
85519012A
SNJ54HC
259FK
Addendum-Page 1
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54HC259J
ACTIVE
CDIP
J
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
8551901EA
SNJ54HC259J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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