SN74HC540PWT

SN54HC540, SN74HC540 SCLS007F – MARCH 1984 – REVISED JULY 2022 SNx4HC540 Octal Buffers and Line Drivers With 3-State Outputs 1 Features 2 Description • • These octal buffers and line drivers feature the performance of the popular ’HC240 series and offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. • • • • • Wide operating voltage range of 2 V to 6 V High-current 3-state outputs drive bus lines directly or up to 15 LSTTL loads Low power consumption, 80-μA max ICC Typical tpd = 8 ns ±6-mA output drive at 5 V Low input current of 1 μA max Data flow-through pinout (all inputs on opposite side from outputs) The 3-state control gate is a 2-input NOR. If either output-enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state. The ’HC540 devices provide inverted data at the outputs. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) SN54HC540J CDIP (20) 26.92 mm × 6.92 mm SN74HC540DW SOIC (20) 12.80 mm × 7.50 mm SN74HC540N PDIP (20) 25.40 mm × 6.35 mm SN74HC540NSR SO (20) 15.00 mm × 5.30 mm SN74HC540PW TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 5.2 Recommended Operating Conditions(1) .................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics ...........................................5 5.6 Switching Characteristics............................................6 5.7 Operating Characteristics........................................... 6 6 Parameter Measurement Information............................ 7 7 Detailed Description........................................................8 7.1 Overview..................................................................... 8 7.2 Functional Block Diagram........................................... 8 7.3 Device Functional Modes............................................8 8 Power Supply Recommendations..................................9 9 Layout...............................................................................9 9.1 Layout Guidelines....................................................... 9 10 Device and Documentation Support..........................10 10.1 Receiving Notification of Documentation Updates..10 10.2 Support Resources................................................. 10 10.3 Trademarks............................................................. 10 10.4 Electrostatic Discharge Caution..............................10 10.5 Glossary..................................................................10 11 Mechanical, Packaging, and Orderable Information.................................................................... 10 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January 2022) to Revision F (July 2022) Page • Junction-to-ambient thermal resistance values increased. DW was 58 is now 109.1, N was 69 is now 84.6, NS was 60 is now 113.4, PW was 83 is now 131.8............................................................................................ 4 Changes from Revision D (August 2003) to Revision E (January 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 4 Pin Configuration and Functions J, DW, N, NS, PW package 20-Pin CDIP, SOIC, PDIP, SO, TSSOP Top View FK Package 20-Pin CDIP Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 3 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 5 Specifications 5.1 Absolute Maximum Ratings overoperating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range current(2) MIN MAX –0.5 7 UNIT V IIK Input clamp VI < 0 or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±35 mA ±70 mA 150 ℃ 150 ℃ 300 ℃ Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature range –65 Lead temperature (Soldering 10s) (SOIC - Lead Tips Only) (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 5.2 Recommended Operating Conditions(1) SN54HC540 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 Low-level input voltage UNIT V V 4.2 VCC = 2 V VIL SN74HC540 VCC = 4.5 V VCC = 6 V 0.5 0.5 1.35 1.35 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V Δt/Δv Input transition rise/fall time TA Operating free-air temperature VCC = 2 V VCC = 4.5 V VCC = 6 V (1) 1000 1000 500 500 400 −55 ns 400 125 −40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5.3 Thermal Information THERMAL METRIC 4 DW (SOIC) N (PDIP) NS (SO) PW (TSSOP) 20 PINS 20 PINS 20 PINS 20 PINS UNIT 109.1 84.6 113.4 131.8 °C/W 76 72.5 78.6 72.2 °C/W RθJA Junction-to-ambient thermal (1) resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance 77.6 65.3 78.4 82.8 °C/W ψJT Junction-to-top characterization parameter 51.5 55.3 47.1 21.5 °C/W ψJB Junction-to-board characterization parameter 77.1 65.2 78.1 82.4 °C/W Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 5.3 Thermal Information (continued) THERMAL METRIC RθJC(bot) (1) DW (SOIC) N (PDIP) NS (SO) PW (TSSOP) 20 PINS 20 PINS 20 PINS 20 PINS UNIT N/A N/A N/A N/A °C/W Junction-to-case (bottom) thermal resistance For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. 5.4 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 μA VOH SN54HC540 TYP 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 IOH = −7.8 mA MAX MIN SN74HC540 MIN VI = VIH or VIIL IOH = −6 mA VOL TA = 25°C VCC MAX MIN MAX V 2V 0.002 0.1 0.1 0.1 IOL = 20 μA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 VI = VIH or VIL IOL = 7.8 mA UNIT V II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0 6V ±0.01 ±0.5 ±10 ±5 μA ICC VI = VCC or 0, 8 160 80 μA 3 10 10 10 pF IO = 0 Ci 6V 2 V to 6 V 5.5 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6-1) PARAMETER tpd ten tdis tt FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y Y VCC TA = 25°C MIN SN54HC540 MIN SN74HC540 TYP MAX MAX MIN MAX 2V 35 100 149 125 4.5 V 10 20 30 25 6V 8 17 25 21 2V 75 150 224 188 4.5 V 15 30 45 38 6V 13 26 38 32 2V 40 150 224 188 4.5 V 18 30 45 38 6V 17 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 UNIT ns ns ns ns Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 5 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 5.6 Switching Characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 6-1) PARAMETER tpd ten FROM (INPUT) TO (OUTPUT) A Y OE Y tt Y VCC TA = 25°C MIN SN54HC540 MIN SN74HC540 TYP MAX MAX MIN 2V 60 150 224 188 4.5 V 15 30 45 38 6V 13 26 38 32 UNIT MAX 2V 100 200 298 250 4.5 V 20 40 60 50 6V 17 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 ns ns ns 5.7 Operating Characteristics TA = 25℃ PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance per buffer/driver No load Submit Document Feedback TYP 35 UNIT pF Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 6 Parameter Measurement Information A. B. C. D. E. F. G. CL includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. The outputs are measured one at a time with one input transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tpd. Figure 6-1. Load Circuit and Voltage Waveforms Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 7 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 7 Detailed Description 7.1 Overview These octal buffers and line drivers feature the performance of the popular ’HC240 series and offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. The 3-state control gate is a 2-input NOR. If either output-enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state. The ’HC540 devices provide inverted data at the outputs. 7.2 Functional Block Diagram 7.3 Device Functional Modes Table 7-1. Function Table (Each Buffer/Driver) INPUTS 8 A OUTPUT Y L L H L H L H X X Z X H X Z OE1 OE2 L L Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 9 SN54HC540, SN74HC540 www.ti.com SCLS007F – MARCH 1984 – REVISED JULY 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HC540 SN74HC540 PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) JM38510/65710BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65710BRA Samples M38510/65710BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65710BRA Samples SN54HC540J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC540J Samples SN74HC540DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540DWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC540N Samples SN74HC540NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540PWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SN74HC540PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC540 Samples SNJ54HC540J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ54HC540J Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2022 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of