SN74HC74ADBR

SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B – DECEMBER 1982 – REVISED MAY 1997 D SN54HC74 . . . J OR W PACKAGE SN74HC74 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1CLR 1D 1CLK 1PRE 1Q 1Q GND description The ’HC74 contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLR NC VCC 2CLR SN54HC74 . . . FK PACKAGE (TOP VIEW) 1CLK NC 1PRE NC 1Q 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q The SN54HC74 is characterized for operation over the full military temperature range –55°C to 125°C. The SN74HC74 is characterized for operation from –40°C to 85°C. 4 NC – No internal connection FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK D Q Q L H X X H L H L X X L L X X L H† H H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B – DECEMBER 1982 – REVISED MAY 1997 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 S 3 5 C1 2 6 1D 1 1Q 1Q R 10 9 11 12 8 13 2Q 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. logic diagram (positive logic) PRE CLK C C Q TG C C C C C D TG TG TG Q C C C CLR absolute maximum ratings over operating free-air temperature range‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B – DECEMBER 1982 – REVISED MAY 1997 recommended operating conditions SN54HC74 VCC Supply voltage VIH VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage Input transition (rise and fall) time TA Operating free-air temperature NOM MAX 2 5 6 VCC = 2 V VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V tt SN74HC74 MIN UNIT V V 4.2 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC 0 1000 0 1000 0 500 0 500 0 400 0 400 –55 125 –40 85 V V V ns °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS Ci TA = 25°C TYP MAX SN54HC74 SN74HC74 MIN MIN MAX MAX UNIT 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –4 mA IOH = –5.2 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 4 80 40 µA 3 10 10 10 pF VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, MIN IOH = –20 µA IOL = 4 mA IOL = 5.2 mA II ICC VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V V 3 SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B – DECEMBER 1982 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency PRE or CLR low tw Pulse duration CLK high or low Data ↑ Setup time before CLK↑ tsu PRE or CLR inactive Hold time, data after CLK↑ ↑ th TA = 25°C MIN MAX SN54HC74 SN74HC74 MIN MAX MIN MAX 2V 0 6 0 4.2 0 5 4.5 V 0 31 0 21 0 25 6V 0 36 0 25 0 29 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 25 40 30 4.5 V 5 8 6 6V 4 7 5 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd d CLK tt Q or Q Q or Q VCC TA = 25°C MIN TYP MAX SN54HC74 SN74HC74 MIN MIN MAX 2V 6 10 4.2 5 4.5 V 31 50 21 25 6V 36 60 25 29 MAX UNIT MHz 2V 70 230 345 290 4.5 V 20 46 69 58 6V 15 39 59 49 2V 70 175 250 220 4.5 V 20 35 50 44 6V 15 30 42 37 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 35 UNIT pF SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B – DECEMBER 1982 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point VCC High-Level Pulse 50% 50% 0V CL = 50 pF (see Note A) tw VCC Low-Level Pulse LOAD CIRCUIT 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS Reference Input VCC 50% Input VCC 50% 50% 0V 0V tsu Data Input 50% 10% 90% tr th tPLH 90% VCC 50% 10% 0 V In-Phase Output 90% 90% tr tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% 10% tPHL tPHL Out-of-Phase Output 90% VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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Copyright  1998, Texas Instruments Incorporated 1 of 3 Products Development Tools Applications Search PRODUCT FOLDER | PRODUCT INFO: FEATURES | DESCRIPTION | DATASHEETS | PRICING/AVAILABILITY | APPLICATION NOTES | RELATED DOCUMENTS PRODUCT SUPPORT: TRAINING SN74HC74, Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset DEVICE STATUS: ACTIVE PARAMETER NAME SN74HC74 Voltage Nodes (V) 6, 5, 2 Vcc range (V) 2.0 to 6.0 Input Level CMOS Output Level CMOS Output Drive (mA) -4/4 Output 3S No. of Bits 2 Static Current 0.04 th (ns) 0 tpd(max) (ns) 37 tsu (ns) 21 FEATURES l Back to Top Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs DESCRIPTION Back to Top The 'HC74 contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE\) or clear (CLR\) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SN54HC74 is characterized for operation over the full military temperature range -55°C to 2 of 3 125°C. The SN74HC74 is characterized for operation from -40°C to 85°C. Back to Top TECHNICAL DOCUMENTS To view the following documents, Acrobat Reader 3.x is required. To download a document to your hard drive, right-click on the link and choose 'Save'. Back to Top DATASHEET Full datasheet in Acrobat PDF: scls094b.pdf (96 KB) ( Updated: 05/01/1997) Full datasheet in Zipped PostScript: scls094b.psz (97 KB) Back to Top APPLICATION NOTES View Application Reports for Digital Logic l l l l l l l l CMOS Power Consumption and CPD Calculation (SCAA035B - Updated: 06/01/1997) Designing With Logic (SDYA009C - Updated: 06/01/1997) HCMOS Design Considerations (SCLA007 - Updated: 04/01/1996) Implications of Slow or Floating CMOS Inputs (SCBA004C - Updated: 02/01/1998) Input and Output Characteristics of Digital Integrated Circuits (SDYA010 - Updated: 10/01/1996) Live Insertion (SDYA012 - Updated: 10/01/1996) SN54/74HCT CMOS Logic Family Applications And Restrictions (SCLA011 - Updated: 05/01/1996) Using High Speed CMOS and Advanced CMOS In Systems With Multiple Vcc (SCLA008 Updated: 04/01/1996) Back to Top RELATED DOCUMENTS l l l l Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated: 05/06/1999) Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000) MicroStar Junior BGA Design Summary (SCET004, 167 KB - Updated: 07/28/2000) More Power In Less Space - Technical Article (SCAU001A, 850 KB - Updated: 03/01/1996) Back to Top PRICING/AVAILABILITY ORDERABLE DEVICE PACKAGE PINS TEMP (ºC) STATUS BUDGETARY PRICE US$/UNIT QTY=1000+ PACK QTY PRICING/AVAILABILITY SN74HC74ADBLE DB 14 -40 TO 85 OBSOLETE SN74HC74ADBR DB 14 -40 TO 85 ACTIVE 0.35 2000 Check stock or order SN74HC74D D 14 -40 TO 85 ACTIVE 0.27 50 Check stock or order SN74HC74DBLE DB 14 -40 TO 85 OBSOLETE SN74HC74DBR DB 14 -40 TO 85 ACTIVE 0.27 2000 Check stock or order SN74HC74DR D 14 ACTIVE 0.30 2500 Check stock or order -40 TO 3 of 3 85 SN74HC74N N 14 -40 TO 85 ACTIVE SN74HC74N3 N 14 -40 TO 85 OBSOLETE SN74HC74NSR NS 14 -40 TO 85 ACTIVE SN74HC74PWLE PW 14 -40 TO 85 OBSOLETE SN74HC74PWR PW 14 -40 TO 85 ACTIVE 0.25 25 Check stock or order 0.35 2000 Check stock or order 0.27 2000 Check stock or order Table Data Updated on: 11/16/2000 © Copyright 2000 Texas Instruments Incorporated. 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