SN74LVC16646ADGGR

SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 FEATURES • • • • • • • • • • DGG, DGV, OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V In Transparent Mode, Max tpd of 5.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) 1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE DESCRIPTION/ORDERING INFORMATION This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC16646A can be used as two 8-bit transceivers or one 16-bit transceiver. The device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING SN74LVC16646ADL Tape and reel SN74LVC16646ADLR TSSOP – DGG Tape and reel SN74LVC16646ADGGR LVC16646A TVSOP – DGV Tape and reel SN74LVC16646ADGVR LD646A SSOP – DL –40°C to 85°C ORDERABLE PART NUMBER Tube LVC16646A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2005, Texas Instruments Incorporated SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC16646A. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the other register. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE DATA I/O (1) INPUTS (1) 2 OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1-A8 B1-B8 X X ↑ X X X Input Unspecified Store A, B unspecified (1) X X X ↑ X X Unspecified Input Store B, A unspecified (1) H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input Input Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B Bus L H H or L X H X Input Output Stored A data to bus The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com OE L DIR L CLKAB CLKBA X X SAB X BUS B BUS A BUS A BUS B SCES408B – AUGUST 2002 – REVISED APRIL 2005 SBA L OE L DIR H DIR X X X CLKAB CLKBA ↑ X ↑ X ↑ ↑ STORAGE FROM A, B, OR A AND B SAB L SBA X BUS B BUS A BUS A OE X X H CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SAB SBA X X X X X X OE L L DIR L H CLKAB X H or L CLKBA H or L X SAB X H SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions 3 SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 56 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB To Seven Other Channels 29 28 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 1D C1 To Seven Other Channels 4 2B1 SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg (1) (2) (3) (4) DGG package 64 DGV package 48 DL package 56 Storage temperature range –65 V °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 1.5 Low-level input voltage VI VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 VO Output voltage IOH High-level output current 0.35 × VCC 0.7 VCC = 2.7 V to 3.6 V 0.8 0 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) V VCC = 2.3 V to 2.7 V Input voltage V 0.65 × VCC VCC = 1.65 V to 1.95 V VIL UNIT V V V mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V 24 –40 mA 10 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5 SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOL = 24 mA II Control inputs MAX VI = 0 to 5.5 V UNIT VCC – 0.2 IOH = –4 mA IOH = –12 mA VOL MIN TYP (1) VCC V V 3.6 V ±5 µA Ioff VI or VO = 5.5 V 0 ±10 µA IOZ (2) VO = 0 to 5.5 V 3.6 V ±10 µA VI = VCC or GND ICC 3.6 V ≤ VI ≤ 5.5 V (3) IO = 0 3.6 V One input at VCC – 0.6 V, Other inputs at VCC or GND ∆ICC 20 20 2.7 V to 3.6 V 500 µA µA Ci Control inputs VI = VCC or GND 3.3 V 5 pF Cio A or B ports VO = VCC or GND 3.3 V 8.5 pF (1) (2) (3) All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current, but not II(hold). This applies in the disabled state only. Timing Requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 1.8 V ± 0.15 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, A or B before CLKAB↑ or CLKBA↑ th Hold time, A or B after CLKAB↑ or CLKBA↑ 6 MAX VCC = 2.5 V ± 0.2 V MIN 85 MAX VCC = 2.7 V MIN 125 MAX VCC = 3.3 V ± 0.3 V MIN 150 UNIT MAX 150 MHz 5 4 3.3 3.3 ns 6.5 3.5 3 2.7 ns 0 0 0 0.3 ns SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) A or B B or A fmax tpd tdis ten tdis MIN MAX 85 CLKAB or CLKBA SAB or SBA ten VCC = 1.8 V ± 0.15 V A or B OE A or B DIR A or B VCC = 2.5 V ± 0.2 V MIN VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX 125 MIN MAX 150 MIN UNIT MAX 150 MHz 11.3 6.2 6 0.5 5.2 12.4 7.2 7 1.8 6 13.5 7.3 7 1.7 6.1 13 9.5 8.5 1.3 6.9 12 8.5 7.7 2.1 6.9 13 9.5 8.5 1.4 7.2 12 8.5 7.8 2 7 1 1 tsk(o) 1 ns ns ns ns Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 53 55 60 9 10 12 UNIT pF 7 SN74LVC16646A 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS www.ti.com SCES408B – AUGUST 2002 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH - V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 8 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74LVC16646ADGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16646A Samples SN74LVC16646ADL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16646A Samples SN74LVC16646ADLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVC16646A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of